1 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ 2 ; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM 3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ 4 ; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM 5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ 6 ; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM 7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ 8 ; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM 9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ 10 ; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM 11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ 12 ; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM 13 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ 14 ; RUN: -check-prefixes=GP32-MM,GP32,MM 15 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ 16 ; RUN: -check-prefixes=GP32-MM,GP32,MM 17 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ 18 ; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM 19 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ 20 ; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM 21 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ 22 ; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM 23 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ 24 ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM 25 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ 26 ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM 27 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ 28 ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM 29 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ 30 ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM 31 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ 32 ; RUN: -check-prefixes=GP64,MM 33 34 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) { 35 entry: 36 ; ALL-LABEL: sub_i1: 37 38 ; NOT-MM: subu $[[T0:[0-9]+]], $4, $5 39 ; NOT-MM: sll $[[T0]], $[[T0]], 31 40 ; NOT-MM: sra $2, $[[T0]], 31 41 42 ; MM: subu16 $[[T0:[0-9]+]], $4, $5 43 ; MM: sll $[[T1:[0-9]+]], $[[T0]], 31 44 ; MM: sra $[[T0]], $[[T1]], 31 45 46 %r = sub i1 %a, %b 47 ret i1 %r 48 } 49 50 define signext i8 @sub_i8(i8 signext %a, i8 signext %b) { 51 entry: 52 ; ALL-LABEL: sub_i8: 53 54 ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5 55 ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24 56 ; NOT-R2-R6: sra $2, $[[T0]], 24 57 58 ; R2-R6: subu $[[T0:[0-9]+]], $4, $5 59 ; R2-R6: seb $2, $[[T0:[0-9]+]] 60 61 ; MM: subu16 $[[T0:[0-9]+]], $4, $5 62 ; MM: seb $[[T0]], $[[T0]] 63 64 %r = sub i8 %a, %b 65 ret i8 %r 66 } 67 68 define signext i16 @sub_i16(i16 signext %a, i16 signext %b) { 69 entry: 70 ; ALL-LABEL: sub_i16: 71 72 ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5 73 ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16 74 ; NOT-R2-R6: sra $2, $[[T0]], 16 75 76 ; R2-R6: subu $[[T0:[0-9]+]], $4, $5 77 ; R2-R6: seh $2, $[[T0:[0-9]+]] 78 79 ; MM: subu16 $[[T0:[0-9]+]], $4, $5 80 ; MM: seh $[[T0]], $[[T0]] 81 82 %r = sub i16 %a, %b 83 ret i16 %r 84 } 85 86 define signext i32 @sub_i32(i32 signext %a, i32 signext %b) { 87 entry: 88 ; ALL-LABEL: sub_i32: 89 90 ; NOT-MM: subu $2, $4, $5 91 92 ; MM: subu16 $2, $4, $5 93 94 %r = sub i32 %a, %b 95 ret i32 %r 96 } 97 98 define signext i64 @sub_i64(i64 signext %a, i64 signext %b) { 99 entry: 100 ; ALL-LABEL: sub_i64: 101 102 ; GP32: subu $3, $5, $7 103 ; GP32: sltu $[[T0:[0-9]+]], $5, $7 104 ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6 105 ; GP32: subu $2, $4, $[[T1]] 106 107 ; GP64: dsubu $2, $4, $5 108 109 %r = sub i64 %a, %b 110 ret i64 %r 111 } 112 113 define signext i128 @sub_i128(i128 signext %a, i128 signext %b) { 114 entry: 115 ; ALL-LABEL: sub_i128: 116 117 ; GP32-NOT-MM: lw $[[T0:[0-9]+]], 20($sp) 118 ; GP32-NOT-MM: sltu $[[T1:[0-9]+]], $5, $[[T0]] 119 ; GP32-NOT-MM: lw $[[T2:[0-9]+]], 16($sp) 120 ; GP32-NOT-MM: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]] 121 ; GP32-NOT-MM: lw $[[T4:[0-9]+]], 24($sp) 122 ; GP32-NOT-MM: lw $[[T5:[0-9]+]], 28($sp) 123 ; GP32-NOT-MM: subu $[[T6:[0-9]+]], $7, $[[T5]] 124 ; GP32-NOT-MM: subu $2, $4, $[[T3]] 125 ; GP32-NOT-MM: sltu $[[T8:[0-9]+]], $6, $[[T4]] 126 ; GP32-NOT-MM: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]] 127 ; GP32-NOT-MM: subu $3, $5, $[[T9]] 128 ; GP32-NOT-MM: sltu $[[T10:[0-9]+]], $7, $[[T5]] 129 ; GP32-NOT-MM: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]] 130 ; GP32-NOT-MM: subu $4, $6, $[[T11]] 131 ; GP32-NOT-MM: move $5, $[[T6]] 132 133 ; GP32-MM: lw $[[T0:[0-9]+]], 20($sp) 134 ; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]] 135 ; GP32-MM: lw $[[T3:[0-9]+]], 16($sp) 136 ; GP32-MM: addu $[[T3]], $[[T1]], $[[T3]] 137 ; GP32-MM: lw $[[T4:[0-9]+]], 28($sp) 138 ; GP32-MM: subu $[[T1]], $7, $[[T4]] 139 ; GP32-MM: subu $[[T3]], $[[T5:[0-9]+]], $[[T3]] 140 ; GP32-MM: lw $[[T5]], 24($sp) 141 ; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]] 142 ; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]] 143 ; GP32-MM: subu $[[T0]], $5, $[[T0]] 144 ; GP32-MM: sltu $[[T2]], $7, $[[T4]] 145 ; GP32-MM: addu $[[T5]], $[[T2]], $[[T5]] 146 ; GP32-MM: subu $[[T5]], $6, $[[T5]] 147 ; GP32-MM: move $[[T2]], $[[T1]] 148 149 ; GP64: dsubu $3, $5, $7 150 ; GP64: sltu $[[T0:[0-9]+]], $5, $7 151 ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 152 ; GP64: dsubu $2, $4, $[[T1]] 153 154 %r = sub i128 %a, %b 155 ret i128 %r 156 } 157
