| /external/llvm/test/MC/ARM/ |
| neon-reciprocal-encoding.s | 23 @ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xf2]
24 vrsqrts.f32 d16, d16, d17
25 @ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xf2]
26 vrsqrts.f32 q8, q8, q9
|
| neont2-reciprocal-encoding.s | 25 @ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x0f]
26 vrsqrts.f32 d16, d16, d17
27 @ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x0f]
28 vrsqrts.f32 q8, q8, q9
|
| fullfp16-neon-neg.s | 180 vrsqrts.f16 d0, d1, d2
181 vrsqrts.f16 q0, q1, q2
|
| fullfp16-neon.s | 247 vrsqrts.f16 d0, d1, d2
248 vrsqrts.f16 q0, q1, q2
249 @ ARM: vrsqrts.f16 d0, d1, d2 @ encoding: [0x12,0x0f,0x31,0xf2]
250 @ ARM: vrsqrts.f16 q0, q1, q2 @ encoding: [0x54,0x0f,0x32,0xf2]
251 @ THUMB: vrsqrts.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x12,0x0f]
252 @ THUMB: vrsqrts.f16 q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x0f]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neon-reciprocal-encoding.s | 23 @ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xf2]
24 vrsqrts.f32 d16, d16, d17
25 @ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xf2]
26 vrsqrts.f32 q8, q8, q9
|
| neont2-reciprocal-encoding.s | 25 @ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x0f]
26 vrsqrts.f32 d16, d16, d17
27 @ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x0f]
28 vrsqrts.f32 q8, q8, q9
|
| /external/capstone/suite/MC/ARM/ |
| neon-reciprocal-encoding.s.cs | 12 0xb1,0x0f,0x60,0xf2 = vrsqrts.f32 d16, d16, d17
13 0xf2,0x0f,0x60,0xf2 = vrsqrts.f32 q8, q8, q9
|
| neont2-reciprocal-encoding.s.cs | 12 0x60,0xef,0xb1,0x0f = vrsqrts.f32 d16, d16, d17
13 0x60,0xef,0xf2,0x0f = vrsqrts.f32 q8, q8, q9
|
| /external/arm-neon-tests/ |
| ref_vrsqrts.c | 35 #define TEST_MSG "VRSQRTS/VRSQRTSQ"
40 /* Basic test: y=vrsqrts(x), then store the result. */
43 vrsqrts##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
|
| Android.mk | 40 vcalt vrecps vrsqrts vcvt
|
| Makefile.gcc | 61 vcalt vrecps vrsqrts vcvt
|
| Makefile | 55 vcalt vrecps vrsqrts vcvt
|
| /external/llvm/test/CodeGen/ARM/ |
| vrec.ll | 102 ;CHECK: vrsqrts.f32
105 %tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
111 ;CHECK: vrsqrts.f32
114 %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
118 declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
119 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
| 2009-11-01-NeonMoves.ll | 25 %10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1]
40 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| vrec.ll | 102 ;CHECK: vrsqrts.f32
105 %tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
111 ;CHECK: vrsqrts.f32
114 %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
118 declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
119 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
| 2009-11-01-NeonMoves.ll | 25 %10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1]
40 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| armv8-2-fp16-simd-thumb.d | 97 154: ef3a 8f1c vrsqrts.f16 d8, d10, d12
98 158: ef74 0ff8 vrsqrts.f16 q8, q10, q12
100 160: ef30 4f58 vrsqrts.f16 q2, q0, q4
|
| armv8-2-fp16-simd.d | 97 154: f23a8f1c vrsqrts.f16 d8, d10, d12
98 158: f2740ff8 vrsqrts.f16 q8, q10, q12
100 160: f2304f58 vrsqrts.f16 q2, q0, q4
|
| armv8-2-fp16-simd.s | 102 .irp op, vrecps.f16, vrsqrts.f16
|
| armv8-2-fp16-simd-warning.l | 87 [^:]*:202: Error: selected processor does not support fp16 instruction -- `vrsqrts.f16 d8,d10,d12'
88 [^:]*:202: Error: selected processor does not support fp16 instruction -- `vrsqrts.f16 q8,q10,q12'
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| fullfp16-neon-arm.txt | 158 # CHECK: vrsqrts.f16 d0, d1, d2
159 # CHECK: vrsqrts.f16 q0, q1, q2
|
| fullfp16-neon-thumb.txt | 158 # CHECK: vrsqrts.f16 d0, d1, d2
159 # CHECK: vrsqrts.f16 q0, q1, q2
|
| /external/valgrind/none/tests/arm/ |
| neon128.c | [all...] |
| neon64.c | [all...] |
| /external/clang/include/clang/Basic/ |
| arm_neon.td | 594 def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">;
[all...] |
