1 //===--- arm_neon.td - ARM NEON compiler interface ------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the TableGen definitions from which the ARM NEON header 11 // file will be generated. See ARM document DUI0348B. 12 // 13 //===----------------------------------------------------------------------===// 14 // 15 // Each intrinsic is a subclass of the Inst class. An intrinsic can either 16 // generate a __builtin_* call or it can expand to a set of generic operations. 17 // 18 // The operations are subclasses of Operation providing a list of DAGs, the 19 // last of which is the return value. The available DAG nodes are documented 20 // below. 21 // 22 //===----------------------------------------------------------------------===// 23 24 // The base Operation class. All operations must subclass this. 25 class Operation<list<dag> ops=[]> { 26 list<dag> Ops = ops; 27 bit Unavailable = 0; 28 } 29 // An operation that only contains a single DAG. 30 class Op<dag op> : Operation<[op]>; 31 // A shorter version of Operation - takes a list of DAGs. The last of these will 32 // be the return value. 33 class LOp<list<dag> ops> : Operation<ops>; 34 35 // These defs and classes are used internally to implement the SetTheory 36 // expansion and should be ignored. 37 foreach Index = 0-63 in 38 def sv##Index; 39 class MaskExpand; 40 41 //===----------------------------------------------------------------------===// 42 // Available operations 43 //===----------------------------------------------------------------------===// 44 45 // DAG arguments can either be operations (documented below) or variables. 46 // Variables are prefixed with '$'. There are variables for each input argument, 47 // with the name $pN, where N starts at zero. So the zero'th argument will be 48 // $p0, the first $p1 etc. 49 50 // op - Binary or unary operator, depending on the number of arguments. The 51 // operator itself is just treated as a raw string and is not checked. 52 // example: (op "+", $p0, $p1) -> "__p0 + __p1". 53 // (op "-", $p0) -> "-__p0" 54 def op; 55 // call - Invoke another intrinsic. The input types are type checked and 56 // disambiguated. If there is no intrinsic defined that takes 57 // the given types (or if there is a type ambiguity) an error is 58 // generated at tblgen time. The name of the intrinsic is the raw 59 // name as given to the Inst class (not mangled). 60 // example: (call "vget_high", $p0) -> "vgetq_high_s16(__p0)" 61 // (assuming $p0 has type int16x8_t). 62 def call; 63 // cast - Perform a cast to a different type. This gets emitted as a static 64 // C-style cast. For a pure reinterpret cast (T x = *(T*)&y), use 65 // "bitcast". 66 // 67 // The syntax is (cast MOD* VAL). The last argument is the value to 68 // cast, preceded by a sequence of type modifiers. The target type 69 // starts off as the type of VAL, and is modified by MOD in sequence. 70 // The available modifiers are: 71 // - $X - Take the type of parameter/variable X. For example: 72 // (cast $p0, $p1) would cast $p1 to the type of $p0. 73 // - "R" - The type of the return type. 74 // - A typedef string - A NEON or stdint.h type that is then parsed. 75 // for example: (cast "uint32x4_t", $p0). 76 // - "U" - Make the type unsigned. 77 // - "S" - Make the type signed. 78 // - "H" - Halve the number of lanes in the type. 79 // - "D" - Double the number of lanes in the type. 80 // - "8" - Convert type to an equivalent vector of 8-bit signed 81 // integers. 82 // example: (cast "R", "U", $p0) -> "(uint32x4_t)__p0" (assuming the return 83 // value is of type "int32x4_t". 84 // (cast $p0, "D", "8", $p1) -> "(int8x16_t)__p1" (assuming __p0 85 // has type float64x1_t or any other vector type of 64 bits). 86 // (cast "int32_t", $p2) -> "(int32_t)__p2" 87 def cast; 88 // bitcast - Same as "cast", except a reinterpret-cast is produced: 89 // (bitcast "T", $p0) -> "*(T*)&__p0". 90 // The VAL argument is saved to a temporary so it can be used 91 // as an l-value. 92 def bitcast; 93 // dup - Take a scalar argument and create a vector by duplicating it into 94 // all lanes. The type of the vector is the base type of the intrinsic. 95 // example: (dup $p1) -> "(uint32x2_t) {__p1, __p1}" (assuming the base type 96 // is uint32x2_t). 97 def dup; 98 // splat - Take a vector and a lane index, and return a vector of the same type 99 // containing repeated instances of the source vector at the lane index. 100 // example: (splat $p0, $p1) -> 101 // "__builtin_shufflevector(__p0, __p0, __p1, __p1, __p1, __p1)" 102 // (assuming __p0 has four elements). 103 def splat; 104 // save_temp - Create a temporary (local) variable. The variable takes a name 105 // based on the zero'th parameter and can be referenced using 106 // using that name in subsequent DAGs in the same 107 // operation. The scope of a temp is the operation. If a variable 108 // with the given name already exists, an error will be given at 109 // tblgen time. 110 // example: [(save_temp $var, (call "foo", $p0)), 111 // (op "+", $var, $p1)] -> 112 // "int32x2_t __var = foo(__p0); return __var + __p1;" 113 def save_temp; 114 // name_replace - Return the name of the current intrinsic with the first 115 // argument replaced by the second argument. Raises an error if 116 // the first argument does not exist in the intrinsic name. 117 // example: (call (name_replace "_high_", "_"), $p0) (to call the non-high 118 // version of this intrinsic). 119 def name_replace; 120 // literal - Create a literal piece of code. The code is treated as a raw 121 // string, and must be given a type. The type is a stdint.h or 122 // NEON intrinsic type as given to (cast). 123 // example: (literal "int32_t", "0") 124 def literal; 125 // shuffle - Create a vector shuffle. The syntax is (shuffle ARG0, ARG1, MASK). 126 // The MASK argument is a set of elements. The elements are generated 127 // from the two special defs "mask0" and "mask1". "mask0" expands to 128 // the lane indices in sequence for ARG0, and "mask1" expands to 129 // the lane indices in sequence for ARG1. They can be used as-is, e.g. 130 // 131 // (shuffle $p0, $p1, mask0) -> $p0 132 // (shuffle $p0, $p1, mask1) -> $p1 133 // 134 // or, more usefully, they can be manipulated using the SetTheory 135 // operators plus some extra operators defined in the NEON emitter. 136 // The operators are described below. 137 // example: (shuffle $p0, $p1, (add (highhalf mask0), (highhalf mask1))) -> 138 // A concatenation of the high halves of the input vectors. 139 def shuffle; 140 141 // add, interleave, decimate: These set operators are vanilla SetTheory 142 // operators and take their normal definition. 143 def add; 144 def interleave; 145 def decimate; 146 // rotl - Rotate set left by a number of elements. 147 // example: (rotl mask0, 3) -> [3, 4, 5, 6, 0, 1, 2] 148 def rotl; 149 // rotl - Rotate set right by a number of elements. 150 // example: (rotr mask0, 3) -> [4, 5, 6, 0, 1, 2, 3] 151 def rotr; 152 // highhalf - Take only the high half of the input. 153 // example: (highhalf mask0) -> [4, 5, 6, 7] (assuming mask0 had 8 elements) 154 def highhalf; 155 // highhalf - Take only the low half of the input. 156 // example: (lowhalf mask0) -> [0, 1, 2, 3] (assuming mask0 had 8 elements) 157 def lowhalf; 158 // rev - Perform a variable-width reversal of the elements. The zero'th argument 159 // is a width in bits to reverse. The lanes this maps to is determined 160 // based on the element width of the underlying type. 161 // example: (rev 32, mask0) -> [3, 2, 1, 0, 7, 6, 5, 4] (if 8-bit elements) 162 // example: (rev 32, mask0) -> [1, 0, 3, 2] (if 16-bit elements) 163 def rev; 164 // mask0 - The initial sequence of lanes for shuffle ARG0 165 def mask0 : MaskExpand; 166 // mask0 - The initial sequence of lanes for shuffle ARG1 167 def mask1 : MaskExpand; 168 169 def OP_NONE : Operation; 170 def OP_UNAVAILABLE : Operation { 171 let Unavailable = 1; 172 } 173 174 //===----------------------------------------------------------------------===// 175 // Instruction definitions 176 //===----------------------------------------------------------------------===// 177 178 // Every intrinsic subclasses "Inst". An intrinsic has a name, a prototype and 179 // a sequence of typespecs. 180 // 181 // The name is the base name of the intrinsic, for example "vget_lane". This is 182 // then mangled by the tblgen backend to add type information ("vget_lane_s16"). 183 // 184 // A typespec is a sequence of uppercase characters (modifiers) followed by one 185 // lowercase character. A typespec encodes a particular "base type" of the 186 // intrinsic. 187 // 188 // An example typespec is "Qs" - quad-size short - uint16x8_t. The available 189 // typespec codes are given below. 190 // 191 // The string given to an Inst class is a sequence of typespecs. The intrinsic 192 // is instantiated for every typespec in the sequence. For example "sdQsQd". 193 // 194 // The prototype is a string that defines the return type of the intrinsic 195 // and the type of each argument. The return type and every argument gets a 196 // "modifier" that can change in some way the "base type" of the intrinsic. 197 // 198 // The modifier 'd' means "default" and does not modify the base type in any 199 // way. The available modifiers are given below. 200 // 201 // Typespecs 202 // --------- 203 // c: char 204 // s: short 205 // i: int 206 // l: long 207 // k: 128-bit long 208 // f: float 209 // h: half-float 210 // d: double 211 // 212 // Typespec modifiers 213 // ------------------ 214 // S: scalar, only used for function mangling. 215 // U: unsigned 216 // Q: 128b 217 // H: 128b without mangling 'q' 218 // P: polynomial 219 // 220 // Prototype modifiers 221 // ------------------- 222 // prototype: return (arg, arg, ...) 223 // 224 // v: void 225 // t: best-fit integer (int/poly args) 226 // x: signed integer (int/float args) 227 // u: unsigned integer (int/float args) 228 // f: float (int args) 229 // F: double (int args) 230 // d: default 231 // g: default, ignore 'Q' size modifier. 232 // j: default, force 'Q' size modifier. 233 // w: double width elements, same num elts 234 // n: double width elements, half num elts 235 // h: half width elements, double num elts 236 // q: half width elements, quad num elts 237 // e: half width elements, double num elts, unsigned 238 // m: half width elements, same num elts 239 // i: constant int 240 // l: constant uint64 241 // s: scalar of element type 242 // z: scalar of half width element type, signed 243 // r: scalar of double width element type, signed 244 // a: scalar of element type (splat to vector type) 245 // b: scalar of unsigned integer/long type (int/float args) 246 // $: scalar of signed integer/long type (int/float args) 247 // y: scalar of float 248 // o: scalar of double 249 // k: default elt width, double num elts 250 // 2,3,4: array of default vectors 251 // B,C,D: array of default elts, force 'Q' size modifier. 252 // p: pointer type 253 // c: const pointer type 254 255 // Every intrinsic subclasses Inst. 256 class Inst <string n, string p, string t, Operation o> { 257 string Name = n; 258 string Prototype = p; 259 string Types = t; 260 string ArchGuard = ""; 261 262 Operation Operation = o; 263 bit CartesianProductOfTypes = 0; 264 bit BigEndianSafe = 0; 265 bit isShift = 0; 266 bit isScalarShift = 0; 267 bit isScalarNarrowShift = 0; 268 bit isVCVT_N = 0; 269 // For immediate checks: the immediate will be assumed to specify the lane of 270 // a Q register. Only used for intrinsics which end up calling polymorphic 271 // builtins. 272 bit isLaneQ = 0; 273 274 // Certain intrinsics have different names than their representative 275 // instructions. This field allows us to handle this correctly when we 276 // are generating tests. 277 string InstName = ""; 278 279 // Certain intrinsics even though they are not a WOpInst or LOpInst, 280 // generate a WOpInst/LOpInst instruction (see below for definition 281 // of a WOpInst/LOpInst). For testing purposes we need to know 282 // this. Ex: vset_lane which outputs vmov instructions. 283 bit isHiddenWInst = 0; 284 bit isHiddenLInst = 0; 285 } 286 287 // The following instruction classes are implemented via builtins. 288 // These declarations are used to generate Builtins.def: 289 // 290 // SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8") 291 // IInst: Instruction with generic integer suffix (e.g., "i8") 292 // WInst: Instruction with only bit size suffix (e.g., "8") 293 class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 294 class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 295 class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 296 297 // The following instruction classes are implemented via operators 298 // instead of builtins. As such these declarations are only used for 299 // the purpose of generating tests. 300 // 301 // SOpInst: Instruction with signed/unsigned suffix (e.g., "s8", 302 // "u8", "p8"). 303 // IOpInst: Instruction with generic integer suffix (e.g., "i8"). 304 // WOpInst: Instruction with bit size only suffix (e.g., "8"). 305 // LOpInst: Logical instruction with no bit size suffix. 306 // NoTestOpInst: Intrinsic that has no corresponding instruction. 307 class SOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 308 class IOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 309 class WOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 310 class LOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 311 class NoTestOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 312 313 //===----------------------------------------------------------------------===// 314 // Operations 315 //===----------------------------------------------------------------------===// 316 317 def OP_ADD : Op<(op "+", $p0, $p1)>; 318 def OP_ADDL : Op<(op "+", (call "vmovl", $p0), (call "vmovl", $p1))>; 319 def OP_ADDLHi : Op<(op "+", (call "vmovl_high", $p0), 320 (call "vmovl_high", $p1))>; 321 def OP_ADDW : Op<(op "+", $p0, (call "vmovl", $p1))>; 322 def OP_ADDWHi : Op<(op "+", $p0, (call "vmovl_high", $p1))>; 323 def OP_SUB : Op<(op "-", $p0, $p1)>; 324 def OP_SUBL : Op<(op "-", (call "vmovl", $p0), (call "vmovl", $p1))>; 325 def OP_SUBLHi : Op<(op "-", (call "vmovl_high", $p0), 326 (call "vmovl_high", $p1))>; 327 def OP_SUBW : Op<(op "-", $p0, (call "vmovl", $p1))>; 328 def OP_SUBWHi : Op<(op "-", $p0, (call "vmovl_high", $p1))>; 329 def OP_MUL : Op<(op "*", $p0, $p1)>; 330 def OP_MLA : Op<(op "+", $p0, (op "*", $p1, $p2))>; 331 def OP_MLAL : Op<(op "+", $p0, (call "vmull", $p1, $p2))>; 332 def OP_MULLHi : Op<(call "vmull", (call "vget_high", $p0), 333 (call "vget_high", $p1))>; 334 def OP_MULLHi_P64 : Op<(call "vmull", 335 (cast "poly64_t", (call "vget_high", $p0)), 336 (cast "poly64_t", (call "vget_high", $p1)))>; 337 def OP_MULLHi_N : Op<(call "vmull_n", (call "vget_high", $p0), $p1)>; 338 def OP_MLALHi : Op<(call "vmlal", $p0, (call "vget_high", $p1), 339 (call "vget_high", $p2))>; 340 def OP_MLALHi_N : Op<(call "vmlal_n", $p0, (call "vget_high", $p1), $p2)>; 341 def OP_MLS : Op<(op "-", $p0, (op "*", $p1, $p2))>; 342 def OP_FMLS : Op<(call "vfma", $p0, (op "-", $p1), $p2)>; 343 def OP_MLSL : Op<(op "-", $p0, (call "vmull", $p1, $p2))>; 344 def OP_MLSLHi : Op<(call "vmlsl", $p0, (call "vget_high", $p1), 345 (call "vget_high", $p2))>; 346 def OP_MLSLHi_N : Op<(call "vmlsl_n", $p0, (call "vget_high", $p1), $p2)>; 347 def OP_MUL_N : Op<(op "*", $p0, (dup $p1))>; 348 def OP_MLA_N : Op<(op "+", $p0, (op "*", $p1, (dup $p2)))>; 349 def OP_MLS_N : Op<(op "-", $p0, (op "*", $p1, (dup $p2)))>; 350 def OP_FMLA_N : Op<(call "vfma", $p0, $p1, (dup $p2))>; 351 def OP_FMLS_N : Op<(call "vfma", $p0, (op "-", $p1), (dup $p2))>; 352 def OP_MLAL_N : Op<(op "+", $p0, (call "vmull", $p1, (dup $p2)))>; 353 def OP_MLSL_N : Op<(op "-", $p0, (call "vmull", $p1, (dup $p2)))>; 354 def OP_MUL_LN : Op<(op "*", $p0, (splat $p1, $p2))>; 355 def OP_MULX_LN : Op<(call "vmulx", $p0, (splat $p1, $p2))>; 356 def OP_MULL_LN : Op<(call "vmull", $p0, (splat $p1, $p2))>; 357 def OP_MULLHi_LN: Op<(call "vmull", (call "vget_high", $p0), (splat $p1, $p2))>; 358 def OP_MLA_LN : Op<(op "+", $p0, (op "*", $p1, (splat $p2, $p3)))>; 359 def OP_MLS_LN : Op<(op "-", $p0, (op "*", $p1, (splat $p2, $p3)))>; 360 def OP_MLAL_LN : Op<(op "+", $p0, (call "vmull", $p1, (splat $p2, $p3)))>; 361 def OP_MLALHi_LN: Op<(op "+", $p0, (call "vmull", (call "vget_high", $p1), 362 (splat $p2, $p3)))>; 363 def OP_MLSL_LN : Op<(op "-", $p0, (call "vmull", $p1, (splat $p2, $p3)))>; 364 def OP_MLSLHi_LN : Op<(op "-", $p0, (call "vmull", (call "vget_high", $p1), 365 (splat $p2, $p3)))>; 366 def OP_QDMULL_LN : Op<(call "vqdmull", $p0, (splat $p1, $p2))>; 367 def OP_QDMULLHi_LN : Op<(call "vqdmull", (call "vget_high", $p0), 368 (splat $p1, $p2))>; 369 def OP_QDMLAL_LN : Op<(call "vqdmlal", $p0, $p1, (splat $p2, $p3))>; 370 def OP_QDMLALHi_LN : Op<(call "vqdmlal", $p0, (call "vget_high", $p1), 371 (splat $p2, $p3))>; 372 def OP_QDMLSL_LN : Op<(call "vqdmlsl", $p0, $p1, (splat $p2, $p3))>; 373 def OP_QDMLSLHi_LN : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1), 374 (splat $p2, $p3))>; 375 def OP_QDMULH_LN : Op<(call "vqdmulh", $p0, (splat $p1, $p2))>; 376 def OP_QRDMULH_LN : Op<(call "vqrdmulh", $p0, (splat $p1, $p2))>; 377 def OP_QRDMLAH : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, $p2))>; 378 def OP_QRDMLSH : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, $p2))>; 379 def OP_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>; 380 def OP_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>; 381 def OP_FMS_LN : Op<(call "vfma_lane", $p0, (op "-", $p1), $p2, $p3)>; 382 def OP_FMS_LNQ : Op<(call "vfma_laneq", $p0, (op "-", $p1), $p2, $p3)>; 383 def OP_TRN1 : Op<(shuffle $p0, $p1, (interleave (decimate mask0, 2), 384 (decimate mask1, 2)))>; 385 def OP_ZIP1 : Op<(shuffle $p0, $p1, (lowhalf (interleave mask0, mask1)))>; 386 def OP_UZP1 : Op<(shuffle $p0, $p1, (add (decimate mask0, 2), 387 (decimate mask1, 2)))>; 388 def OP_TRN2 : Op<(shuffle $p0, $p1, (interleave 389 (decimate (rotl mask0, 1), 2), 390 (decimate (rotl mask1, 1), 2)))>; 391 def OP_ZIP2 : Op<(shuffle $p0, $p1, (highhalf (interleave mask0, mask1)))>; 392 def OP_UZP2 : Op<(shuffle $p0, $p1, (add (decimate (rotl mask0, 1), 2), 393 (decimate (rotl mask1, 1), 2)))>; 394 def OP_EQ : Op<(cast "R", (op "==", $p0, $p1))>; 395 def OP_GE : Op<(cast "R", (op ">=", $p0, $p1))>; 396 def OP_LE : Op<(cast "R", (op "<=", $p0, $p1))>; 397 def OP_GT : Op<(cast "R", (op ">", $p0, $p1))>; 398 def OP_LT : Op<(cast "R", (op "<", $p0, $p1))>; 399 def OP_NEG : Op<(op "-", $p0)>; 400 def OP_NOT : Op<(op "~", $p0)>; 401 def OP_AND : Op<(op "&", $p0, $p1)>; 402 def OP_OR : Op<(op "|", $p0, $p1)>; 403 def OP_XOR : Op<(op "^", $p0, $p1)>; 404 def OP_ANDN : Op<(op "&", $p0, (op "~", $p1))>; 405 def OP_ORN : Op<(op "|", $p0, (op "~", $p1))>; 406 def OP_CAST : Op<(cast "R", $p0)>; 407 def OP_HI : Op<(shuffle $p0, $p0, (highhalf mask0))>; 408 def OP_LO : Op<(shuffle $p0, $p0, (lowhalf mask0))>; 409 def OP_CONC : Op<(shuffle $p0, $p1, (add mask0, mask1))>; 410 def OP_DUP : Op<(dup $p0)>; 411 def OP_DUP_LN : Op<(splat $p0, $p1)>; 412 def OP_SEL : Op<(cast "R", (op "|", 413 (op "&", $p0, (cast $p0, $p1)), 414 (op "&", (op "~", $p0), (cast $p0, $p2))))>; 415 def OP_REV16 : Op<(shuffle $p0, $p0, (rev 16, mask0))>; 416 def OP_REV32 : Op<(shuffle $p0, $p0, (rev 32, mask0))>; 417 def OP_REV64 : Op<(shuffle $p0, $p0, (rev 64, mask0))>; 418 def OP_XTN : Op<(call "vcombine", $p0, (call "vmovn", $p1))>; 419 def OP_SQXTUN : Op<(call "vcombine", (cast $p0, "U", $p0), 420 (call "vqmovun", $p1))>; 421 def OP_QXTN : Op<(call "vcombine", $p0, (call "vqmovn", $p1))>; 422 def OP_VCVT_NA_HI_F16 : Op<(call "vcombine", $p0, (call "vcvt_f16_f32", $p1))>; 423 def OP_VCVT_NA_HI_F32 : Op<(call "vcombine", $p0, (call "vcvt_f32_f64", $p1))>; 424 def OP_VCVT_EX_HI_F32 : Op<(call "vcvt_f32_f16", (call "vget_high", $p0))>; 425 def OP_VCVT_EX_HI_F64 : Op<(call "vcvt_f64_f32", (call "vget_high", $p0))>; 426 def OP_VCVTX_HI : Op<(call "vcombine", $p0, (call "vcvtx_f32", $p1))>; 427 def OP_REINT : Op<(cast "R", $p0)>; 428 def OP_ADDHNHi : Op<(call "vcombine", $p0, (call "vaddhn", $p1, $p2))>; 429 def OP_RADDHNHi : Op<(call "vcombine", $p0, (call "vraddhn", $p1, $p2))>; 430 def OP_SUBHNHi : Op<(call "vcombine", $p0, (call "vsubhn", $p1, $p2))>; 431 def OP_RSUBHNHi : Op<(call "vcombine", $p0, (call "vrsubhn", $p1, $p2))>; 432 def OP_ABDL : Op<(cast "R", (call "vmovl", (cast $p0, "U", 433 (call "vabd", $p0, $p1))))>; 434 def OP_ABDLHi : Op<(call "vabdl", (call "vget_high", $p0), 435 (call "vget_high", $p1))>; 436 def OP_ABA : Op<(op "+", $p0, (call "vabd", $p1, $p2))>; 437 def OP_ABAL : Op<(op "+", $p0, (call "vabdl", $p1, $p2))>; 438 def OP_ABALHi : Op<(call "vabal", $p0, (call "vget_high", $p1), 439 (call "vget_high", $p2))>; 440 def OP_QDMULLHi : Op<(call "vqdmull", (call "vget_high", $p0), 441 (call "vget_high", $p1))>; 442 def OP_QDMULLHi_N : Op<(call "vqdmull_n", (call "vget_high", $p0), $p1)>; 443 def OP_QDMLALHi : Op<(call "vqdmlal", $p0, (call "vget_high", $p1), 444 (call "vget_high", $p2))>; 445 def OP_QDMLALHi_N : Op<(call "vqdmlal_n", $p0, (call "vget_high", $p1), $p2)>; 446 def OP_QDMLSLHi : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1), 447 (call "vget_high", $p2))>; 448 def OP_QDMLSLHi_N : Op<(call "vqdmlsl_n", $p0, (call "vget_high", $p1), $p2)>; 449 def OP_DIV : Op<(op "/", $p0, $p1)>; 450 def OP_LONG_HI : Op<(cast "R", (call (name_replace "_high_", "_"), 451 (call "vget_high", $p0), $p1))>; 452 def OP_NARROW_HI : Op<(cast "R", (call "vcombine", 453 (cast "R", "H", $p0), 454 (cast "R", "H", 455 (call (name_replace "_high_", "_"), 456 $p1, $p2))))>; 457 def OP_MOVL_HI : LOp<[(save_temp $a1, (call "vget_high", $p0)), 458 (cast "R", 459 (call "vshll_n", $a1, (literal "int32_t", "0")))]>; 460 def OP_COPY_LN : Op<(call "vset_lane", (call "vget_lane", $p2, $p3), $p0, $p1)>; 461 def OP_SCALAR_MUL_LN : Op<(op "*", $p0, (call "vget_lane", $p1, $p2))>; 462 def OP_SCALAR_MULX_LN : Op<(call "vmulx", $p0, (call "vget_lane", $p1, $p2))>; 463 def OP_SCALAR_VMULX_LN : LOp<[(save_temp $x, (call "vget_lane", $p0, 464 (literal "int32_t", "0"))), 465 (save_temp $y, (call "vget_lane", $p1, $p2)), 466 (save_temp $z, (call "vmulx", $x, $y)), 467 (call "vset_lane", $z, $p0, $p2)]>; 468 def OP_SCALAR_VMULX_LNQ : LOp<[(save_temp $x, (call "vget_lane", $p0, 469 (literal "int32_t", "0"))), 470 (save_temp $y, (call "vget_lane", $p1, $p2)), 471 (save_temp $z, (call "vmulx", $x, $y)), 472 (call "vset_lane", $z, $p0, (literal "int32_t", 473 "0"))]>; 474 class ScalarMulOp<string opname> : 475 Op<(call opname, $p0, (call "vget_lane", $p1, $p2))>; 476 477 def OP_SCALAR_QDMULL_LN : ScalarMulOp<"vqdmull">; 478 def OP_SCALAR_QDMULH_LN : ScalarMulOp<"vqdmulh">; 479 def OP_SCALAR_QRDMULH_LN : ScalarMulOp<"vqrdmulh">; 480 481 def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, 482 (call "vget_lane", $p2, $p3)))>; 483 def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, 484 (call "vget_lane", $p2, $p3)))>; 485 486 def OP_SCALAR_HALF_GET_LN : Op<(bitcast "float16_t", 487 (call "vget_lane", 488 (bitcast "int16x4_t", $p0), $p1))>; 489 def OP_SCALAR_HALF_GET_LNQ : Op<(bitcast "float16_t", 490 (call "vget_lane", 491 (bitcast "int16x8_t", $p0), $p1))>; 492 def OP_SCALAR_HALF_SET_LN : Op<(bitcast "float16x4_t", 493 (call "vset_lane", 494 (bitcast "int16_t", $p0), 495 (bitcast "int16x4_t", $p1), $p2))>; 496 def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast "float16x8_t", 497 (call "vset_lane", 498 (bitcast "int16_t", $p0), 499 (bitcast "int16x8_t", $p1), $p2))>; 500 501 //===----------------------------------------------------------------------===// 502 // Instructions 503 //===----------------------------------------------------------------------===// 504 505 //////////////////////////////////////////////////////////////////////////////// 506 // E.3.1 Addition 507 def VADD : IOpInst<"vadd", "ddd", 508 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>; 509 def VADDL : SOpInst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>; 510 def VADDW : SOpInst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>; 511 def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 512 def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 513 def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 514 def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">; 515 def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">; 516 517 //////////////////////////////////////////////////////////////////////////////// 518 // E.3.2 Multiplication 519 def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>; 520 def VMULP : SInst<"vmul", "ddd", "PcQPc">; 521 def VMLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>; 522 def VMLAL : SOpInst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>; 523 def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>; 524 def VMLSL : SOpInst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>; 525 def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">; 526 def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">; 527 528 let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in { 529 def VQRDMLAH : SOpInst<"vqrdmlah", "dddd", "siQsQi", OP_QRDMLAH>; 530 def VQRDMLSH : SOpInst<"vqrdmlsh", "dddd", "siQsQi", OP_QRDMLSH>; 531 } 532 533 def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">; 534 def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">; 535 def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">; 536 def VQDMULL : SInst<"vqdmull", "wdd", "si">; 537 538 //////////////////////////////////////////////////////////////////////////////// 539 // E.3.3 Subtraction 540 def VSUB : IOpInst<"vsub", "ddd", 541 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>; 542 def VSUBL : SOpInst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>; 543 def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>; 544 def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 545 def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 546 def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">; 547 def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">; 548 549 //////////////////////////////////////////////////////////////////////////////// 550 // E.3.4 Comparison 551 def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>; 552 def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>; 553 let InstName = "vcge" in 554 def VCLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>; 555 def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>; 556 let InstName = "vcgt" in 557 def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>; 558 let InstName = "vacge" in { 559 def VCAGE : IInst<"vcage", "udd", "fQf">; 560 def VCALE : IInst<"vcale", "udd", "fQf">; 561 } 562 let InstName = "vacgt" in { 563 def VCAGT : IInst<"vcagt", "udd", "fQf">; 564 def VCALT : IInst<"vcalt", "udd", "fQf">; 565 } 566 def VTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">; 567 568 //////////////////////////////////////////////////////////////////////////////// 569 // E.3.5 Absolute Difference 570 def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 571 def VABDL : SOpInst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>; 572 def VABA : SOpInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>; 573 def VABAL : SOpInst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>; 574 575 //////////////////////////////////////////////////////////////////////////////// 576 // E.3.6 Max/Min 577 def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 578 def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 579 580 //////////////////////////////////////////////////////////////////////////////// 581 // E.3.7 Pairwise Addition 582 def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">; 583 def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">; 584 def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">; 585 586 //////////////////////////////////////////////////////////////////////////////// 587 // E.3.8-9 Folding Max/Min 588 def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">; 589 def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">; 590 591 //////////////////////////////////////////////////////////////////////////////// 592 // E.3.10 Reciprocal/Sqrt 593 def VRECPS : IInst<"vrecps", "ddd", "fQf">; 594 def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">; 595 596 //////////////////////////////////////////////////////////////////////////////// 597 // E.3.11 Shifts by signed variable 598 def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 599 def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 600 def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 601 def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 602 603 //////////////////////////////////////////////////////////////////////////////// 604 // E.3.12 Shifts by constant 605 let isShift = 1 in { 606 def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 607 def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 608 def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 609 def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 610 def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 611 def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 612 def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">; 613 def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">; 614 def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">; 615 def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">; 616 def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">; 617 def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">; 618 def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">; 619 def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">; 620 621 //////////////////////////////////////////////////////////////////////////////// 622 // E.3.13 Shifts with insert 623 def VSRI_N : WInst<"vsri_n", "dddi", 624 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 625 def VSLI_N : WInst<"vsli_n", "dddi", 626 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 627 } 628 629 //////////////////////////////////////////////////////////////////////////////// 630 // E.3.14 Loads and stores of a single vector 631 def VLD1 : WInst<"vld1", "dc", 632 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 633 def VLD1_LANE : WInst<"vld1_lane", "dcdi", 634 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 635 def VLD1_DUP : WInst<"vld1_dup", "dc", 636 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 637 def VST1 : WInst<"vst1", "vpd", 638 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 639 def VST1_LANE : WInst<"vst1_lane", "vpdi", 640 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 641 642 //////////////////////////////////////////////////////////////////////////////// 643 // E.3.15 Loads and stores of an N-element structure 644 def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 645 def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 646 def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 647 def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">; 648 def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">; 649 def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">; 650 def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 651 def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 652 def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 653 def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 654 def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 655 def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 656 def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 657 def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 658 def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 659 660 //////////////////////////////////////////////////////////////////////////////// 661 // E.3.16 Extract lanes from a vector 662 let InstName = "vmov" in 663 def VGET_LANE : IInst<"vget_lane", "sdi", 664 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 665 666 //////////////////////////////////////////////////////////////////////////////// 667 // E.3.17 Set lanes within a vector 668 let InstName = "vmov" in 669 def VSET_LANE : IInst<"vset_lane", "dsdi", 670 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 671 672 //////////////////////////////////////////////////////////////////////////////// 673 // E.3.18 Initialize a vector from bit pattern 674 def VCREATE : NoTestOpInst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST> { 675 let BigEndianSafe = 1; 676 } 677 678 //////////////////////////////////////////////////////////////////////////////// 679 // E.3.19 Set all lanes to same value 680 let InstName = "vmov" in { 681 def VDUP_N : WOpInst<"vdup_n", "ds", 682 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl", 683 OP_DUP>; 684 def VMOV_N : WOpInst<"vmov_n", "ds", 685 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl", 686 OP_DUP>; 687 } 688 let InstName = "" in 689 def VDUP_LANE: WOpInst<"vdup_lane", "dgi", 690 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", 691 OP_DUP_LN>; 692 693 //////////////////////////////////////////////////////////////////////////////// 694 // E.3.20 Combining vectors 695 def VCOMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>; 696 697 //////////////////////////////////////////////////////////////////////////////// 698 // E.3.21 Splitting vectors 699 let InstName = "vmov" in { 700 def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>; 701 def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>; 702 } 703 704 //////////////////////////////////////////////////////////////////////////////// 705 // E.3.22 Converting vectors 706 707 let ArchGuard = "(__ARM_FP & 2)" in { 708 def VCVT_F16_F32 : SInst<"vcvt_f16_f32", "md", "Hf">; 709 def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "wd", "h">; 710 } 711 712 def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">; 713 def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">; 714 def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">; 715 let isVCVT_N = 1 in { 716 def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">; 717 def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">; 718 def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">; 719 } 720 721 def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">; 722 def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">; 723 def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">; 724 def VQMOVUN : SInst<"vqmovun", "ek", "sil">; 725 726 //////////////////////////////////////////////////////////////////////////////// 727 // E.3.23-24 Table lookup, Extended table lookup 728 let InstName = "vtbl" in { 729 def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">; 730 def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">; 731 def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">; 732 def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">; 733 } 734 let InstName = "vtbx" in { 735 def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">; 736 def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">; 737 def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">; 738 def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">; 739 } 740 741 //////////////////////////////////////////////////////////////////////////////// 742 // E.3.25 Operations with a scalar value 743 def VMLA_LANE : IOpInst<"vmla_lane", "dddgi", 744 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 745 def VMLAL_LANE : SOpInst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>; 746 def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>; 747 def VMLS_LANE : IOpInst<"vmls_lane", "dddgi", 748 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 749 def VMLSL_LANE : SOpInst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>; 750 def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>; 751 def VMUL_N : IOpInst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>; 752 def VMUL_LANE : IOpInst<"vmul_lane", "ddgi", 753 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>; 754 def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">; 755 def VMULL_LANE : SOpInst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>; 756 def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">; 757 def VQDMULL_LANE : SOpInst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>; 758 def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">; 759 def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>; 760 def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">; 761 def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>; 762 763 let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in { 764 def VQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "dddgi", "siQsQi", OP_QRDMLAH_LN>; 765 def VQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "dddgi", "siQsQi", OP_QRDMLSH_LN>; 766 } 767 768 def VMLA_N : IOpInst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>; 769 def VMLAL_N : SOpInst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>; 770 def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">; 771 def VMLS_N : IOpInst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>; 772 def VMLSL_N : SOpInst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>; 773 def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">; 774 775 //////////////////////////////////////////////////////////////////////////////// 776 // E.3.26 Vector Extract 777 def VEXT : WInst<"vext", "dddi", 778 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">; 779 780 //////////////////////////////////////////////////////////////////////////////// 781 // E.3.27 Reverse vector elements 782 def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", 783 OP_REV64>; 784 def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>; 785 def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>; 786 787 //////////////////////////////////////////////////////////////////////////////// 788 // E.3.28 Other single operand arithmetic 789 def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">; 790 def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">; 791 def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>; 792 def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">; 793 def VCLS : SInst<"vcls", "dd", "csiQcQsQi">; 794 def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">; 795 def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">; 796 def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">; 797 def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">; 798 799 //////////////////////////////////////////////////////////////////////////////// 800 // E.3.29 Logical operations 801 def VMVN : LOpInst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>; 802 def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>; 803 def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>; 804 def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>; 805 def VBIC : LOpInst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>; 806 def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>; 807 let isHiddenLInst = 1 in 808 def VBSL : SInst<"vbsl", "dudd", 809 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">; 810 811 //////////////////////////////////////////////////////////////////////////////// 812 // E.3.30 Transposition operations 813 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 814 def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 815 def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 816 817 //////////////////////////////////////////////////////////////////////////////// 818 // E.3.31 Vector reinterpret cast operations 819 def VREINTERPRET 820 : NoTestOpInst<"vreinterpret", "dd", 821 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT> { 822 let CartesianProductOfTypes = 1; 823 let ArchGuard = "!defined(__aarch64__)"; 824 let BigEndianSafe = 1; 825 } 826 827 //////////////////////////////////////////////////////////////////////////////// 828 // Vector fused multiply-add operations 829 830 let ArchGuard = "defined(__ARM_FEATURE_FMA)" in { 831 def VFMA : SInst<"vfma", "dddd", "fQf">; 832 def VFMS : SOpInst<"vfms", "dddd", "fQf", OP_FMLS>; 833 } 834 835 //////////////////////////////////////////////////////////////////////////////// 836 // fp16 vector operations 837 def SCALAR_HALF_GET_LANE : IOpInst<"vget_lane", "sdi", "h", OP_SCALAR_HALF_GET_LN>; 838 def SCALAR_HALF_SET_LANE : IOpInst<"vset_lane", "dsdi", "h", OP_SCALAR_HALF_SET_LN>; 839 def SCALAR_HALF_GET_LANEQ : IOpInst<"vget_lane", "sdi", "Qh", OP_SCALAR_HALF_GET_LNQ>; 840 def SCALAR_HALF_SET_LANEQ : IOpInst<"vset_lane", "dsdi", "Qh", OP_SCALAR_HALF_SET_LNQ>; 841 842 //////////////////////////////////////////////////////////////////////////////// 843 // AArch64 Intrinsics 844 845 let ArchGuard = "defined(__aarch64__)" in { 846 847 //////////////////////////////////////////////////////////////////////////////// 848 // Load/Store 849 def LD1 : WInst<"vld1", "dc", "dQdPlQPl">; 850 def LD2 : WInst<"vld2", "2c", "QUlQldQdPlQPl">; 851 def LD3 : WInst<"vld3", "3c", "QUlQldQdPlQPl">; 852 def LD4 : WInst<"vld4", "4c", "QUlQldQdPlQPl">; 853 def ST1 : WInst<"vst1", "vpd", "dQdPlQPl">; 854 def ST2 : WInst<"vst2", "vp2", "QUlQldQdPlQPl">; 855 def ST3 : WInst<"vst3", "vp3", "QUlQldQdPlQPl">; 856 def ST4 : WInst<"vst4", "vp4", "QUlQldQdPlQPl">; 857 858 def LD1_X2 : WInst<"vld1_x2", "2c", 859 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 860 def LD3_x3 : WInst<"vld1_x3", "3c", 861 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 862 def LD4_x4 : WInst<"vld1_x4", "4c", 863 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 864 865 def ST1_X2 : WInst<"vst1_x2", "vp2", 866 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 867 def ST1_X3 : WInst<"vst1_x3", "vp3", 868 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 869 def ST1_X4 : WInst<"vst1_x4", "vp4", 870 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 871 872 def LD1_LANE : WInst<"vld1_lane", "dcdi", "dQdPlQPl">; 873 def LD2_LANE : WInst<"vld2_lane", "2c2i", "lUlQcQUcQPcQlQUldQdPlQPl">; 874 def LD3_LANE : WInst<"vld3_lane", "3c3i", "lUlQcQUcQPcQlQUldQdPlQPl">; 875 def LD4_LANE : WInst<"vld4_lane", "4c4i", "lUlQcQUcQPcQlQUldQdPlQPl">; 876 def ST1_LANE : WInst<"vst1_lane", "vpdi", "dQdPlQPl">; 877 def ST2_LANE : WInst<"vst2_lane", "vp2i", "lUlQcQUcQPcQlQUldQdPlQPl">; 878 def ST3_LANE : WInst<"vst3_lane", "vp3i", "lUlQcQUcQPcQlQUldQdPlQPl">; 879 def ST4_LANE : WInst<"vst4_lane", "vp4i", "lUlQcQUcQPcQlQUldQdPlQPl">; 880 881 def LD1_DUP : WInst<"vld1_dup", "dc", "dQdPlQPl">; 882 def LD2_DUP : WInst<"vld2_dup", "2c", 883 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">; 884 def LD3_DUP : WInst<"vld3_dup", "3c", 885 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">; 886 def LD4_DUP : WInst<"vld4_dup", "4c", 887 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">; 888 889 def VLDRQ : WInst<"vldrq", "sc", "Pk">; 890 def VSTRQ : WInst<"vstrq", "vps", "Pk">; 891 892 //////////////////////////////////////////////////////////////////////////////// 893 // Addition 894 def ADD : IOpInst<"vadd", "ddd", "dQd", OP_ADD>; 895 896 //////////////////////////////////////////////////////////////////////////////// 897 // Subtraction 898 def SUB : IOpInst<"vsub", "ddd", "dQd", OP_SUB>; 899 900 //////////////////////////////////////////////////////////////////////////////// 901 // Multiplication 902 def MUL : IOpInst<"vmul", "ddd", "dQd", OP_MUL>; 903 def MLA : IOpInst<"vmla", "dddd", "dQd", OP_MLA>; 904 def MLS : IOpInst<"vmls", "dddd", "dQd", OP_MLS>; 905 906 //////////////////////////////////////////////////////////////////////////////// 907 // Multiplication Extended 908 def MULX : SInst<"vmulx", "ddd", "fdQfQd">; 909 910 //////////////////////////////////////////////////////////////////////////////// 911 // Division 912 def FDIV : IOpInst<"vdiv", "ddd", "fdQfQd", OP_DIV>; 913 914 //////////////////////////////////////////////////////////////////////////////// 915 // Vector fused multiply-add operations 916 def FMLA : SInst<"vfma", "dddd", "dQd">; 917 def FMLS : SOpInst<"vfms", "dddd", "dQd", OP_FMLS>; 918 919 //////////////////////////////////////////////////////////////////////////////// 920 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument 921 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>; 922 923 def FMLA_N : SOpInst<"vfma_n", "ddds", "fQfQd", OP_FMLA_N>; 924 def FMLS_N : SOpInst<"vfms_n", "ddds", "fQfQd", OP_FMLS_N>; 925 926 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>; 927 def MLS_N : SOpInst<"vmls_n", "ddds", "Qd", OP_MLS_N>; 928 929 //////////////////////////////////////////////////////////////////////////////// 930 // Logical operations 931 def BSL : SInst<"vbsl", "dudd", "dPlQdQPl">; 932 933 //////////////////////////////////////////////////////////////////////////////// 934 // Absolute Difference 935 def ABD : SInst<"vabd", "ddd", "dQd">; 936 937 //////////////////////////////////////////////////////////////////////////////// 938 // saturating absolute/negate 939 def ABS : SInst<"vabs", "dd", "dQdlQl">; 940 def QABS : SInst<"vqabs", "dd", "lQl">; 941 def NEG : SOpInst<"vneg", "dd", "dlQdQl", OP_NEG>; 942 def QNEG : SInst<"vqneg", "dd", "lQl">; 943 944 //////////////////////////////////////////////////////////////////////////////// 945 // Signed Saturating Accumulated of Unsigned Value 946 def SUQADD : SInst<"vuqadd", "ddd", "csilQcQsQiQl">; 947 948 //////////////////////////////////////////////////////////////////////////////// 949 // Unsigned Saturating Accumulated of Signed Value 950 def USQADD : SInst<"vsqadd", "ddd", "UcUsUiUlQUcQUsQUiQUl">; 951 952 //////////////////////////////////////////////////////////////////////////////// 953 // Reciprocal/Sqrt 954 def FRECPS : IInst<"vrecps", "ddd", "dQd">; 955 def FRSQRTS : IInst<"vrsqrts", "ddd", "dQd">; 956 def FRECPE : SInst<"vrecpe", "dd", "dQd">; 957 def FRSQRTE : SInst<"vrsqrte", "dd", "dQd">; 958 def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">; 959 960 //////////////////////////////////////////////////////////////////////////////// 961 // bitwise reverse 962 def RBIT : IInst<"vrbit", "dd", "cUcPcQcQUcQPc">; 963 964 //////////////////////////////////////////////////////////////////////////////// 965 // Integer extract and narrow to high 966 def XTN2 : SOpInst<"vmovn_high", "qhk", "silUsUiUl", OP_XTN>; 967 968 //////////////////////////////////////////////////////////////////////////////// 969 // Signed integer saturating extract and unsigned narrow to high 970 def SQXTUN2 : SOpInst<"vqmovun_high", "emd", "HsHiHl", OP_SQXTUN>; 971 972 //////////////////////////////////////////////////////////////////////////////// 973 // Integer saturating extract and narrow to high 974 def QXTN2 : SOpInst<"vqmovn_high", "qhk", "silUsUiUl", OP_QXTN>; 975 976 //////////////////////////////////////////////////////////////////////////////// 977 // Converting vectors 978 979 def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "md", "Qd">; 980 def VCVT_F64_F32 : SInst<"vcvt_f64_f32", "wd", "f">; 981 982 def VCVT_S64 : SInst<"vcvt_s64", "xd", "dQd">; 983 def VCVT_U64 : SInst<"vcvt_u64", "ud", "dQd">; 984 def VCVT_F64 : SInst<"vcvt_f64", "Fd", "lUlQlQUl">; 985 986 def VCVT_HIGH_F16_F32 : SOpInst<"vcvt_high_f16", "hmj", "Hf", OP_VCVT_NA_HI_F16>; 987 def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "wk", "h", OP_VCVT_EX_HI_F32>; 988 def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "qfj", "d", OP_VCVT_NA_HI_F32>; 989 def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "wj", "f", OP_VCVT_EX_HI_F64>; 990 991 def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">; 992 def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "qfj", "d", OP_VCVTX_HI>; 993 994 //////////////////////////////////////////////////////////////////////////////// 995 // Comparison 996 def FCAGE : IInst<"vcage", "udd", "dQd">; 997 def FCAGT : IInst<"vcagt", "udd", "dQd">; 998 def FCALE : IInst<"vcale", "udd", "dQd">; 999 def FCALT : IInst<"vcalt", "udd", "dQd">; 1000 def CMTST : WInst<"vtst", "udd", "lUlPlQlQUlQPl">; 1001 def CFMEQ : SOpInst<"vceq", "udd", "lUldQdQlQUlPlQPl", OP_EQ>; 1002 def CFMGE : SOpInst<"vcge", "udd", "lUldQdQlQUl", OP_GE>; 1003 def CFMLE : SOpInst<"vcle", "udd", "lUldQdQlQUl", OP_LE>; 1004 def CFMGT : SOpInst<"vcgt", "udd", "lUldQdQlQUl", OP_GT>; 1005 def CFMLT : SOpInst<"vclt", "udd", "lUldQdQlQUl", OP_LT>; 1006 1007 def CMEQ : SInst<"vceqz", "ud", 1008 "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">; 1009 def CMGE : SInst<"vcgez", "ud", "csilfdQcQsQiQlQfQd">; 1010 def CMLE : SInst<"vclez", "ud", "csilfdQcQsQiQlQfQd">; 1011 def CMGT : SInst<"vcgtz", "ud", "csilfdQcQsQiQlQfQd">; 1012 def CMLT : SInst<"vcltz", "ud", "csilfdQcQsQiQlQfQd">; 1013 1014 //////////////////////////////////////////////////////////////////////////////// 1015 // Max/Min Integer 1016 def MAX : SInst<"vmax", "ddd", "dQd">; 1017 def MIN : SInst<"vmin", "ddd", "dQd">; 1018 1019 //////////////////////////////////////////////////////////////////////////////// 1020 // Pairwise Max/Min 1021 def MAXP : SInst<"vpmax", "ddd", "QcQsQiQUcQUsQUiQfQd">; 1022 def MINP : SInst<"vpmin", "ddd", "QcQsQiQUcQUsQUiQfQd">; 1023 1024 //////////////////////////////////////////////////////////////////////////////// 1025 // Pairwise MaxNum/MinNum Floating Point 1026 def FMAXNMP : SInst<"vpmaxnm", "ddd", "fQfQd">; 1027 def FMINNMP : SInst<"vpminnm", "ddd", "fQfQd">; 1028 1029 //////////////////////////////////////////////////////////////////////////////// 1030 // Pairwise Addition 1031 def ADDP : IInst<"vpadd", "ddd", "QcQsQiQlQUcQUsQUiQUlQfQd">; 1032 1033 //////////////////////////////////////////////////////////////////////////////// 1034 // Shifts by constant 1035 let isShift = 1 in { 1036 // Left shift long high 1037 def SHLL_HIGH_N : SOpInst<"vshll_high_n", "ndi", "HcHsHiHUcHUsHUi", 1038 OP_LONG_HI>; 1039 1040 //////////////////////////////////////////////////////////////////////////////// 1041 def SRI_N : WInst<"vsri_n", "dddi", "PlQPl">; 1042 def SLI_N : WInst<"vsli_n", "dddi", "PlQPl">; 1043 1044 // Right shift narrow high 1045 def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "hmdi", 1046 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1047 def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "hmdi", 1048 "HsHiHl", OP_NARROW_HI>; 1049 def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "hmdi", 1050 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1051 def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "hmdi", 1052 "HsHiHl", OP_NARROW_HI>; 1053 def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "hmdi", 1054 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1055 def QRSHRN_HIGH_N : SOpInst<"vqrshrn_high_n", "hmdi", 1056 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1057 } 1058 1059 //////////////////////////////////////////////////////////////////////////////// 1060 // Converting vectors 1061 def VMOVL_HIGH : SOpInst<"vmovl_high", "nd", "HcHsHiHUcHUsHUi", OP_MOVL_HI>; 1062 1063 let isVCVT_N = 1 in { 1064 def CVTF_N_F64 : SInst<"vcvt_n_f64", "Fdi", "lUlQlQUl">; 1065 def FCVTZS_N_S64 : SInst<"vcvt_n_s64", "xdi", "dQd">; 1066 def FCVTZS_N_U64 : SInst<"vcvt_n_u64", "udi", "dQd">; 1067 } 1068 1069 //////////////////////////////////////////////////////////////////////////////// 1070 // 3VDiff class using high 64-bit in operands 1071 def VADDL_HIGH : SOpInst<"vaddl_high", "wkk", "csiUcUsUi", OP_ADDLHi>; 1072 def VADDW_HIGH : SOpInst<"vaddw_high", "wwk", "csiUcUsUi", OP_ADDWHi>; 1073 def VSUBL_HIGH : SOpInst<"vsubl_high", "wkk", "csiUcUsUi", OP_SUBLHi>; 1074 def VSUBW_HIGH : SOpInst<"vsubw_high", "wwk", "csiUcUsUi", OP_SUBWHi>; 1075 1076 def VABDL_HIGH : SOpInst<"vabdl_high", "wkk", "csiUcUsUi", OP_ABDLHi>; 1077 def VABAL_HIGH : SOpInst<"vabal_high", "wwkk", "csiUcUsUi", OP_ABALHi>; 1078 1079 def VMULL_HIGH : SOpInst<"vmull_high", "wkk", "csiUcUsUiPc", OP_MULLHi>; 1080 def VMULL_HIGH_N : SOpInst<"vmull_high_n", "wks", "siUsUi", OP_MULLHi_N>; 1081 def VMLAL_HIGH : SOpInst<"vmlal_high", "wwkk", "csiUcUsUi", OP_MLALHi>; 1082 def VMLAL_HIGH_N : SOpInst<"vmlal_high_n", "wwks", "siUsUi", OP_MLALHi_N>; 1083 def VMLSL_HIGH : SOpInst<"vmlsl_high", "wwkk", "csiUcUsUi", OP_MLSLHi>; 1084 def VMLSL_HIGH_N : SOpInst<"vmlsl_high_n", "wwks", "siUsUi", OP_MLSLHi_N>; 1085 1086 def VADDHN_HIGH : SOpInst<"vaddhn_high", "qhkk", "silUsUiUl", OP_ADDHNHi>; 1087 def VRADDHN_HIGH : SOpInst<"vraddhn_high", "qhkk", "silUsUiUl", OP_RADDHNHi>; 1088 def VSUBHN_HIGH : SOpInst<"vsubhn_high", "qhkk", "silUsUiUl", OP_SUBHNHi>; 1089 def VRSUBHN_HIGH : SOpInst<"vrsubhn_high", "qhkk", "silUsUiUl", OP_RSUBHNHi>; 1090 1091 def VQDMULL_HIGH : SOpInst<"vqdmull_high", "wkk", "si", OP_QDMULLHi>; 1092 def VQDMULL_HIGH_N : SOpInst<"vqdmull_high_n", "wks", "si", OP_QDMULLHi_N>; 1093 def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "wwkk", "si", OP_QDMLALHi>; 1094 def VQDMLAL_HIGH_N : SOpInst<"vqdmlal_high_n", "wwks", "si", OP_QDMLALHi_N>; 1095 def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "wwkk", "si", OP_QDMLSLHi>; 1096 def VQDMLSL_HIGH_N : SOpInst<"vqdmlsl_high_n", "wwks", "si", OP_QDMLSLHi_N>; 1097 def VMULL_P64 : SInst<"vmull", "rss", "Pl">; 1098 def VMULL_HIGH_P64 : SOpInst<"vmull_high", "rdd", "HPl", OP_MULLHi_P64>; 1099 1100 1101 //////////////////////////////////////////////////////////////////////////////// 1102 // Extract or insert element from vector 1103 def GET_LANE : IInst<"vget_lane", "sdi", "dQdPlQPl">; 1104 def SET_LANE : IInst<"vset_lane", "dsdi", "dQdPlQPl">; 1105 def COPY_LANE : IOpInst<"vcopy_lane", "ddidi", 1106 "csilUcUsUiUlPcPsPlfd", OP_COPY_LN>; 1107 def COPYQ_LANE : IOpInst<"vcopy_lane", "ddigi", 1108 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>; 1109 def COPY_LANEQ : IOpInst<"vcopy_laneq", "ddiki", 1110 "csilPcPsPlUcUsUiUlfd", OP_COPY_LN>; 1111 def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "ddidi", 1112 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>; 1113 1114 //////////////////////////////////////////////////////////////////////////////// 1115 // Set all lanes to same value 1116 def VDUP_LANE1: WOpInst<"vdup_lane", "dgi", "hdQhQdPlQPl", OP_DUP_LN>; 1117 def VDUP_LANE2: WOpInst<"vdup_laneq", "dji", 1118 "csilUcUsUiUlPcPshfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl", 1119 OP_DUP_LN>; 1120 def DUP_N : WOpInst<"vdup_n", "ds", "dQdPlQPl", OP_DUP>; 1121 def MOV_N : WOpInst<"vmov_n", "ds", "dQdPlQPl", OP_DUP>; 1122 1123 //////////////////////////////////////////////////////////////////////////////// 1124 def COMBINE : NoTestOpInst<"vcombine", "kdd", "dPl", OP_CONC>; 1125 1126 //////////////////////////////////////////////////////////////////////////////// 1127 //Initialize a vector from bit pattern 1128 def CREATE : NoTestOpInst<"vcreate", "dl", "dPl", OP_CAST> { 1129 let BigEndianSafe = 1; 1130 } 1131 1132 //////////////////////////////////////////////////////////////////////////////// 1133 1134 def VMLA_LANEQ : IOpInst<"vmla_laneq", "dddji", 1135 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 1136 def VMLS_LANEQ : IOpInst<"vmls_laneq", "dddji", 1137 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 1138 1139 def VFMA_LANE : IInst<"vfma_lane", "dddgi", "fdQfQd">; 1140 def VFMA_LANEQ : IInst<"vfma_laneq", "dddji", "fdQfQd"> { 1141 let isLaneQ = 1; 1142 } 1143 def VFMS_LANE : IOpInst<"vfms_lane", "dddgi", "fdQfQd", OP_FMS_LN>; 1144 def VFMS_LANEQ : IOpInst<"vfms_laneq", "dddji", "fdQfQd", OP_FMS_LNQ>; 1145 1146 def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "wwdki", "siUsUi", OP_MLAL_LN>; 1147 def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "wwkdi", "siUsUi", 1148 OP_MLALHi_LN>; 1149 def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "wwkki", "siUsUi", 1150 OP_MLALHi_LN>; 1151 def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "wwdki", "siUsUi", OP_MLSL_LN>; 1152 def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "wwkdi", "siUsUi", 1153 OP_MLSLHi_LN>; 1154 def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "wwkki", "siUsUi", 1155 OP_MLSLHi_LN>; 1156 1157 def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "wwdki", "si", OP_QDMLAL_LN>; 1158 def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "wwkdi", "si", 1159 OP_QDMLALHi_LN>; 1160 def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "wwkki", "si", 1161 OP_QDMLALHi_LN>; 1162 def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "wwdki", "si", OP_QDMLSL_LN>; 1163 def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "wwkdi", "si", 1164 OP_QDMLSLHi_LN>; 1165 def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "wwkki", "si", 1166 OP_QDMLSLHi_LN>; 1167 1168 // Newly add double parameter for vmul_lane in aarch64 1169 // Note: d type is handled by SCALAR_VMUL_LANE 1170 def VMUL_LANE_A64 : IOpInst<"vmul_lane", "ddgi", "Qd", OP_MUL_LN>; 1171 1172 // Note: d type is handled by SCALAR_VMUL_LANEQ 1173 def VMUL_LANEQ : IOpInst<"vmul_laneq", "ddji", 1174 "sifUsUiQsQiQUsQUiQfQd", OP_MUL_LN>; 1175 def VMULL_LANEQ : SOpInst<"vmull_laneq", "wdki", "siUsUi", OP_MULL_LN>; 1176 def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "wkdi", "siUsUi", 1177 OP_MULLHi_LN>; 1178 def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "wkki", "siUsUi", 1179 OP_MULLHi_LN>; 1180 1181 def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "wdki", "si", OP_QDMULL_LN>; 1182 def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "wkdi", "si", 1183 OP_QDMULLHi_LN>; 1184 def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "wkki", "si", 1185 OP_QDMULLHi_LN>; 1186 1187 def VQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ddji", "siQsQi", OP_QDMULH_LN>; 1188 def VQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ddji", "siQsQi", OP_QRDMULH_LN>; 1189 1190 let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in { 1191 def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "dddji", "siQsQi", OP_QRDMLAH_LN>; 1192 def VQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "dddji", "siQsQi", OP_QRDMLSH_LN>; 1193 } 1194 1195 // Note: d type implemented by SCALAR_VMULX_LANE 1196 def VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "fQfQd", OP_MULX_LN>; 1197 // Note: d type is implemented by SCALAR_VMULX_LANEQ 1198 def VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "fQfQd", OP_MULX_LN>; 1199 1200 //////////////////////////////////////////////////////////////////////////////// 1201 // Across vectors class 1202 def VADDLV : SInst<"vaddlv", "rd", "csiUcUsUiQcQsQiQUcQUsQUi">; 1203 def VMAXV : SInst<"vmaxv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">; 1204 def VMINV : SInst<"vminv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">; 1205 def VADDV : SInst<"vaddv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">; 1206 def FMAXNMV : SInst<"vmaxnmv", "sd", "fQfQd">; 1207 def FMINNMV : SInst<"vminnmv", "sd", "fQfQd">; 1208 1209 //////////////////////////////////////////////////////////////////////////////// 1210 // Newly added Vector Extract for f64 1211 def VEXT_A64 : WInst<"vext", "dddi", "dQdPlQPl">; 1212 1213 //////////////////////////////////////////////////////////////////////////////// 1214 // Crypto 1215 let ArchGuard = "__ARM_FEATURE_CRYPTO" in { 1216 def AESE : SInst<"vaese", "ddd", "QUc">; 1217 def AESD : SInst<"vaesd", "ddd", "QUc">; 1218 def AESMC : SInst<"vaesmc", "dd", "QUc">; 1219 def AESIMC : SInst<"vaesimc", "dd", "QUc">; 1220 1221 def SHA1H : SInst<"vsha1h", "ss", "Ui">; 1222 def SHA1SU1 : SInst<"vsha1su1", "ddd", "QUi">; 1223 def SHA256SU0 : SInst<"vsha256su0", "ddd", "QUi">; 1224 1225 def SHA1C : SInst<"vsha1c", "ddsd", "QUi">; 1226 def SHA1P : SInst<"vsha1p", "ddsd", "QUi">; 1227 def SHA1M : SInst<"vsha1m", "ddsd", "QUi">; 1228 def SHA1SU0 : SInst<"vsha1su0", "dddd", "QUi">; 1229 def SHA256H : SInst<"vsha256h", "dddd", "QUi">; 1230 def SHA256H2 : SInst<"vsha256h2", "dddd", "QUi">; 1231 def SHA256SU1 : SInst<"vsha256su1", "dddd", "QUi">; 1232 } 1233 1234 //////////////////////////////////////////////////////////////////////////////// 1235 // Float -> Int conversions with explicit rounding mode 1236 1237 let ArchGuard = "__ARM_ARCH >= 8" in { 1238 def FCVTNS_S32 : SInst<"vcvtn_s32", "xd", "fQf">; 1239 def FCVTNU_S32 : SInst<"vcvtn_u32", "ud", "fQf">; 1240 def FCVTPS_S32 : SInst<"vcvtp_s32", "xd", "fQf">; 1241 def FCVTPU_S32 : SInst<"vcvtp_u32", "ud", "fQf">; 1242 def FCVTMS_S32 : SInst<"vcvtm_s32", "xd", "fQf">; 1243 def FCVTMU_S32 : SInst<"vcvtm_u32", "ud", "fQf">; 1244 def FCVTAS_S32 : SInst<"vcvta_s32", "xd", "fQf">; 1245 def FCVTAU_S32 : SInst<"vcvta_u32", "ud", "fQf">; 1246 } 1247 1248 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in { 1249 def FCVTNS_S64 : SInst<"vcvtn_s64", "xd", "dQd">; 1250 def FCVTNU_S64 : SInst<"vcvtn_u64", "ud", "dQd">; 1251 def FCVTPS_S64 : SInst<"vcvtp_s64", "xd", "dQd">; 1252 def FCVTPU_S64 : SInst<"vcvtp_u64", "ud", "dQd">; 1253 def FCVTMS_S64 : SInst<"vcvtm_s64", "xd", "dQd">; 1254 def FCVTMU_S64 : SInst<"vcvtm_u64", "ud", "dQd">; 1255 def FCVTAS_S64 : SInst<"vcvta_s64", "xd", "dQd">; 1256 def FCVTAU_S64 : SInst<"vcvta_u64", "ud", "dQd">; 1257 } 1258 1259 //////////////////////////////////////////////////////////////////////////////// 1260 // Round to Integral 1261 1262 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in { 1263 def FRINTN_S32 : SInst<"vrndn", "dd", "fQf">; 1264 def FRINTA_S32 : SInst<"vrnda", "dd", "fQf">; 1265 def FRINTP_S32 : SInst<"vrndp", "dd", "fQf">; 1266 def FRINTM_S32 : SInst<"vrndm", "dd", "fQf">; 1267 def FRINTX_S32 : SInst<"vrndx", "dd", "fQf">; 1268 def FRINTZ_S32 : SInst<"vrnd", "dd", "fQf">; 1269 } 1270 1271 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in { 1272 def FRINTN_S64 : SInst<"vrndn", "dd", "dQd">; 1273 def FRINTA_S64 : SInst<"vrnda", "dd", "dQd">; 1274 def FRINTP_S64 : SInst<"vrndp", "dd", "dQd">; 1275 def FRINTM_S64 : SInst<"vrndm", "dd", "dQd">; 1276 def FRINTX_S64 : SInst<"vrndx", "dd", "dQd">; 1277 def FRINTZ_S64 : SInst<"vrnd", "dd", "dQd">; 1278 def FRINTI_S64 : SInst<"vrndi", "dd", "fdQfQd">; 1279 } 1280 1281 //////////////////////////////////////////////////////////////////////////////// 1282 // MaxNum/MinNum Floating Point 1283 1284 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in { 1285 def FMAXNM_S32 : SInst<"vmaxnm", "ddd", "fQf">; 1286 def FMINNM_S32 : SInst<"vminnm", "ddd", "fQf">; 1287 } 1288 1289 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in { 1290 def FMAXNM_S64 : SInst<"vmaxnm", "ddd", "dQd">; 1291 def FMINNM_S64 : SInst<"vminnm", "ddd", "dQd">; 1292 } 1293 1294 //////////////////////////////////////////////////////////////////////////////// 1295 // Permutation 1296 def VTRN1 : SOpInst<"vtrn1", "ddd", 1297 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN1>; 1298 def VZIP1 : SOpInst<"vzip1", "ddd", 1299 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP1>; 1300 def VUZP1 : SOpInst<"vuzp1", "ddd", 1301 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP1>; 1302 def VTRN2 : SOpInst<"vtrn2", "ddd", 1303 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN2>; 1304 def VZIP2 : SOpInst<"vzip2", "ddd", 1305 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP2>; 1306 def VUZP2 : SOpInst<"vuzp2", "ddd", 1307 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP2>; 1308 1309 //////////////////////////////////////////////////////////////////////////////// 1310 // Table lookup 1311 let InstName = "vtbl" in { 1312 def VQTBL1_A64 : WInst<"vqtbl1", "djt", "UccPcQUcQcQPc">; 1313 def VQTBL2_A64 : WInst<"vqtbl2", "dBt", "UccPcQUcQcQPc">; 1314 def VQTBL3_A64 : WInst<"vqtbl3", "dCt", "UccPcQUcQcQPc">; 1315 def VQTBL4_A64 : WInst<"vqtbl4", "dDt", "UccPcQUcQcQPc">; 1316 } 1317 let InstName = "vtbx" in { 1318 def VQTBX1_A64 : WInst<"vqtbx1", "ddjt", "UccPcQUcQcQPc">; 1319 def VQTBX2_A64 : WInst<"vqtbx2", "ddBt", "UccPcQUcQcQPc">; 1320 def VQTBX3_A64 : WInst<"vqtbx3", "ddCt", "UccPcQUcQcQPc">; 1321 def VQTBX4_A64 : WInst<"vqtbx4", "ddDt", "UccPcQUcQcQPc">; 1322 } 1323 1324 //////////////////////////////////////////////////////////////////////////////// 1325 // Vector reinterpret cast operations 1326 1327 // NeonEmitter implicitly takes the cartesian product of the type string with 1328 // itself during generation so, unlike all other intrinsics, this one should 1329 // include *all* types, not just additional ones. 1330 def VVREINTERPRET 1331 : NoTestOpInst<"vreinterpret", "dd", 1332 "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", OP_REINT> { 1333 let CartesianProductOfTypes = 1; 1334 let BigEndianSafe = 1; 1335 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)"; 1336 } 1337 1338 //////////////////////////////////////////////////////////////////////////////// 1339 // Scalar Intrinsics 1340 // Scalar Arithmetic 1341 1342 // Scalar Addition 1343 def SCALAR_ADD : SInst<"vadd", "sss", "SlSUl">; 1344 // Scalar Saturating Add 1345 def SCALAR_QADD : SInst<"vqadd", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1346 1347 // Scalar Subtraction 1348 def SCALAR_SUB : SInst<"vsub", "sss", "SlSUl">; 1349 // Scalar Saturating Sub 1350 def SCALAR_QSUB : SInst<"vqsub", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1351 1352 let InstName = "vmov" in { 1353 def VGET_HIGH_A64 : NoTestOpInst<"vget_high", "dk", "dPl", OP_HI>; 1354 def VGET_LOW_A64 : NoTestOpInst<"vget_low", "dk", "dPl", OP_LO>; 1355 } 1356 1357 //////////////////////////////////////////////////////////////////////////////// 1358 // Scalar Shift 1359 // Scalar Shift Left 1360 def SCALAR_SHL: SInst<"vshl", "sss", "SlSUl">; 1361 // Scalar Saturating Shift Left 1362 def SCALAR_QSHL: SInst<"vqshl", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1363 // Scalar Saturating Rounding Shift Left 1364 def SCALAR_QRSHL: SInst<"vqrshl", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1365 // Scalar Shift Rouding Left 1366 def SCALAR_RSHL: SInst<"vrshl", "sss", "SlSUl">; 1367 1368 //////////////////////////////////////////////////////////////////////////////// 1369 // Scalar Shift (Immediate) 1370 let isScalarShift = 1 in { 1371 // Signed/Unsigned Shift Right (Immediate) 1372 def SCALAR_SSHR_N: SInst<"vshr_n", "ssi", "SlSUl">; 1373 // Signed/Unsigned Rounding Shift Right (Immediate) 1374 def SCALAR_SRSHR_N: SInst<"vrshr_n", "ssi", "SlSUl">; 1375 1376 // Signed/Unsigned Shift Right and Accumulate (Immediate) 1377 def SCALAR_SSRA_N: SInst<"vsra_n", "sssi", "SlSUl">; 1378 // Signed/Unsigned Rounding Shift Right and Accumulate (Immediate) 1379 def SCALAR_SRSRA_N: SInst<"vrsra_n", "sssi", "SlSUl">; 1380 1381 // Shift Left (Immediate) 1382 def SCALAR_SHL_N: SInst<"vshl_n", "ssi", "SlSUl">; 1383 // Signed/Unsigned Saturating Shift Left (Immediate) 1384 def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">; 1385 // Signed Saturating Shift Left Unsigned (Immediate) 1386 def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">; 1387 1388 // Shift Right And Insert (Immediate) 1389 def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">; 1390 // Shift Left And Insert (Immediate) 1391 def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">; 1392 1393 let isScalarNarrowShift = 1 in { 1394 // Signed/Unsigned Saturating Shift Right Narrow (Immediate) 1395 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">; 1396 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate) 1397 def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "zsi", "SsSiSlSUsSUiSUl">; 1398 // Signed Saturating Shift Right Unsigned Narrow (Immediate) 1399 def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "zsi", "SsSiSl">; 1400 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) 1401 def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "zsi", "SsSiSl">; 1402 } 1403 1404 //////////////////////////////////////////////////////////////////////////////// 1405 // Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate) 1406 def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "ysi", "SiSUi">; 1407 def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "osi", "SlSUl">; 1408 1409 //////////////////////////////////////////////////////////////////////////////// 1410 // Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate) 1411 def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "$si", "Sf">; 1412 def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "bsi", "Sf">; 1413 def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "$si", "Sd">; 1414 def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "bsi", "Sd">; 1415 } 1416 1417 //////////////////////////////////////////////////////////////////////////////// 1418 // Scalar Reduce Pairwise Addition (Scalar and Floating Point) 1419 def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHdSHUl">; 1420 1421 //////////////////////////////////////////////////////////////////////////////// 1422 // Scalar Reduce Floating Point Pairwise Max/Min 1423 def SCALAR_FMAXP : SInst<"vpmax", "sd", "SfSQd">; 1424 1425 def SCALAR_FMINP : SInst<"vpmin", "sd", "SfSQd">; 1426 1427 //////////////////////////////////////////////////////////////////////////////// 1428 // Scalar Reduce Floating Point Pairwise maxNum/minNum 1429 def SCALAR_FMAXNMP : SInst<"vpmaxnm", "sd", "SfSQd">; 1430 def SCALAR_FMINNMP : SInst<"vpminnm", "sd", "SfSQd">; 1431 1432 //////////////////////////////////////////////////////////////////////////////// 1433 // Scalar Integer Saturating Doubling Multiply Half High 1434 def SCALAR_SQDMULH : SInst<"vqdmulh", "sss", "SsSi">; 1435 1436 //////////////////////////////////////////////////////////////////////////////// 1437 // Scalar Integer Saturating Rounding Doubling Multiply Half High 1438 def SCALAR_SQRDMULH : SInst<"vqrdmulh", "sss", "SsSi">; 1439 1440 let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in { 1441 //////////////////////////////////////////////////////////////////////////////// 1442 // Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half 1443 def SCALAR_SQRDMLAH : SOpInst<"vqrdmlah", "ssss", "SsSi", OP_QRDMLAH>; 1444 1445 //////////////////////////////////////////////////////////////////////////////// 1446 // Signed Saturating Rounding Doubling Multiply Subtract Returning High Half 1447 def SCALAR_SQRDMLSH : SOpInst<"vqrdmlsh", "ssss", "SsSi", OP_QRDMLSH>; 1448 } 1449 1450 //////////////////////////////////////////////////////////////////////////////// 1451 // Scalar Floating-point Multiply Extended 1452 def SCALAR_FMULX : IInst<"vmulx", "sss", "SfSd">; 1453 1454 //////////////////////////////////////////////////////////////////////////////// 1455 // Scalar Floating-point Reciprocal Step 1456 def SCALAR_FRECPS : IInst<"vrecps", "sss", "SfSd">; 1457 1458 //////////////////////////////////////////////////////////////////////////////// 1459 // Scalar Floating-point Reciprocal Square Root Step 1460 def SCALAR_FRSQRTS : IInst<"vrsqrts", "sss", "SfSd">; 1461 1462 //////////////////////////////////////////////////////////////////////////////// 1463 // Scalar Signed Integer Convert To Floating-point 1464 def SCALAR_SCVTFS : SInst<"vcvt_f32", "ys", "Si">; 1465 def SCALAR_SCVTFD : SInst<"vcvt_f64", "os", "Sl">; 1466 1467 //////////////////////////////////////////////////////////////////////////////// 1468 // Scalar Unsigned Integer Convert To Floating-point 1469 def SCALAR_UCVTFS : SInst<"vcvt_f32", "ys", "SUi">; 1470 def SCALAR_UCVTFD : SInst<"vcvt_f64", "os", "SUl">; 1471 1472 //////////////////////////////////////////////////////////////////////////////// 1473 // Scalar Floating-point Converts 1474 def SCALAR_FCVTXN : IInst<"vcvtx_f32", "ys", "Sd">; 1475 def SCALAR_FCVTNSS : SInst<"vcvtn_s32", "$s", "Sf">; 1476 def SCALAR_FCVTNUS : SInst<"vcvtn_u32", "bs", "Sf">; 1477 def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "$s", "Sd">; 1478 def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "bs", "Sd">; 1479 def SCALAR_FCVTMSS : SInst<"vcvtm_s32", "$s", "Sf">; 1480 def SCALAR_FCVTMUS : SInst<"vcvtm_u32", "bs", "Sf">; 1481 def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "$s", "Sd">; 1482 def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "bs", "Sd">; 1483 def SCALAR_FCVTASS : SInst<"vcvta_s32", "$s", "Sf">; 1484 def SCALAR_FCVTAUS : SInst<"vcvta_u32", "bs", "Sf">; 1485 def SCALAR_FCVTASD : SInst<"vcvta_s64", "$s", "Sd">; 1486 def SCALAR_FCVTAUD : SInst<"vcvta_u64", "bs", "Sd">; 1487 def SCALAR_FCVTPSS : SInst<"vcvtp_s32", "$s", "Sf">; 1488 def SCALAR_FCVTPUS : SInst<"vcvtp_u32", "bs", "Sf">; 1489 def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "$s", "Sd">; 1490 def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "bs", "Sd">; 1491 def SCALAR_FCVTZSS : SInst<"vcvt_s32", "$s", "Sf">; 1492 def SCALAR_FCVTZUS : SInst<"vcvt_u32", "bs", "Sf">; 1493 def SCALAR_FCVTZSD : SInst<"vcvt_s64", "$s", "Sd">; 1494 def SCALAR_FCVTZUD : SInst<"vcvt_u64", "bs", "Sd">; 1495 1496 //////////////////////////////////////////////////////////////////////////////// 1497 // Scalar Floating-point Reciprocal Estimate 1498 def SCALAR_FRECPE : IInst<"vrecpe", "ss", "SfSd">; 1499 1500 //////////////////////////////////////////////////////////////////////////////// 1501 // Scalar Floating-point Reciprocal Exponent 1502 def SCALAR_FRECPX : IInst<"vrecpx", "ss", "SfSd">; 1503 1504 //////////////////////////////////////////////////////////////////////////////// 1505 // Scalar Floating-point Reciprocal Square Root Estimate 1506 def SCALAR_FRSQRTE : IInst<"vrsqrte", "ss", "SfSd">; 1507 1508 //////////////////////////////////////////////////////////////////////////////// 1509 // Scalar Integer Comparison 1510 def SCALAR_CMEQ : SInst<"vceq", "sss", "SlSUl">; 1511 def SCALAR_CMEQZ : SInst<"vceqz", "ss", "SlSUl">; 1512 def SCALAR_CMGE : SInst<"vcge", "sss", "Sl">; 1513 def SCALAR_CMGEZ : SInst<"vcgez", "ss", "Sl">; 1514 def SCALAR_CMHS : SInst<"vcge", "sss", "SUl">; 1515 def SCALAR_CMLE : SInst<"vcle", "sss", "SlSUl">; 1516 def SCALAR_CMLEZ : SInst<"vclez", "ss", "Sl">; 1517 def SCALAR_CMLT : SInst<"vclt", "sss", "SlSUl">; 1518 def SCALAR_CMLTZ : SInst<"vcltz", "ss", "Sl">; 1519 def SCALAR_CMGT : SInst<"vcgt", "sss", "Sl">; 1520 def SCALAR_CMGTZ : SInst<"vcgtz", "ss", "Sl">; 1521 def SCALAR_CMHI : SInst<"vcgt", "sss", "SUl">; 1522 def SCALAR_CMTST : SInst<"vtst", "sss", "SlSUl">; 1523 1524 //////////////////////////////////////////////////////////////////////////////// 1525 // Scalar Floating-point Comparison 1526 def SCALAR_FCMEQ : IInst<"vceq", "bss", "SfSd">; 1527 def SCALAR_FCMEQZ : IInst<"vceqz", "bs", "SfSd">; 1528 def SCALAR_FCMGE : IInst<"vcge", "bss", "SfSd">; 1529 def SCALAR_FCMGEZ : IInst<"vcgez", "bs", "SfSd">; 1530 def SCALAR_FCMGT : IInst<"vcgt", "bss", "SfSd">; 1531 def SCALAR_FCMGTZ : IInst<"vcgtz", "bs", "SfSd">; 1532 def SCALAR_FCMLE : IInst<"vcle", "bss", "SfSd">; 1533 def SCALAR_FCMLEZ : IInst<"vclez", "bs", "SfSd">; 1534 def SCALAR_FCMLT : IInst<"vclt", "bss", "SfSd">; 1535 def SCALAR_FCMLTZ : IInst<"vcltz", "bs", "SfSd">; 1536 1537 //////////////////////////////////////////////////////////////////////////////// 1538 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal 1539 def SCALAR_FACGE : IInst<"vcage", "bss", "SfSd">; 1540 def SCALAR_FACLE : IInst<"vcale", "bss", "SfSd">; 1541 1542 //////////////////////////////////////////////////////////////////////////////// 1543 // Scalar Floating-point Absolute Compare Mask Greater Than 1544 def SCALAR_FACGT : IInst<"vcagt", "bss", "SfSd">; 1545 def SCALAR_FACLT : IInst<"vcalt", "bss", "SfSd">; 1546 1547 //////////////////////////////////////////////////////////////////////////////// 1548 // Scalar Absolute Value 1549 def SCALAR_ABS : SInst<"vabs", "ss", "Sl">; 1550 1551 //////////////////////////////////////////////////////////////////////////////// 1552 // Scalar Absolute Difference 1553 def SCALAR_ABD : IInst<"vabd", "sss", "SfSd">; 1554 1555 //////////////////////////////////////////////////////////////////////////////// 1556 // Scalar Signed Saturating Absolute Value 1557 def SCALAR_SQABS : SInst<"vqabs", "ss", "ScSsSiSl">; 1558 1559 //////////////////////////////////////////////////////////////////////////////// 1560 // Scalar Negate 1561 def SCALAR_NEG : SInst<"vneg", "ss", "Sl">; 1562 1563 //////////////////////////////////////////////////////////////////////////////// 1564 // Scalar Signed Saturating Negate 1565 def SCALAR_SQNEG : SInst<"vqneg", "ss", "ScSsSiSl">; 1566 1567 //////////////////////////////////////////////////////////////////////////////// 1568 // Scalar Signed Saturating Accumulated of Unsigned Value 1569 def SCALAR_SUQADD : SInst<"vuqadd", "sss", "ScSsSiSl">; 1570 1571 //////////////////////////////////////////////////////////////////////////////// 1572 // Scalar Unsigned Saturating Accumulated of Signed Value 1573 def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">; 1574 1575 //////////////////////////////////////////////////////////////////////////////// 1576 // Signed Saturating Doubling Multiply-Add Long 1577 def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">; 1578 1579 //////////////////////////////////////////////////////////////////////////////// 1580 // Signed Saturating Doubling Multiply-Subtract Long 1581 def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">; 1582 1583 //////////////////////////////////////////////////////////////////////////////// 1584 // Signed Saturating Doubling Multiply Long 1585 def SCALAR_SQDMULL : SInst<"vqdmull", "rss", "SsSi">; 1586 1587 //////////////////////////////////////////////////////////////////////////////// 1588 // Scalar Signed Saturating Extract Unsigned Narrow 1589 def SCALAR_SQXTUN : SInst<"vqmovun", "zs", "SsSiSl">; 1590 1591 //////////////////////////////////////////////////////////////////////////////// 1592 // Scalar Signed Saturating Extract Narrow 1593 def SCALAR_SQXTN : SInst<"vqmovn", "zs", "SsSiSl">; 1594 1595 //////////////////////////////////////////////////////////////////////////////// 1596 // Scalar Unsigned Saturating Extract Narrow 1597 def SCALAR_UQXTN : SInst<"vqmovn", "zs", "SUsSUiSUl">; 1598 1599 // Scalar Floating Point multiply (scalar, by element) 1600 def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "ssdi", "SfSd", OP_SCALAR_MUL_LN>; 1601 def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "ssji", "SfSd", OP_SCALAR_MUL_LN>; 1602 1603 // Scalar Floating Point multiply extended (scalar, by element) 1604 def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "ssdi", "SfSd", OP_SCALAR_MULX_LN>; 1605 def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "ssji", "SfSd", OP_SCALAR_MULX_LN>; 1606 1607 def SCALAR_VMUL_N : IInst<"vmul_n", "dds", "d">; 1608 1609 // VMUL_LANE_A64 d type implemented using scalar mul lane 1610 def SCALAR_VMUL_LANE : IInst<"vmul_lane", "ddgi", "d">; 1611 1612 // VMUL_LANEQ d type implemented using scalar mul lane 1613 def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "ddji", "d"> { 1614 let isLaneQ = 1; 1615 } 1616 1617 // VMULX_LANE d type implemented using scalar vmulx_lane 1618 def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "d", OP_SCALAR_VMULX_LN>; 1619 1620 // VMULX_LANEQ d type implemented using scalar vmulx_laneq 1621 def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "d", OP_SCALAR_VMULX_LNQ>; 1622 1623 // Scalar Floating Point fused multiply-add (scalar, by element) 1624 def SCALAR_FMLA_LANE : IInst<"vfma_lane", "sssdi", "SfSd">; 1625 def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "sssji", "SfSd">; 1626 1627 // Scalar Floating Point fused multiply-subtract (scalar, by element) 1628 def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "sssdi", "SfSd", OP_FMS_LN>; 1629 def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "sssji", "SfSd", OP_FMS_LNQ>; 1630 1631 // Signed Saturating Doubling Multiply Long (scalar by element) 1632 def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "rsdi", "SsSi", OP_SCALAR_QDMULL_LN>; 1633 def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "rsji", "SsSi", OP_SCALAR_QDMULL_LN>; 1634 1635 // Signed Saturating Doubling Multiply-Add Long (scalar by element) 1636 def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "rrsdi", "SsSi">; 1637 def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "rrsji", "SsSi">; 1638 1639 // Signed Saturating Doubling Multiply-Subtract Long (scalar by element) 1640 def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "rrsdi", "SsSi">; 1641 def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "rrsji", "SsSi">; 1642 1643 // Scalar Integer Saturating Doubling Multiply Half High (scalar by element) 1644 def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QDMULH_LN>; 1645 def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QDMULH_LN>; 1646 1647 // Scalar Integer Saturating Rounding Doubling Multiply Half High 1648 def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QRDMULH_LN>; 1649 def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QRDMULH_LN>; 1650 1651 let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in { 1652 // Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half 1653 def SCALAR_SQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "sssdi", "SsSi", OP_SCALAR_QRDMLAH_LN>; 1654 def SCALAR_SQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "sssji", "SsSi", OP_SCALAR_QRDMLAH_LN>; 1655 1656 // Signed Saturating Rounding Doubling Multiply Subtract Returning High Half 1657 def SCALAR_SQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "sssdi", "SsSi", OP_SCALAR_QRDMLSH_LN>; 1658 def SCALAR_SQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "sssji", "SsSi", OP_SCALAR_QRDMLSH_LN>; 1659 } 1660 1661 def SCALAR_VDUP_LANE : IInst<"vdup_lane", "sdi", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1662 def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "sji", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1663 } 1664
