1 %default {"preinstr":"", "result":"w0", "chkzero":"0"} 2 /* 3 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4 * that specifies an instruction that performs "result = w0 op w1". 5 * This could be an ARM instruction or a function call. (If the result 6 * comes back in a register other than w0, you can override "result".) 7 * 8 * If "chkzero" is set to 1, we perform a divide-by-zero check on 9 * vCC (w1). Useful for integer division and modulus. 10 * 11 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 12 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 13 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 14 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 15 */ 16 /* binop/2addr vA, vB */ 17 lsr w3, wINST, #12 // w3<- B 18 ubfx w9, wINST, #8, #4 // w9<- A 19 GET_VREG w1, w3 // w1<- vB 20 GET_VREG w0, w9 // w0<- vA 21 .if $chkzero 22 cbz w1, common_errDivideByZero 23 .endif 24 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 25 $preinstr // optional op; may set condition codes 26 $instr // $result<- op, w0-w3 changed 27 GET_INST_OPCODE ip // extract opcode from rINST 28 SET_VREG $result, w9 // vAA<- $result 29 GOTO_OPCODE ip // jump to next instruction 30 /* 10-13 instructions */ 31
