1 %default { "gt_bias":"0" } 2 /* 3 * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) 4 * into the destination register based on the comparison results. 5 * 6 * For: cmpl-double, cmpg-double 7 */ 8 /* op vAA, vBB, vCC */ 9 10 FETCH(a0, 1) # a0 <- CCBB 11 and rOBJ, a0, 255 # rOBJ <- BB 12 srl t0, a0, 8 # t0 <- CC 13 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] 14 EAS2(t0, rFP, t0) # t0 <- &fp[CC] 15 LOAD64_F(ft0, ft0f, rOBJ) 16 LOAD64_F(ft1, ft1f, t0) 17 #ifdef MIPS32REVGE6 18 cmp.eq.d ft2, ft0, ft1 19 li rTEMP, 0 20 bc1nez ft2, 1f # done if vBB == vCC (ordered) 21 .if $gt_bias 22 cmp.lt.d ft2, ft0, ft1 23 li rTEMP, -1 24 bc1nez ft2, 1f # done if vBB < vCC (ordered) 25 li rTEMP, 1 # vBB > vCC or unordered 26 .else 27 cmp.lt.d ft2, ft1, ft0 28 li rTEMP, 1 29 bc1nez ft2, 1f # done if vBB > vCC (ordered) 30 li rTEMP, -1 # vBB < vCC or unordered 31 .endif 32 #else 33 c.eq.d fcc0, ft0, ft1 34 li rTEMP, 0 35 bc1t fcc0, 1f # done if vBB == vCC (ordered) 36 .if $gt_bias 37 c.olt.d fcc0, ft0, ft1 38 li rTEMP, -1 39 bc1t fcc0, 1f # done if vBB < vCC (ordered) 40 li rTEMP, 1 # vBB > vCC or unordered 41 .else 42 c.olt.d fcc0, ft1, ft0 43 li rTEMP, 1 44 bc1t fcc0, 1f # done if vBB > vCC (ordered) 45 li rTEMP, -1 # vBB < vCC or unordered 46 .endif 47 #endif 48 1: 49 GET_OPA(rOBJ) 50 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 51 GET_INST_OPCODE(t0) # extract opcode from rINST 52 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 53
