1 /*- 2 * Copyright (c) 2004-2005 David Schultz <das (at) FreeBSD.ORG> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ 27 */ 28 29 #ifndef _BITS_FENV_ARM_H_ 30 #define _BITS_FENV_ARM_H_ 31 32 #include <sys/types.h> 33 34 __BEGIN_DECLS 35 36 /* 37 * The ARM Cortex-A75 registers are described here: 38 * 39 * AArch64: 40 * FPCR: http://infocenter.arm.com/help/topic/com.arm.doc.100403_0200_00_en/lau1442502503726.html 41 * FPSR: http://infocenter.arm.com/help/topic/com.arm.doc.100403_0200_00_en/lau1442502526288.html 42 * AArch32: 43 * FPSCR: http://infocenter.arm.com/help/topic/com.arm.doc.100403_0200_00_en/lau1442504290459.html 44 */ 45 46 #if defined(__LP64__) 47 typedef struct { 48 /* FPCR, Floating-point Control Register. */ 49 __uint32_t __control; 50 /* FPSR, Floating-point Status Register. */ 51 __uint32_t __status; 52 } fenv_t; 53 54 #else 55 typedef __uint32_t fenv_t; 56 #endif 57 58 typedef __uint32_t fexcept_t; 59 60 /* Exception flags. */ 61 #define FE_INVALID 0x01 62 #define FE_DIVBYZERO 0x02 63 #define FE_OVERFLOW 0x04 64 #define FE_UNDERFLOW 0x08 65 #define FE_INEXACT 0x10 66 #define FE_DENORMAL 0x80 67 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW | FE_DENORMAL) 68 69 /* Rounding modes. */ 70 #define FE_TONEAREST 0x0 71 #define FE_UPWARD 0x1 72 #define FE_DOWNWARD 0x2 73 #define FE_TOWARDZERO 0x3 74 75 __END_DECLS 76 77 #endif 78
