1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __ARM_KVM_H__ 20 #define __ARM_KVM_H__ 21 #define KVM_SPSR_EL1 0 22 #define KVM_SPSR_SVC KVM_SPSR_EL1 23 #define KVM_SPSR_ABT 1 24 #define KVM_SPSR_UND 2 25 #define KVM_SPSR_IRQ 3 26 #define KVM_SPSR_FIQ 4 27 #define KVM_NR_SPSR 5 28 #ifndef __ASSEMBLY__ 29 #include <linux/psci.h> 30 #include <linux/types.h> 31 #include <asm/ptrace.h> 32 #define __KVM_HAVE_GUEST_DEBUG 33 #define __KVM_HAVE_IRQ_LINE 34 #define __KVM_HAVE_READONLY_MEM 35 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 36 #define KVM_REG_SIZE(id) (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 37 struct kvm_regs { 38 struct user_pt_regs regs; 39 __u64 sp_el1; 40 __u64 elr_el1; 41 __u64 spsr[KVM_NR_SPSR]; 42 struct user_fpsimd_state fp_regs; 43 }; 44 #define KVM_ARM_TARGET_AEM_V8 0 45 #define KVM_ARM_TARGET_FOUNDATION_V8 1 46 #define KVM_ARM_TARGET_CORTEX_A57 2 47 #define KVM_ARM_TARGET_XGENE_POTENZA 3 48 #define KVM_ARM_TARGET_CORTEX_A53 4 49 #define KVM_ARM_TARGET_GENERIC_V8 5 50 #define KVM_ARM_NUM_TARGETS 6 51 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 52 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 53 #define KVM_ARM_DEVICE_ID_SHIFT 16 54 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 55 #define KVM_ARM_DEVICE_VGIC_V2 0 56 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 57 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 58 #define KVM_VGIC_V2_DIST_SIZE 0x1000 59 #define KVM_VGIC_V2_CPU_SIZE 0x2000 60 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 61 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 62 #define KVM_VGIC_ITS_ADDR_TYPE 4 63 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 64 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 65 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 66 #define KVM_ARM_VCPU_POWER_OFF 0 67 #define KVM_ARM_VCPU_EL1_32BIT 1 68 #define KVM_ARM_VCPU_PSCI_0_2 2 69 #define KVM_ARM_VCPU_PMU_V3 3 70 struct kvm_vcpu_init { 71 __u32 target; 72 __u32 features[7]; 73 }; 74 struct kvm_sregs { 75 }; 76 struct kvm_fpu { 77 }; 78 #define KVM_ARM_MAX_DBG_REGS 16 79 struct kvm_guest_debug_arch { 80 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 81 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 82 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 83 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 84 }; 85 struct kvm_debug_exit_arch { 86 __u32 hsr; 87 __u64 far; 88 }; 89 #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 90 #define KVM_GUESTDBG_USE_HW (1 << 17) 91 struct kvm_sync_regs { 92 __u64 device_irq_level; 93 }; 94 struct kvm_arch_memory_slot { 95 }; 96 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 97 #define KVM_REG_ARM_COPROC_SHIFT 16 98 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 99 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 100 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 101 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 102 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 103 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 104 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 105 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 106 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 107 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 108 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 109 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 110 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 111 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 112 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 113 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 114 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 115 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 116 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 117 #define ARM64_SYS_REG_SHIFT_MASK(x,n) (((x) << KVM_REG_ARM64_SYSREG_ ##n ##_SHIFT) & KVM_REG_ARM64_SYSREG_ ##n ##_MASK) 118 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 119 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 120 #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 121 #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 122 #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 123 #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 124 #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 125 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 126 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 127 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 128 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 129 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 130 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 131 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 132 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 133 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 134 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 135 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 136 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 137 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 138 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 139 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 140 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 141 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 142 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 143 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 144 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 145 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 146 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 147 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 148 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 149 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 150 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 151 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 152 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 153 #define KVM_ARM_VCPU_PMU_V3_INIT 1 154 #define KVM_ARM_VCPU_TIMER_CTRL 1 155 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 156 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 157 #define KVM_ARM_IRQ_TYPE_SHIFT 24 158 #define KVM_ARM_IRQ_TYPE_MASK 0xff 159 #define KVM_ARM_IRQ_VCPU_SHIFT 16 160 #define KVM_ARM_IRQ_VCPU_MASK 0xff 161 #define KVM_ARM_IRQ_NUM_SHIFT 0 162 #define KVM_ARM_IRQ_NUM_MASK 0xffff 163 #define KVM_ARM_IRQ_TYPE_CPU 0 164 #define KVM_ARM_IRQ_TYPE_SPI 1 165 #define KVM_ARM_IRQ_TYPE_PPI 2 166 #define KVM_ARM_IRQ_CPU_IRQ 0 167 #define KVM_ARM_IRQ_CPU_FIQ 1 168 #define KVM_ARM_IRQ_GIC_MAX 127 169 #define KVM_NR_IRQCHIPS 1 170 #define KVM_PSCI_FN_BASE 0x95c1ba5e 171 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 172 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 173 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 174 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 175 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 176 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 177 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 178 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 179 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 180 #endif 181 #endif 182
