1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_VC4_DRM_H_ 20 #define _UAPI_VC4_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 #endif 24 #define DRM_VC4_SUBMIT_CL 0x00 25 #define DRM_VC4_WAIT_SEQNO 0x01 26 #define DRM_VC4_WAIT_BO 0x02 27 #define DRM_VC4_CREATE_BO 0x03 28 #define DRM_VC4_MMAP_BO 0x04 29 #define DRM_VC4_CREATE_SHADER_BO 0x05 30 #define DRM_VC4_GET_HANG_STATE 0x06 31 #define DRM_VC4_GET_PARAM 0x07 32 #define DRM_VC4_SET_TILING 0x08 33 #define DRM_VC4_GET_TILING 0x09 34 #define DRM_VC4_LABEL_BO 0x0a 35 #define DRM_VC4_GEM_MADVISE 0x0b 36 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) 37 #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) 38 #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) 39 #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) 40 #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) 41 #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) 42 #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) 43 #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) 44 #define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) 45 #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) 46 #define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) 47 #define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) 48 struct drm_vc4_submit_rcl_surface { 49 __u32 hindex; 50 __u32 offset; 51 __u16 bits; 52 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) 53 __u16 flags; 54 }; 55 struct drm_vc4_submit_cl { 56 __u64 bin_cl; 57 __u64 shader_rec; 58 __u64 uniforms; 59 __u64 bo_handles; 60 __u32 bin_cl_size; 61 __u32 shader_rec_size; 62 __u32 shader_rec_count; 63 __u32 uniforms_size; 64 __u32 bo_handle_count; 65 __u16 width; 66 __u16 height; 67 __u8 min_x_tile; 68 __u8 min_y_tile; 69 __u8 max_x_tile; 70 __u8 max_y_tile; 71 struct drm_vc4_submit_rcl_surface color_read; 72 struct drm_vc4_submit_rcl_surface color_write; 73 struct drm_vc4_submit_rcl_surface zs_read; 74 struct drm_vc4_submit_rcl_surface zs_write; 75 struct drm_vc4_submit_rcl_surface msaa_color_write; 76 struct drm_vc4_submit_rcl_surface msaa_zs_write; 77 __u32 clear_color[2]; 78 __u32 clear_z; 79 __u8 clear_s; 80 __u32 pad : 24; 81 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) 82 #define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1) 83 #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2) 84 #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3) 85 __u32 flags; 86 __u64 seqno; 87 }; 88 struct drm_vc4_wait_seqno { 89 __u64 seqno; 90 __u64 timeout_ns; 91 }; 92 struct drm_vc4_wait_bo { 93 __u32 handle; 94 __u32 pad; 95 __u64 timeout_ns; 96 }; 97 struct drm_vc4_create_bo { 98 __u32 size; 99 __u32 flags; 100 __u32 handle; 101 __u32 pad; 102 }; 103 struct drm_vc4_mmap_bo { 104 __u32 handle; 105 __u32 flags; 106 __u64 offset; 107 }; 108 struct drm_vc4_create_shader_bo { 109 __u32 size; 110 __u32 flags; 111 __u64 data; 112 __u32 handle; 113 __u32 pad; 114 }; 115 struct drm_vc4_get_hang_state_bo { 116 __u32 handle; 117 __u32 paddr; 118 __u32 size; 119 __u32 pad; 120 }; 121 struct drm_vc4_get_hang_state { 122 __u64 bo; 123 __u32 bo_count; 124 __u32 start_bin, start_render; 125 __u32 ct0ca, ct0ea; 126 __u32 ct1ca, ct1ea; 127 __u32 ct0cs, ct1cs; 128 __u32 ct0ra0, ct1ra0; 129 __u32 bpca, bpcs; 130 __u32 bpoa, bpos; 131 __u32 vpmbase; 132 __u32 dbge; 133 __u32 fdbgo; 134 __u32 fdbgb; 135 __u32 fdbgr; 136 __u32 fdbgs; 137 __u32 errstat; 138 __u32 pad[16]; 139 }; 140 #define DRM_VC4_PARAM_V3D_IDENT0 0 141 #define DRM_VC4_PARAM_V3D_IDENT1 1 142 #define DRM_VC4_PARAM_V3D_IDENT2 2 143 #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 144 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 145 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 146 #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 147 #define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 148 struct drm_vc4_get_param { 149 __u32 param; 150 __u32 pad; 151 __u64 value; 152 }; 153 struct drm_vc4_get_tiling { 154 __u32 handle; 155 __u32 flags; 156 __u64 modifier; 157 }; 158 struct drm_vc4_set_tiling { 159 __u32 handle; 160 __u32 flags; 161 __u64 modifier; 162 }; 163 struct drm_vc4_label_bo { 164 __u32 handle; 165 __u32 len; 166 __u64 name; 167 }; 168 #define VC4_MADV_WILLNEED 0 169 #define VC4_MADV_DONTNEED 1 170 #define __VC4_MADV_PURGED 2 171 #define __VC4_MADV_NOTSUPP 3 172 struct drm_vc4_gem_madvise { 173 __u32 handle; 174 __u32 madv; 175 __u32 retained; 176 __u32 pad; 177 }; 178 #ifdef __cplusplus 179 #endif 180 #endif 181
