1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _VIA_DRM_H_ 20 #define _VIA_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 #endif 24 #ifndef _VIA_DEFINES_ 25 #define _VIA_DEFINES_ 26 #define VIA_NR_SAREA_CLIPRECTS 8 27 #define VIA_NR_XVMC_PORTS 10 28 #define VIA_NR_XVMC_LOCKS 5 29 #define VIA_MAX_CACHELINE_SIZE 64 30 #define XVMCLOCKPTR(saPriv,lockNo) ((volatile struct drm_hw_lock *) (((((unsigned long) (saPriv)->XvMCLockArea) + (VIA_MAX_CACHELINE_SIZE - 1)) & ~(VIA_MAX_CACHELINE_SIZE - 1)) + VIA_MAX_CACHELINE_SIZE * (lockNo))) 31 #define VIA_NR_TEX_REGIONS 64 32 #define VIA_LOG_MIN_TEX_REGION_SIZE 16 33 #endif 34 #define VIA_UPLOAD_TEX0IMAGE 0x1 35 #define VIA_UPLOAD_TEX1IMAGE 0x2 36 #define VIA_UPLOAD_CTX 0x4 37 #define VIA_UPLOAD_BUFFERS 0x8 38 #define VIA_UPLOAD_TEX0 0x10 39 #define VIA_UPLOAD_TEX1 0x20 40 #define VIA_UPLOAD_CLIPRECTS 0x40 41 #define VIA_UPLOAD_ALL 0xff 42 #define DRM_VIA_ALLOCMEM 0x00 43 #define DRM_VIA_FREEMEM 0x01 44 #define DRM_VIA_AGP_INIT 0x02 45 #define DRM_VIA_FB_INIT 0x03 46 #define DRM_VIA_MAP_INIT 0x04 47 #define DRM_VIA_DEC_FUTEX 0x05 48 #define NOT_USED 49 #define DRM_VIA_DMA_INIT 0x07 50 #define DRM_VIA_CMDBUFFER 0x08 51 #define DRM_VIA_FLUSH 0x09 52 #define DRM_VIA_PCICMD 0x0a 53 #define DRM_VIA_CMDBUF_SIZE 0x0b 54 #define NOT_USED 55 #define DRM_VIA_WAIT_IRQ 0x0d 56 #define DRM_VIA_DMA_BLIT 0x0e 57 #define DRM_VIA_BLIT_SYNC 0x0f 58 #define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t) 59 #define DRM_IOCTL_VIA_FREEMEM DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t) 60 #define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t) 61 #define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t) 62 #define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t) 63 #define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t) 64 #define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t) 65 #define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t) 66 #define DRM_IOCTL_VIA_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_VIA_FLUSH) 67 #define DRM_IOCTL_VIA_PCICMD DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t) 68 #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, drm_via_cmdbuf_size_t) 69 #define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t) 70 #define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t) 71 #define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t) 72 #define VIA_TEX_SETUP_SIZE 8 73 #define VIA_FRONT 0x1 74 #define VIA_BACK 0x2 75 #define VIA_DEPTH 0x4 76 #define VIA_STENCIL 0x8 77 #define VIA_MEM_VIDEO 0 78 #define VIA_MEM_AGP 1 79 #define VIA_MEM_SYSTEM 2 80 #define VIA_MEM_MIXED 3 81 #define VIA_MEM_UNKNOWN 4 82 typedef struct { 83 __u32 offset; 84 __u32 size; 85 } drm_via_agp_t; 86 typedef struct { 87 __u32 offset; 88 __u32 size; 89 } drm_via_fb_t; 90 typedef struct { 91 __u32 context; 92 __u32 type; 93 __u32 size; 94 unsigned long index; 95 unsigned long offset; 96 } drm_via_mem_t; 97 typedef struct _drm_via_init { 98 enum { 99 VIA_INIT_MAP = 0x01, 100 VIA_CLEANUP_MAP = 0x02 101 } func; 102 unsigned long sarea_priv_offset; 103 unsigned long fb_offset; 104 unsigned long mmio_offset; 105 unsigned long agpAddr; 106 } drm_via_init_t; 107 typedef struct _drm_via_futex { 108 enum { 109 VIA_FUTEX_WAIT = 0x00, 110 VIA_FUTEX_WAKE = 0X01 111 } func; 112 __u32 ms; 113 __u32 lock; 114 __u32 val; 115 } drm_via_futex_t; 116 typedef struct _drm_via_dma_init { 117 enum { 118 VIA_INIT_DMA = 0x01, 119 VIA_CLEANUP_DMA = 0x02, 120 VIA_DMA_INITIALIZED = 0x03 121 } func; 122 unsigned long offset; 123 unsigned long size; 124 unsigned long reg_pause_addr; 125 } drm_via_dma_init_t; 126 typedef struct _drm_via_cmdbuffer { 127 char __user * buf; 128 unsigned long size; 129 } drm_via_cmdbuffer_t; 130 typedef struct _drm_via_tex_region { 131 unsigned char next, prev; 132 unsigned char inUse; 133 int age; 134 } drm_via_tex_region_t; 135 typedef struct _drm_via_sarea { 136 unsigned int dirty; 137 unsigned int nbox; 138 struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; 139 drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; 140 int texAge; 141 int ctxOwner; 142 int vertexPrim; 143 char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; 144 unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; 145 unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; 146 unsigned int XvMCCtxNoGrabbed; 147 unsigned int pfCurrentOffset; 148 } drm_via_sarea_t; 149 typedef struct _drm_via_cmdbuf_size { 150 enum { 151 VIA_CMDBUF_SPACE = 0x01, 152 VIA_CMDBUF_LAG = 0x02 153 } func; 154 int wait; 155 __u32 size; 156 } drm_via_cmdbuf_size_t; 157 typedef enum { 158 VIA_IRQ_ABSOLUTE = 0x0, 159 VIA_IRQ_RELATIVE = 0x1, 160 VIA_IRQ_SIGNAL = 0x10000000, 161 VIA_IRQ_FORCE_SEQUENCE = 0x20000000 162 } via_irq_seq_type_t; 163 #define VIA_IRQ_FLAGS_MASK 0xF0000000 164 enum drm_via_irqs { 165 drm_via_irq_hqv0 = 0, 166 drm_via_irq_hqv1, 167 drm_via_irq_dma0_dd, 168 drm_via_irq_dma0_td, 169 drm_via_irq_dma1_dd, 170 drm_via_irq_dma1_td, 171 drm_via_irq_num 172 }; 173 struct drm_via_wait_irq_request { 174 unsigned irq; 175 via_irq_seq_type_t type; 176 __u32 sequence; 177 __u32 signal; 178 }; 179 typedef union drm_via_irqwait { 180 struct drm_via_wait_irq_request request; 181 struct drm_wait_vblank_reply reply; 182 } drm_via_irqwait_t; 183 typedef struct drm_via_blitsync { 184 __u32 sync_handle; 185 unsigned engine; 186 } drm_via_blitsync_t; 187 typedef struct drm_via_dmablit { 188 __u32 num_lines; 189 __u32 line_length; 190 __u32 fb_addr; 191 __u32 fb_stride; 192 unsigned char * mem_addr; 193 __u32 mem_stride; 194 __u32 flags; 195 int to_fb; 196 drm_via_blitsync_t sync; 197 } drm_via_dmablit_t; 198 #ifdef __cplusplus 199 #endif 200 #endif 201
