1 ## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn54x) 2 ## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn54x) 3 4 ############################################################################### 5 # Application options 6 # Logging Levels 7 # NXPLOG_DEFAULT_LOGLEVEL 0x01 8 # ANDROID_LOG_DEBUG 0x03 9 # ANDROID_LOG_WARN 0x02 10 # ANDROID_LOG_ERROR 0x01 11 # ANDROID_LOG_SILENT 0x00 12 # 13 NXPLOG_EXTNS_LOGLEVEL=0x01 14 NXPLOG_NCIHAL_LOGLEVEL=0x01 15 NXPLOG_NCIX_LOGLEVEL=0x01 16 NXPLOG_NCIR_LOGLEVEL=0x01 17 NXPLOG_FWDNLD_LOGLEVEL=0x01 18 NXPLOG_TML_LOGLEVEL=0x01 19 NFC_DEBUG_ENABLED=0 20 21 ############################################################################### 22 # Nfc Device Node name 23 NXP_NFC_DEV_NODE="/dev/pn551" 24 25 ############################################################################### 26 # Extension for Mifare reader enable 27 MIFARE_READER_ENABLE=0x01 28 29 ############################################################################### 30 # Firmware file type 31 #.so file 0x01 32 #.bin file 0x02 33 NXP_FW_TYPE=0x01 34 35 ############################################################################### 36 # System clock source selection configuration 37 #define CLK_SRC_XTAL 1 38 #define CLK_SRC_PLL 2 39 NXP_SYS_CLK_SRC_SEL=0x01 40 41 ############################################################################### 42 # System clock frequency selection configuration 43 #define CLK_FREQ_13MHZ 1 44 #define CLK_FREQ_19_2MHZ 2 45 #define CLK_FREQ_24MHZ 3 46 #define CLK_FREQ_26MHZ 4 47 #define CLK_FREQ_38_4MHZ 5 48 #define CLK_FREQ_52MHZ 6 49 NXP_SYS_CLK_FREQ_SEL=0x01 50 51 ############################################################################### 52 # The timeout value to be used for clock request acknowledgment 53 # min value = 0x01 to max = 0x06 54 NXP_SYS_CLOCK_TO_CFG=0x06 55 56 ############################################################################### 57 # NXP proprietary settings 58 NXP_ACT_PROP_EXTN={2F, 02, 00} 59 60 ############################################################################### 61 # NFC forum profile settings 62 NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00} 63 64 ############################################################################### 65 # NXP TVDD configurations settings 66 # Allow NFCC to configure External TVDD, There are currently three 67 #configurations (1, 2 and 3) are supported, out of them only one can be 68 #supported. 69 NXP_EXT_TVDD_CFG=0x02 70 71 #config1:SLALM, 3.3V for both RM and CM 72 NXP_EXT_TVDD_CFG_1={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 02, 09, 00} 73 74 #config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM, 75 #monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms 76 NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 40, 0A } 77 78 ############################################################################### 79 # NXP RF ALMSL configuration settings for FW VERSION = 10.05.02 80 # 81 # A0, 0D, 03, 00, 40, 01 RF_CLIF_CFG_BOOT CLIF_ANA_NFCLD_REG 82 # A0, 0D, 03, 04, 47, 02 RF_CLIF_CFG_INITIATOR CLIF_ANA_AGC_REG 83 # A0, 0D, 03, 06, 47, 02 RF_CLIF_CFG_TARGET CLIF_ANA_AGC_REG 84 # A0, 0D, 06, 06, 03, 00, 6D, 00, 20 RF_CLIF_CFG_TARGET CLIF_TRANSCEIVE_CONTROL_REG 85 # A0, 0D, 06, 06, 42, 00, 02, FF, FF RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG 86 # A0, 0D, 03, 06, 37, 08 RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG 87 # A0, 0D, 06, 32, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG 88 # A0, 0D, 06, 34, 2D, 24, 47, 0C, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG 89 # A0, 0D, 04, 34, 44, 21, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG 90 # A0, 0D, 04, 46, 44, 26, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_ANA_RX_REG 91 # A0, 0D, 06, 46, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG 92 # A0, 0D, 06, 44, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG 93 # A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG 94 # A0, 0D, 04, 56, 44, 22, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG 95 # A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG 96 # A0, 0D, 04, 5C, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG 97 # A0, 0D, 06, 54, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG 98 # A0, 0D, 06, 5A, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG 99 # A0, 0D, 06, 98, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_B CLIF_ANA_TX_AMPLITUDE_REG 100 # A0, 0D, 06, 6C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG 101 # A0, 0D, 06, 7C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_ANA_RX_REG 102 # A0, 0D, 06, 8E, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXF CLIF_ANA_RX_REG 103 # A0, 0D, 06, 94, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXF CLIF_ANA_RX_REG 104 # A0, 0D, 06, 24, 42, 00, 02, FF, FF RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_AMPLITUDE_REG 105 # *** ALMSL FW VERSION = 10.05.02 *** 106 NXP_RF_CONF_BLK_1={ 107 20, 02, C5, 18, 108 A0, 0D, 03, 00, 40, 03, 109 A0, 0D, 03, 04, 47, 02, 110 A0, 0D, 03, 06, 47, 02, 111 A0, 0D, 06, 06, 03, 00, 6F, 00, 20, 112 A0, 0D, 06, 06, 42, 00, 00, F8, F8, 113 A0, 0D, 03, 06, 37, 08, 114 A0, 0D, 06, 32, 42, F8, 10, FF, FF, 115 A0, 0D, 06, 34, 2D, 24, 47, 0C, 00, 116 A0, 0D, 04, 34, 44, 21, 00, 117 A0, 0D, 04, 46, 44, 26, 00, 118 A0, 0D, 06, 46, 2D, 15, 25, 0D, 00, 119 A0, 0D, 06, 44, 42, 88, 10, FF, FF, 120 A0, 0D, 06, 56, 2D, 05, 5E, 0C, 00, 121 A0, 0D, 04, 56, 44, 21, 00, 122 A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00, 123 A0, 0D, 04, 5C, 44, 26, 00, 124 A0, 0D, 06, 54, 42, 88, 10, FF, FF, 125 A0, 0D, 06, 5A, 42, 90, 10, FF, FF, 126 A0, 0D, 06, 98, 42, 00, 00, F8, F8, 127 A0, 0D, 06, 6C, 44, A3, 90, 03, 00, 128 A0, 0D, 06, 7C, 44, A3, 90, 03, 00, 129 A0, 0D, 06, 8E, 44, 12, 90, 03, 00, 130 A0, 0D, 06, 94, 44, 12, 90, 03, 00, 131 A0, 0D, 06, 24, 42, 00, 00, F8, F8 132 } 133 134 ############################################################################### 135 # NXP RF configuration ALM/PLM settings 136 # This section needs to be updated with the correct values based on the platform 137 NXP_RF_CONF_BLK_2={ 138 20, 02, 71, 03, 139 A0, 1D, 11, 53, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00, 140 A0, 1E, 11, 1B, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00, 141 A0, 92, 45, 23, 04, 50, 10, 00, 19, 00, 14, 00, 92, 00, 08, 00, 01, 01, 09, 00, 4B, 01, 0A, 00, FF, 83, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00 142 } 143 144 ############################################################################### 145 # NXP RF configuration ALM/PLM settings 146 # This section needs to be updated with the correct values based on the platform 147 NXP_RF_CONF_BLK_3={ 148 20, 02, 2E, 05, 149 A0, 0D, 06, 00, 35, 50, 00, FF, 02, 150 A0, 0D, 06, 04, 35, F4, 01, F4, 01, 151 A0, 0D, 06, 06, 35, FF, 03, FF, 03, 152 A0, 0D, 06, 07, 35, FF, 01, FF, 02, 153 A0, 0D, 06, 10, 35, FF, 01, FF, 02 154 } 155 156 ############################################################################### 157 # NXP RF configuration ALM/PLM settings 158 # This section needs to be updated with the correct values based on the platform 159 #NXP_RF_CONF_BLK_4={ 160 #} 161 162 ############################################################################### 163 # NXP RF configuration ALM/PLM settings 164 # This section needs to be updated with the correct values based on the platform 165 #NXP_RF_CONF_BLK_5={ 166 #} 167 168 ############################################################################### 169 # NXP RF configuration ALM/PLM settings 170 # This section needs to be updated with the correct values based on the platform 171 #NXP_RF_CONF_BLK_6={ 172 #} 173 174 ############################################################################### 175 # Core configuration extensions 176 # It includes 177 # Wired mode settings A0ED, A0EE 178 # Tag Detector A040, A041, A043 179 # Low Power mode A007 180 # Clock settings A002, A003 181 # PbF settings A008 182 NXP_CORE_CONF_EXTN={20, 02, 29, 0A, 183 A0, 06, 01, 01, 184 A0, 07, 01, 02, 185 A0, EC, 01, 00, 186 A0, ED, 01, 00, 187 A0, 5E, 01, 01, 188 A0, 40, 01, 01, 189 A0, DD, 01, 2D, 190 A0, 96, 01, 01, 191 A0, 41, 01, 02, 192 A0, 43, 01, 00 193 } 194 195 ############################################################################### 196 # Core configuration rf field filter settings to enable set to 01 to disable set to 00 last bit 197 NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 01 198 } 199 ############################################################################### 200 # To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set to 0x00 201 NXP_I2C_FRAGMENTATION_ENABLED=0x00 202 203 ############################################################################### 204 # Core configuration settings 205 NXP_CORE_CONF={ 20, 02, 2A, 0E, 206 28, 01, 00, 207 21, 01, 00, 208 30, 01, 08, 209 31, 01, 03, 210 32, 01, 60, 211 38, 01, 01, 212 33, 00, 213 54, 01, 06, 214 50, 01, 02, 215 5B, 01, 00, 216 80, 01, 01, 217 81, 01, 01, 218 82, 01, 0E, 219 18, 01, 01 220 } 221 222 ############################################################################### 223 #Enable SWP full power mode when phone is power off 224 NXP_SWP_FULL_PWR_ON=0x00 225 226 ############################################################################### 227 #Set the default Felica T3T System Code OffHost route Location : 228 # host 0x00 229 # UICC 0x02 230 # UICC2 0x03 231 DEFAULT_SYS_CODE_ROUTE=0x00 232 233 ############################################################################### 234 #Set the default Felica T3T System Code : 235 DEFAULT_SYS_CODE={FE,FF} 236 237 ############################################################################### 238 # AID Matching platform options 239 # AID_MATCHING_L 0x01 240 # AID_MATCHING_K 0x02 241 AID_MATCHING_PLATFORM=0x01 242 243 ############################################################################### 244 #CHINA_TIANJIN_RF_SETTING 245 #Enable 0x01 246 #Disable 0x00 247 NXP_CHINA_TIANJIN_RF_ENABLED=0x01 248 249 ############################################################################### 250 #SWP_SWITCH_TIMEOUT_SETTING 251 # Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60]. 252 # Timeout in milliseconds, for example 253 # No Timeout 0x00 254 # 10 millisecond timeout 0x0A 255 NXP_SWP_SWITCH_TIMEOUT=0x0A 256 257 ############################################################################### 258 # Extended APDU length for ISO_DEP 259 ISO_DEP_MAX_TRANSCEIVE=0xFEFF 260 261 ############################################################################### 262 # Vendor Specific Proprietary Protocol & Discovery Configuration 263 # Set to 0xFF if unsupported 264 # byte[0] NCI_PROTOCOL_18092_ACTIVE 265 # byte[1] NCI_PROTOCOL_B_PRIME 266 # byte[2] NCI_PROTOCOL_DUAL 267 # byte[3] NCI_PROTOCOL_15693 268 # byte[4] NCI_PROTOCOL_KOVIO 269 # byte[5] NCI_PROTOCOL_MIFARE 270 # byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO 271 # byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME 272 # byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME 273 NFA_PROPRIETARY_CFG={05, FF, FF, 06, 81, 80, 70, FF, FF} 274 275 ############################################################################### 276 # Choose the presence-check algorithm for type-4 tag. If not defined, the default value is 1. 277 # 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm 278 # 1 NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block 279 # 2 NFA_RW_PRES_CHK_ISO_DEP_NAK; Type - 4 tag protocol iso-dep nak presence check 280 # command is sent waiting for rsp and ntf. 281 PRESENCE_CHECK_ALGORITHM=1 282 283 ############################################################################### 284
