1 /** @file 2 * 3 * Copyright (c) 2016, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2016, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef __PCIE_REG_OFFSET__ 17 #define __PCIE_REG_OFFSET__ 18 19 20 21 22 #define PCIE_EEP_PCI_CFG_HDR0_REG (0x0) 23 #define PCIE_EEP_PCI_CFG_HDR1_REG (0x4) 24 #define PCIE_EEP_PCI_CFG_HDR2_REG (0x8) 25 #define PCIE_EEP_PCI_CFG_HDR3_REG (0xC) 26 #define PCIE_EEP_PCI_CFG_HDR4_REG (0x10) 27 #define PCIE_EEP_PCI_CFG_HDR5_REG (0x14) 28 #define PCIE_EEP_PCI_CFG_HDR6_REG (0x18) 29 #define PCIE_EEP_PCI_CFG_HDR7_REG (0x1C) 30 #define PCIE_EEP_PCI_CFG_HDR8_REG (0x20) 31 #define PCIE_EEP_PCI_CFG_HDR9_REG (0x24) 32 #define PCIE_EEP_PCI_CFG_HDR10_REG (0x28) 33 #define PCIE_EEP_PCI_CFG_HDR11_REG (0x2C) 34 #define PCIE_EEP_PCI_CFG_HDR12_REG (0x30) 35 #define PCIE_EEP_PCI_CFG_HDR13_REG (0x34) 36 #define PCIE_EEP_PCI_CFG_HDR14_REG (0x38) 37 #define PCIE_EEP_PCI_CFG_HDR15_REG (0x3C) 38 #define PCIE_EEP_PCI_PM_CAP0_REG (0x40) 39 #define PCIE_EEP_PCI_PM_CAP1_REG (0x44) 40 #define PCIE_EEP_PCI_MSI_CAP0_REG (0x50) 41 #define PCIE_EEP_PCI_MSI_CAP1_REG (0x54) 42 #define PCIE_EEP_PCI_MSI_CAP2_REG (0x58) 43 #define PCIE_EEP_PCI_MSI_CAP3_REG (0x5C) 44 #define PCIE_EEP_PCIE_CAP0_REG (0x70) 45 #define PCIE_EEP_PCIE_CAP1_REG (0x74) 46 #define PCIE_EEP_PCIE_CAP2_REG (0x78) 47 #define PCIE_EEP_PCIE_CAP3_REG (0x7C) 48 #define PCIE_EEP_PCIE_CAP4_REG (0x80) 49 #define PCIE_EEP_PCIE_CAP5_REG (0x84) 50 #define PCIE_EEP_PCIE_CAP6_REG (0x88) 51 #define PCIE_EEP_PCIE_CAP7_REG (0x8C) 52 #define PCIE_EEP_PCIE_CAP8_REG (0x90) 53 #define PCIE_EEP_PCIE_CAP9_REG (0x94) 54 #define PCIE_EEP_PCIE_CAP10_REG (0x98) 55 #define PCIE_EEP_PCIE_CAP11_REG (0x9C) 56 #define PCIE_EEP_PCIE_CAP12_REG (0xA0) 57 #define PCIE_EEP_SLOT_CAP_REG (0xC0) 58 #define PCIE_EEP_AER_CAP0_REG (0x100) 59 #define PCIE_EEP_AER_CAP1_REG (0x104) 60 #define PCIE_EEP_AER_CAP2_REG (0x108) 61 #define PCIE_EEP_AER_CAP3_REG (0x10C) 62 #define PCIE_EEP_AER_CAP4_REG (0x110) 63 #define PCIE_EEP_AER_CAP5_REG (0x114) 64 #define PCIE_EEP_AER_CAP6_REG (0x118) 65 #define PCIE_EEP_AER_CAP7_REG (0x11C) 66 #define PCIE_EEP_AER_CAP8_REG (0x120) 67 #define PCIE_EEP_AER_CAP9_REG (0x124) 68 #define PCIE_EEP_AER_CAP10_REG (0x128) 69 #define PCIE_EEP_AER_CAP11_REG (0x12C) 70 #define PCIE_EEP_AER_CAP12_REG (0x130) 71 #define PCIE_EEP_AER_CAP13_REG (0x134) 72 #define PCIE_EEP_VC_CAP0_REG (0x140) 73 #define PCIE_EEP_VC_CAP1_REG (0x144) 74 #define PCIE_EEP_VC_CAP2_REG (0x148) 75 #define PCIE_EEP_VC_CAP3_REG (0x14C) 76 #define PCIE_EEP_VC_CAP4_REG (0x150) 77 #define PCIE_EEP_VC_CAP5_REG (0x154) 78 #define PCIE_EEP_VC_CAP6_REG (0x158) 79 #define PCIE_EEP_VC_CAP7_REG (0x15C) 80 #define PCIE_EEP_VC_CAP8_REG (0x160) 81 #define PCIE_EEP_VC_CAP9_REG (0x164) 82 #define PCIE_EEP_PORT_LOGIC0_REG (0x700) 83 #define PCIE_EEP_PORT_LOGIC1_REG (0x704) 84 #define PCIE_EEP_PORT_LOGIC2_REG (0x708) 85 #define PCIE_EEP_PORT_LOGIC3_REG (0x70C) 86 #define PCIE_EEP_PORT_LOGIC4_REG (0x710) 87 #define PCIE_EEP_PORT_LOGIC5_REG (0x714) 88 #define PCIE_EEP_PORT_LOGIC6_REG (0x718) 89 #define PCIE_EEP_PORT_LOGIC7_REG (0x71C) 90 #define PCIE_EEP_PORT_LOGIC8_REG (0x720) 91 #define PCIE_EEP_PORT_LOGIC9_REG (0x724) 92 #define PCIE_EEP_PORT_LOGIC10_REG (0x728) 93 #define PCIE_EEP_PORT_LOGIC11_REG (0x72C) 94 #define PCIE_EEP_PORT_LOGIC12_REG (0x730) 95 #define PCIE_EEP_PORT_LOGIC13_REG (0x734) 96 #define PCIE_EEP_PORT_LOGIC14_REG (0x738) 97 #define PCIE_EEP_PORT_LOGIC15_REG (0x73C) 98 #define PCIE_EEP_PORT_LOGIC16_REG (0x748) 99 #define PCIE_EEP_PORT_LOGIC17_REG (0x74C) 100 #define PCIE_EEP_PORT_LOGIC18_REG (0x750) 101 #define PCIE_EEP_PORT_LOGIC19_REG (0x7A8) 102 #define PCIE_EEP_PORT_LOGIC20_REG (0x7AC) 103 #define PCIE_EEP_PORT_LOGIC21_REG (0x7B0) 104 #define PCIE_EEP_PORT_LOGIC22_REG (0x80C) 105 #define PCIE_EEP_PORTLOGIC23_REG (0x810) 106 #define PCIE_EEP_PORTLOGIC24_REG (0x814) 107 #define PCIE_EEP_PORTLOGIC25_REG (0x818) 108 #define PCIE_EEP_PORTLOGIC26_REG (0x81C) 109 #define PCIE_EEP_PORTLOGIC27_REG (0x820) 110 #define PCIE_EEP_PORTLOGIC28_REG (0x824) 111 #define PCIE_EEP_PORTLOGIC29_REG (0x828) 112 #define PCIE_EEP_PORTLOGIC30_REG (0x82C) 113 #define PCIE_EEP_PORTLOGIC31_REG (0x830) 114 #define PCIE_EEP_PORTLOGIC32_REG (0x834) 115 #define PCIE_EEP_PORTLOGIC33_REG (0x838) 116 #define PCIE_EEP_PORTLOGIC34_REG (0x83C) 117 #define PCIE_EEP_PORTLOGIC35_REG (0x840) 118 #define PCIE_EEP_PORTLOGIC36_REG (0x844) 119 #define PCIE_EEP_PORTLOGIC37_REG (0x848) 120 #define PCIE_EEP_PORTLOGIC38_REG (0x84C) 121 #define PCIE_EEP_PORTLOGIC39_REG (0x850) 122 #define PCIE_EEP_PORTLOGIC40_REG (0x854) 123 #define PCIE_EEP_PORTLOGIC41_REG (0x858) 124 #define PCIE_EEP_PORTLOGIC42_REG (0x85C) 125 #define PCIE_EEP_PORTLOGIC43_REG (0x860) 126 #define PCIE_EEP_PORTLOGIC44_REG (0x864) 127 #define PCIE_EEP_PORTLOGIC45_REG (0x868) 128 #define PCIE_EEP_PORTLOGIC46_REG (0x86C) 129 #define PCIE_EEP_PORTLOGIC47_REG (0x870) 130 #define PCIE_EEP_PORTLOGIC48_REG (0x874) 131 #define PCIE_EEP_PORTLOGIC49_REG (0x878) 132 #define PCIE_EEP_PORTLOGIC50_REG (0x87C) 133 #define PCIE_EEP_PORTLOGIC51_REG (0x880) 134 #define PCIE_EEP_PORTLOGIC52_REG (0x884) 135 #define PCIE_EEP_PORTLOGIC53_REG (0x888) 136 #define PCIE_EEP_GEN3_CONTRL_REG (0x890) 137 #define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8) 138 #define PCIE_EEP_PORTLOGIC54_REG (0x900) 139 #define PCIE_EEP_PORTLOGIC55_REG (0x904) 140 #define PCIE_EEP_PORTLOGIC56_REG (0x908) 141 #define PCIE_EEP_PORTLOGIC57_REG (0x90C) 142 #define PCIE_EEP_PORTLOGIC58_REG (0x910) 143 #define PCIE_EEP_PORTLOGIC59_REG (0x914) 144 #define PCIE_EEP_PORTLOGIC60_REG (0x918) 145 #define PCIE_EEP_PORTLOGIC61_REG (0x91C) 146 #define PCIE_EEP_PORTLOGIC62_REG (0x97C) 147 #define PCIE_EEP_PORTLOGIC63_REG (0x980) 148 #define PCIE_EEP_PORTLOGIC64_REG (0x99C) 149 #define PCIE_EEP_PORTLOGIC65_REG (0x9A0) 150 #define PCIE_EEP_PORTLOGIC66_REG (0x9BC) 151 #define PCIE_EEP_PORTLOGIC67_REG (0x9C4) 152 #define PCIE_EEP_PORTLOGIC68_REG (0x9C8) 153 #define PCIE_EEP_PORTLOGIC69_REG (0x9CC) 154 #define PCIE_EEP_PORTLOGIC70_REG (0x9D0) 155 #define PCIE_EEP_PORTLOGIC71_REG (0x9D4) 156 #define PCIE_EEP_PORTLOGIC72_REG (0x9D8) 157 #define PCIE_EEP_PORTLOGIC73_REG (0x9DC) 158 #define PCIE_EEP_PORTLOGIC74_REG (0x9E0) 159 #define PCIE_EEP_PORTLOGIC75_REG (0xA00) 160 #define PCIE_EEP_PORTLOGIC76_REG (0xA10) 161 #define PCIE_EEP_PORTLOGIC77_REG (0xA18) 162 #define PCIE_EEP_PORTLOGIC78_REG (0xA1C) 163 #define PCIE_EEP_PORTLOGIC79_REG (0xA24) 164 #define PCIE_EEP_PORTLOGIC80_REG (0xA28) 165 #define PCIE_EEP_PORTLOGIC81_REG (0xA34) 166 #define PCIE_EEP_PORTLOGIC82_REG (0xA3C) 167 #define PCIE_EEP_PORTLOGIC83_REG (0xA40) 168 #define PCIE_EEP_PORTLOGIC84_REG (0xA44) 169 #define PCIE_EEP_PORTLOGIC85_REG (0xA48) 170 #define PCIE_EEP_PORTLOGIC86_REG (0xA6C) 171 #define PCIE_EEP_PORTLOGIC87_REG (0xA70) 172 #define PCIE_EEP_PORTLOGIC88_REG (0xA78) 173 #define PCIE_EEP_PORTLOGIC89_REG (0xA7C) 174 #define PCIE_EEP_PORTLOGIC90_REG (0xA80) 175 #define PCIE_EEP_PORTLOGIC91_REG (0xA84) 176 #define PCIE_EEP_PORTLOGIC92_REG (0xA88) 177 #define PCIE_EEP_PORTLOGIC93_REG (0xA8C) 178 #define PCIE_EEP_PORTLOGIC94_REG (0xA90) 179 180 //pcie iatu internal registers define 181 #define IATU_OFFSET 0x700 182 #define IATU_VIEW_POINT 0x200 183 #define IATU_REGION_CTRL1 0x204 184 #define IATU_REGION_CTRL2 0x208 185 #define IATU_REGION_BASE_LOW 0x20C 186 #define IATU_REGION_BASE_HIGH 0x210 187 #define IATU_REGION_BASE_LIMIT 0x214 188 #define IATU_REGION_TARGET_LOW 0x218 189 #define IATU_REGION_TARGET_HIGH 0x21C 190 #define IATU_SHIIF_MODE 0x90000000 191 #define IATU_NORMAL_MODE 0x80000000 192 #define IATU_CTRL1_TYPE_CONFIG0 0x4 193 #define IATU_CTRL1_TYPE_CONFIG1 0x5 194 #define IATU_CTRL1_TYPE_MEM 0 195 #define IATU_CTRL1_TYPE_IO 2 196 197 198 typedef union tagPipeLoopBack 199 { 200 struct 201 { 202 UINT32 reserved : 31 ; 203 UINT32 pipe_loopback_enable : 1 ; 204 }Bits; 205 UINT32 UInt32; 206 }PCIE_PIPE_LOOPBACK_U; 207 208 typedef union tagEepPciCfgHdr0 209 { 210 211 struct 212 { 213 UINT32 vendor_id : 16 ; 214 UINT32 device_id : 16 ; 215 } Bits; 216 217 218 UINT32 UInt32; 219 220 } PCIE_EEP_PCI_CFG_HDR0_U; 221 222 223 224 typedef union tagEepPciCfgHdr1 225 { 226 227 struct 228 { 229 UINT32 io_space_enable : 1 ; 230 UINT32 memory_space_enable : 1 ; 231 UINT32 bus_master_enable : 1 ; 232 UINT32 specialcycleenable : 1 ; 233 UINT32 memory_write_and_invalidate : 1 ; 234 UINT32 vga_palette_snoop_enable : 1 ; 235 UINT32 parity_error_response : 1 ; 236 UINT32 idsel_stepping_waitcycle_control : 1 ; 237 UINT32 serr_enable : 1 ; 238 UINT32 fastback_to_backenable : 1 ; 239 UINT32 interrupt_disable : 1 ; 240 UINT32 Reserved_2 : 5 ; 241 UINT32 Reserved_1 : 3 ; 242 UINT32 intx_status : 1 ; 243 UINT32 capabilitieslist : 1 ; 244 UINT32 pcibus66mhzcapable : 1 ; 245 UINT32 Reserved_0 : 1 ; 246 UINT32 fastback_to_back : 1 ; 247 UINT32 masterdataparityerror : 1 ; 248 UINT32 devsel_timing : 2 ; 249 UINT32 signaled_target_abort : 1 ; 250 UINT32 received_target_abort : 1 ; 251 UINT32 received_master_abort : 1 ; 252 UINT32 signaled_system_error : 1 ; 253 UINT32 detected_parity_error : 1 ; 254 } Bits; 255 256 257 UINT32 UInt32; 258 259 } PCIE_EEP_PCI_CFG_HDR1_U; 260 261 typedef union tagEepPciCfgHdr2 262 { 263 264 struct 265 { 266 UINT32 revision_identification : 8 ; 267 UINT32 Reserved_3 : 8 ; 268 UINT32 sub_class : 8 ; 269 UINT32 baseclass : 8 ; 270 } Bits; 271 272 273 UINT32 UInt32; 274 275 } PCIE_EEP_PCI_CFG_HDR2_U; 276 277 278 279 typedef union tagEepPciCfgHdr3 280 { 281 282 struct 283 { 284 UINT32 cache_line_size : 8 ; 285 UINT32 mstr_lat_tmr : 8 ; 286 UINT32 multi_function_device : 7 ; 287 UINT32 hdr_type : 1 ; 288 UINT32 bist : 8 ; 289 } Bits; 290 291 292 UINT32 UInt32; 293 294 } PCIE_EEP_PCI_CFG_HDR3_U; 295 296 297 298 typedef union tagEepPciCfgHdr4 299 { 300 301 struct 302 { 303 UINT32 sbar01_space_inicator : 1 ; 304 UINT32 sbar01_type : 2 ; 305 UINT32 sbar01_prefetchable : 1 ; 306 UINT32 sbar01_lower : 28 ; 307 } Bits; 308 309 310 UINT32 UInt32; 311 312 } PCIE_EEP_PCI_CFG_HDR4_U; 313 314 315 316 typedef union tagEepPciCfgHdr6 317 { 318 319 struct 320 { 321 UINT32 sbar23_space_inicator : 1 ; 322 UINT32 sbar23_type : 2 ; 323 UINT32 sbar23_prefetchable : 1 ; 324 UINT32 Reserved_4 : 8 ; 325 UINT32 sbar23_lower : 20 ; 326 } Bits; 327 328 329 UINT32 UInt32; 330 331 } PCIE_EEP_PCI_CFG_HDR6_U; 332 333 334 335 typedef union tagEepPciCfgHdr8 336 { 337 338 struct 339 { 340 UINT32 sbar45_space_inicator : 1 ; 341 UINT32 sbar45_type : 2 ; 342 UINT32 sbar45_prefetchable : 1 ; 343 UINT32 Reserved_5 : 8 ; 344 UINT32 sbar45_lower : 20 ; 345 } Bits; 346 347 348 UINT32 UInt32; 349 350 } PCIE_EEP_PCI_CFG_HDR8_U; 351 352 353 354 typedef union tagEepPciCfgHdr11 355 { 356 357 struct 358 { 359 UINT32 subsystem_vendor_id : 16 ; 360 UINT32 subsystemid : 16 ; 361 } Bits; 362 363 364 UINT32 UInt32; 365 366 } PCIE_EEP_PCI_CFG_HDR11_U; 367 368 369 370 typedef union tagEepPciCfgHdr13 371 { 372 373 struct 374 { 375 UINT32 capptr : 8 ; 376 UINT32 Reserved_6 : 24 ; 377 } Bits; 378 379 380 UINT32 UInt32; 381 382 } PCIE_EEP_PCI_CFG_HDR13_U; 383 384 385 386 typedef union tagEepPciCfgHdr15 387 { 388 389 struct 390 { 391 UINT32 int_line : 8 ; 392 UINT32 int_pin : 8 ; 393 UINT32 Min_Grant : 8 ; 394 UINT32 Max_Latency : 8 ; 395 } Bits; 396 397 398 UINT32 UInt32; 399 400 } PCIE_EEP_PCI_CFG_HDR15_U; 401 402 403 404 typedef union tagEepPciMsiCap0 405 { 406 407 struct 408 { 409 UINT32 msi_cap_id : 8 ; 410 UINT32 next_capability_pointer : 8 ; 411 UINT32 msi_enabled : 1 ; 412 UINT32 multiple_message_capable : 3 ; 413 UINT32 multiple_message_enabled : 3 ; 414 UINT32 msi_64_en : 1 ; 415 UINT32 pvm_en : 1 ; 416 UINT32 message_control_register : 7 ; 417 } Bits; 418 419 420 UINT32 UInt32; 421 422 } PCIE_EEP_PCI_MSI_CAP0_U; 423 424 425 426 typedef union tagEepPciMsiCap1 427 { 428 429 struct 430 { 431 UINT32 Reserved_11 : 2 ; 432 UINT32 msi_addr_low : 30 ; 433 } Bits; 434 435 436 UINT32 UInt32; 437 438 } PCIE_EEP_PCI_MSI_CAP1_U; 439 440 441 442 typedef union tagEepPciMsiCap3 443 { 444 445 struct 446 { 447 UINT32 msi_data : 16 ; 448 UINT32 Reserved_12 : 16 ; 449 } Bits; 450 451 452 UINT32 UInt32; 453 454 } PCIE_EEP_PCI_MSI_CAP3_U; 455 456 457 458 typedef union tagEepPcieCap0 459 { 460 461 struct 462 { 463 UINT32 pcie_cap_id : 8 ; 464 UINT32 pcie_next_ptr : 8 ; 465 UINT32 pcie_capability_version : 4 ; 466 UINT32 device_port_type : 4 ; 467 UINT32 slot_implemented : 1 ; 468 UINT32 interrupt_message_number : 5 ; 469 UINT32 Reserved_13 : 2 ; 470 } Bits; 471 472 473 UINT32 UInt32; 474 475 } PCIE_EEP_PCIE_CAP0_U; 476 477 478 479 typedef union tagEepPcieCap1 480 { 481 482 struct 483 { 484 UINT32 max_payload_size_supported : 3 ; 485 UINT32 phantom_function_supported : 2 ; 486 UINT32 extended_tagEepfield_supported : 1 ; 487 UINT32 endpoint_l0sacceptable_latency : 3 ; 488 UINT32 endpoint_l1acceptable_latency : 3 ; 489 UINT32 undefined : 3 ; 490 UINT32 Reserved_16 : 3 ; 491 UINT32 captured_slot_power_limit_value : 8 ; 492 UINT32 captured_slot_power_limit_scale : 2 ; 493 UINT32 function_level_reset : 1 ; 494 UINT32 Reserved_15 : 3 ; 495 } Bits; 496 497 498 UINT32 UInt32; 499 500 } PCIE_EEP_PCIE_CAP1_U; 501 502 503 504 typedef union tagEepPcieCap2 505 { 506 507 struct 508 { 509 UINT32 correctable_error_reporting_enable : 1 ; 510 UINT32 non_fatal_error_reporting_enable : 1 ; 511 UINT32 fatal_error_reporting_enable : 1 ; 512 UINT32 urenable : 1 ; 513 UINT32 enable_relaxed_ordering : 1 ; 514 UINT32 max_payload_size : 3 ; 515 UINT32 extended_tagEepfieldenable : 1 ; 516 UINT32 phantom_function_enable : 1 ; 517 UINT32 auxpowerpmenable : 1 ; 518 UINT32 enablenosnoop : 1 ; 519 UINT32 max_read_request_size : 3 ; 520 UINT32 Reserved_18 : 1 ; 521 UINT32 correctableerrordetected : 1 ; 522 UINT32 non_fatalerrordetected : 1 ; 523 UINT32 fatalerrordetected : 1 ; 524 UINT32 unsupportedrequestdetected : 1 ; 525 UINT32 auxpowerdetected : 1 ; 526 UINT32 transactionpending : 1 ; 527 UINT32 Reserved_17 : 10 ; 528 } Bits; 529 530 531 UINT32 UInt32; 532 533 } PCIE_EEP_PCIE_CAP2_U; 534 535 536 537 typedef union tagEepPcieCap3 538 { 539 540 struct 541 { 542 UINT32 max_link_speed : 4 ; 543 UINT32 max_link_width : 6 ; 544 UINT32 active_state_power_management : 2 ; 545 UINT32 l0s_exitlatency : 3 ; 546 UINT32 l1_exit_latency : 3 ; 547 UINT32 clock_power_management : 1 ; 548 UINT32 surprise_down_error_report_cap : 1 ; 549 UINT32 data_link_layer_active_report_cap : 1 ; 550 UINT32 link_bandwidth_noti_cap : 1 ; 551 UINT32 aspm_option_compliance : 1 ; 552 UINT32 Reserved_19 : 1 ; 553 UINT32 port_number : 8 ; 554 } Bits; 555 556 557 UINT32 UInt32; 558 559 } PCIE_EEP_PCIE_CAP3_U; 560 561 562 563 564 typedef union tagEepPcieCap4 565 { 566 567 struct 568 { 569 UINT32 active_state_power_management : 2 ; 570 UINT32 Reserved_22 : 1 ; 571 UINT32 rcb : 1 ; 572 UINT32 link_disable : 1 ; 573 UINT32 retrain_link : 1 ; 574 UINT32 common_clock_config : 1 ; 575 UINT32 extended_sync : 1 ; 576 UINT32 enable_clock_pwr_management : 1 ; 577 UINT32 hw_auto_width_disable : 1 ; 578 UINT32 link_bandwidth_management_int_en : 1 ; 579 UINT32 link_auto_bandwidth_int_en : 1 ; 580 UINT32 Reserved_21 : 4 ; 581 UINT32 current_link_speed : 4 ; 582 UINT32 negotiated_link_width : 6 ; 583 UINT32 Reserved_20 : 1 ; 584 UINT32 link_training : 1 ; 585 UINT32 slot_clock_configration : 1 ; 586 UINT32 data_link_layer_active : 1 ; 587 UINT32 link_bandwidth_management_status : 1 ; 588 UINT32 link_auto_bandwidth_status : 1 ; 589 } Bits; 590 591 592 UINT32 UInt32; 593 594 } PCIE_EEP_PCIE_CAP4_U; 595 596 597 598 599 typedef union tagEepPcieCap5 600 { 601 602 struct 603 { 604 UINT32 attentioonbuttonpresent : 1 ; 605 UINT32 powercontrollerpresent : 1 ; 606 UINT32 mrlsensorpresent : 1 ; 607 UINT32 attentionindicatorpresent : 1 ; 608 UINT32 powerindicatorpresent : 1 ; 609 UINT32 hot_plugsurprise : 1 ; 610 UINT32 hot_plugcapable : 1 ; 611 UINT32 slotpowerlimitvalue : 8 ; 612 UINT32 slotpowerlimitscale : 2 ; 613 UINT32 electromechanicalinterlockpresen : 1 ; 614 UINT32 no_cmd_complete_support : 1 ; 615 UINT32 phy_slot_number : 13 ; 616 } Bits; 617 618 619 UINT32 UInt32; 620 621 } PCIE_EEP_PCIE_CAP5_U; 622 623 624 625 626 typedef union tagEepPcieCap6 627 { 628 629 struct 630 { 631 UINT32 attentionbuttonpressedenable : 1 ; 632 UINT32 powerfaultdetectedenable : 1 ; 633 UINT32 mrlsensorchangedenable : 1 ; 634 UINT32 presencedetectchangedenable : 1 ; 635 UINT32 commandcompletedinterruptenable : 1 ; 636 UINT32 hot_pluginterruptenable : 1 ; 637 UINT32 attentionindicatorcontrol : 2 ; 638 UINT32 powerindicatorcontrol : 2 ; 639 UINT32 powercontrollercontrol : 1 ; 640 UINT32 electromechanicalinterlockcontrol : 1 ; 641 UINT32 datalinklayerstatechangedenable : 1 ; 642 UINT32 Reserved_23 : 3 ; 643 UINT32 attentionbuttonpressed : 1 ; 644 UINT32 powerfaultdetected : 1 ; 645 UINT32 mrlsensorchanged : 1 ; 646 UINT32 presencedetectchanged : 1 ; 647 UINT32 commandcompleted : 1 ; 648 UINT32 mrlsensorstate : 1 ; 649 UINT32 presencedetectstate : 1 ; 650 UINT32 electromechanicalinterlockstatus : 1 ; 651 UINT32 datalinklayerstatechanged : 1 ; 652 UINT32 slot_ctrl_status : 7 ; 653 } Bits; 654 655 656 UINT32 UInt32; 657 658 } PCIE_EEP_PCIE_CAP6_U; 659 660 661 662 663 typedef union tagEepPcieCap7 664 { 665 666 struct 667 { 668 UINT32 systemerroroncorrectableerrorenable : 1 ; 669 UINT32 systemerroronnon_fatalerrorenable : 1 ; 670 UINT32 systemerroronfatalerrorenable : 1 ; 671 UINT32 pmeinterruptenable : 1 ; 672 UINT32 crssoftwarevisibilityenable : 1 ; 673 UINT32 Reserved_24 : 11 ; 674 UINT32 crssoftwarevisibility : 1 ; 675 UINT32 root_cap : 15 ; 676 } Bits; 677 678 679 UINT32 UInt32; 680 681 } PCIE_EEP_PCIE_CAP7_U; 682 683 684 685 686 typedef union tagEepPcieCap8 687 { 688 689 struct 690 { 691 UINT32 pmerequesterid : 16 ; 692 UINT32 pmestatus : 1 ; 693 UINT32 pmepending : 1 ; 694 UINT32 root_status : 14 ; 695 } Bits; 696 697 698 UINT32 UInt32; 699 700 } PCIE_EEP_PCIE_CAP8_U; 701 702 703 704 705 typedef union tagEepPcieCap9 706 { 707 708 struct 709 { 710 UINT32 completiontimeoutrangessupported : 4 ; 711 UINT32 completiontimeoutdisablesupported : 1 ; 712 UINT32 ariforwardingsupported : 1 ; 713 UINT32 atomicoproutingsupported : 1 ; 714 UINT32 _2_bitatomicopcompletersupported : 1 ; 715 UINT32 _4_bitatomicopcompletersupported : 1 ; 716 UINT32 _28_bitcascompletersupported : 1 ; 717 UINT32 noro_enabledpr_prpassing : 1 ; 718 UINT32 Reserved_25 : 1 ; 719 UINT32 tphcompletersupported : 2 ; 720 UINT32 dev_cap2 : 18 ; 721 } Bits; 722 723 724 UINT32 UInt32; 725 726 } PCIE_EEP_PCIE_CAP9_U; 727 728 729 730 731 typedef union tagEepPcieCap10 732 { 733 734 struct 735 { 736 UINT32 completiontimeoutvalue : 4 ; 737 UINT32 completiontimeoutdisable : 1 ; 738 UINT32 ariforwardingsupported : 1 ; 739 UINT32 atomicoprequesterenable : 1 ; 740 UINT32 atomicopegressblocking : 1 ; 741 UINT32 idorequestenable : 1 ; 742 UINT32 idocompletionenable : 1 ; 743 UINT32 dev_ctrl2 : 22 ; 744 } Bits; 745 746 747 UINT32 UInt32; 748 749 } PCIE_EEP_PCIE_CAP10_U; 750 751 752 753 754 typedef union tagEepPcieCap11 755 { 756 757 struct 758 { 759 UINT32 Reserved_27 : 1 ; 760 UINT32 gen1_suport : 1 ; 761 UINT32 gen2_suport : 1 ; 762 UINT32 gen3_suport : 1 ; 763 UINT32 Reserved_26 : 4 ; 764 UINT32 crosslink_supported : 1 ; 765 UINT32 link_cap2 : 23 ; 766 } Bits; 767 768 769 UINT32 UInt32; 770 771 } PCIE_EEP_PCIE_CAP11_U; 772 773 774 775 776 typedef union tagEepPcieCap12 777 { 778 779 struct 780 { 781 UINT32 targetlinkspeed : 4 ; 782 UINT32 entercompliance : 1 ; 783 UINT32 hardwareautonomousspeeddisa : 1 ; 784 UINT32 selectablede_empha : 1 ; 785 UINT32 transmitmargin : 3 ; 786 UINT32 _entermodifiedcompliance : 1 ; 787 UINT32 compliancesos : 1 ; 788 UINT32 de_emphasislevel : 4 ; 789 UINT32 currentde_emphasislevel : 1 ; 790 UINT32 equalizationcomplete : 1 ; 791 UINT32 equalizationphase1successful : 1 ; 792 UINT32 equalizationphase2successful : 1 ; 793 UINT32 equalizationphase3successful : 1 ; 794 UINT32 linkequalizationrequest : 1 ; 795 UINT32 link_ctrl2_status2 : 10 ; 796 } Bits; 797 798 799 UINT32 UInt32; 800 801 } PCIE_EEP_PCIE_CAP12_U; 802 803 804 805 806 typedef union tagEepSlotCap 807 { 808 809 struct 810 { 811 UINT32 slotnumberingcapabilitiesid : 8 ; 812 UINT32 nextcapabilitypointer : 8 ; 813 UINT32 add_incardslotsprovided : 5 ; 814 UINT32 firstinchassis : 1 ; 815 UINT32 Reserved_28 : 2 ; 816 UINT32 slot_cap : 8 ; 817 } Bits; 818 819 820 UINT32 UInt32; 821 822 } PCIE_EEP_SLOT_CAP_U; 823 824 825 826 827 typedef union tagEepAerCap0 828 { 829 830 struct 831 { 832 UINT32 pciexpressextendedcapabilityid : 16 ; 833 UINT32 capabilityversion : 4 ; 834 UINT32 aer_cap_hdr : 12 ; 835 } Bits; 836 837 838 UINT32 UInt32; 839 840 } PCIE_EEP_AER_CAP0_U; 841 842 843 844 845 typedef union tagEepAerCap1 846 { 847 848 struct 849 { 850 UINT32 Reserved_34 : 1 ; 851 UINT32 Reserved_33 : 3 ; 852 UINT32 datalinkprotocolerrorsta : 1 ; 853 UINT32 surprisedownerrorstatus : 1 ; 854 UINT32 Reserved_32 : 6 ; 855 UINT32 poisonedtlpstatu : 1 ; 856 UINT32 flowcontrolprotocolerrorst : 1 ; 857 UINT32 completiontimeouts : 1 ; 858 UINT32 completerabortstatus : 1 ; 859 UINT32 receiveroverflowstatus : 1 ; 860 UINT32 malformedtlpstatus : 1 ; 861 UINT32 ecrcerrorstatus : 1 ; 862 UINT32 ecrcerrorstat : 1 ; 863 UINT32 unsupportedrequesterrorstatus : 1 ; 864 UINT32 Reserved_31 : 3 ; 865 UINT32 atomicopegressblockedstatus : 1 ; 866 UINT32 uncorr_err_status : 7 ; 867 } Bits; 868 869 870 UINT32 UInt32; 871 872 } PCIE_EEP_AER_CAP1_U; 873 874 875 876 877 typedef union tagEepAerCap2 878 { 879 880 struct 881 { 882 UINT32 Reserved_38 : 1 ; 883 UINT32 Reserved_37 : 3 ; 884 UINT32 datalinkprotocolerrormask : 1 ; 885 UINT32 surprisedownerrormask : 1 ; 886 UINT32 Reserved_36 : 6 ; 887 UINT32 poisonedtlpmask : 1 ; 888 UINT32 flowcontrolprotocolerrormask : 1 ; 889 UINT32 completiontimeoutmask : 1 ; 890 UINT32 completerabortmask : 1 ; 891 UINT32 unexpectedcompletionmask : 1 ; 892 UINT32 receiveroverflowmask : 1 ; 893 UINT32 malformedtlpmask : 1 ; 894 UINT32 ecrcerrormask : 1 ; 895 UINT32 unsupportedrequesterrormask : 1 ; 896 UINT32 Reserved_35 : 3 ; 897 UINT32 atomicopegressblockedmask : 1 ; 898 UINT32 uncorr_err_mask : 7 ; 899 } Bits; 900 901 902 UINT32 UInt32; 903 904 } PCIE_EEP_AER_CAP2_U; 905 906 907 908 909 typedef union tagEepAerCap3 910 { 911 912 struct 913 { 914 UINT32 Reserved_42 : 1 ; 915 UINT32 Reserved_41 : 3 ; 916 UINT32 datalinkprotocolerrorsever : 1 ; 917 UINT32 surprisedownerrorseverity : 1 ; 918 UINT32 Reserved_40 : 6 ; 919 UINT32 poisonedtlpseverity : 1 ; 920 UINT32 flowcontrolprotocolerrorseveri : 1 ; 921 UINT32 completiontimeoutseverity : 1 ; 922 UINT32 completerabortseverity : 1 ; 923 UINT32 unexpectedcompletionseverity : 1 ; 924 UINT32 receiveroverflowseverity : 1 ; 925 UINT32 malformedtlpseverity : 1 ; 926 UINT32 ecrcerrorseverity : 1 ; 927 UINT32 unsupportedrequesterrorseverity : 1 ; 928 UINT32 Reserved_39 : 3 ; 929 UINT32 atomicopegressblockedseverity : 1 ; 930 UINT32 uncorr_err_ser : 7 ; 931 } Bits; 932 933 934 UINT32 UInt32; 935 936 } PCIE_EEP_AER_CAP3_U; 937 938 939 940 941 typedef union tagEepAerCap4 942 { 943 944 struct 945 { 946 UINT32 receivererrorstatus : 1 ; 947 UINT32 Reserved_44 : 5 ; 948 UINT32 badtlpstatus : 1 ; 949 UINT32 baddllpstatus : 1 ; 950 UINT32 replay_numrolloverstatus : 1 ; 951 UINT32 Reserved_43 : 3 ; 952 UINT32 replytimertimeoutstatus : 1 ; 953 UINT32 advisorynon_fatalerrorstatus : 1 ; 954 UINT32 corr_err_status : 18 ; 955 } Bits; 956 957 958 UINT32 UInt32; 959 960 } PCIE_EEP_AER_CAP4_U; 961 962 963 964 965 typedef union tagEepAerCap5 966 { 967 968 struct 969 { 970 UINT32 receivererrormask : 1 ; 971 UINT32 Reserved_46 : 5 ; 972 UINT32 badtlpmask : 1 ; 973 UINT32 baddllpmask : 1 ; 974 UINT32 replay_numrollovermask : 1 ; 975 UINT32 Reserved_45 : 3 ; 976 UINT32 replytimertimeoutmask : 1 ; 977 UINT32 advisorynon_fatalerrormask : 1 ; 978 UINT32 corr_err_mask : 18 ; 979 } Bits; 980 981 982 UINT32 UInt32; 983 984 } PCIE_EEP_AER_CAP5_U; 985 986 987 988 989 typedef union tagEepAerCap6 990 { 991 992 struct 993 { 994 UINT32 firsterrorpointer : 5 ; 995 UINT32 ecrcgenerationcapability : 1 ; 996 UINT32 ecrcgenerationenable : 1 ; 997 UINT32 ecrccheckcapable : 1 ; 998 UINT32 ecrccheckenable : 1 ; 999 UINT32 adv_cap_ctrl : 23 ; 1000 } Bits; 1001 1002 1003 UINT32 UInt32; 1004 1005 } PCIE_EEP_AER_CAP6_U; 1006 1007 typedef union tagGen3Ctrol 1008 { 1009 struct 1010 { 1011 UINT32 reserved : 16 ; 1012 UINT32 equalization_disable : 1 ; 1013 UINT32 reserved2 : 15 ; 1014 }Bits; 1015 UINT32 UInt32; 1016 }PCIE_GRN3_CONTRL; 1017 1018 1019 1020 1021 typedef union tagEepAerCap11 1022 { 1023 1024 struct 1025 { 1026 UINT32 correctableerrorreportingenable : 1 ; 1027 UINT32 non_fatalerrorreportingenable : 1 ; 1028 UINT32 fatalerrorreportingenable : 1 ; 1029 UINT32 root_err_cmd : 29 ; 1030 } Bits; 1031 1032 1033 UINT32 UInt32; 1034 1035 } PCIE_EEP_AER_CAP11_U; 1036 1037 1038 1039 1040 typedef union tagEepAerCap12 1041 { 1042 1043 struct 1044 { 1045 UINT32 err_correceived : 1 ; 1046 UINT32 multipleerr_correceived : 1 ; 1047 UINT32 err_fatal_nonfatalreceived : 1 ; 1048 UINT32 multipleerr_fatal_nonfatalreceived : 1 ; 1049 UINT32 firstuncorrectablefatal : 1 ; 1050 UINT32 non_fatalerrormessagesreceived : 1 ; 1051 UINT32 fatalerrormessagesreceived : 1 ; 1052 UINT32 Reserved_47 : 20 ; 1053 UINT32 root_err_status : 5 ; 1054 } Bits; 1055 1056 1057 UINT32 UInt32; 1058 1059 } PCIE_EEP_AER_CAP12_U; 1060 1061 1062 1063 1064 typedef union tagEepAerCap13 1065 { 1066 1067 struct 1068 { 1069 UINT32 err_corsourceidentification : 16 ; 1070 UINT32 err_src_id : 16 ; 1071 } Bits; 1072 1073 1074 UINT32 UInt32; 1075 1076 } PCIE_EEP_AER_CAP13_U; 1077 1078 1079 1080 1081 typedef union tagEepVcCap0 1082 { 1083 1084 struct 1085 { 1086 UINT32 pciexpressextendedcapabilityid : 16 ; 1087 UINT32 capabilityversion : 4 ; 1088 UINT32 vc_cap_hdr : 12 ; 1089 } Bits; 1090 1091 1092 UINT32 UInt32; 1093 1094 } PCIE_EEP_VC_CAP0_U; 1095 1096 1097 1098 1099 typedef union tagEepVcCap1 1100 { 1101 1102 struct 1103 { 1104 UINT32 extendedvccount : 3 ; 1105 UINT32 Reserved_50 : 1 ; 1106 UINT32 lowpriorityextendedvccount : 3 ; 1107 UINT32 Reserved_49 : 1 ; 1108 UINT32 referenceclock : 2 ; 1109 UINT32 portarbitrationtableentrysize : 2 ; 1110 UINT32 vc_cap1 : 20 ; 1111 } Bits; 1112 1113 1114 UINT32 UInt32; 1115 1116 } PCIE_EEP_VC_CAP1_U; 1117 1118 1119 1120 1121 typedef union tagEepVcCap2 1122 { 1123 1124 struct 1125 { 1126 UINT32 vcarbitrationcapability : 8 ; 1127 UINT32 Reserved_51 : 16 ; 1128 UINT32 vc_cap2 : 8 ; 1129 } Bits; 1130 1131 1132 UINT32 UInt32; 1133 1134 } PCIE_EEP_VC_CAP2_U; 1135 1136 1137 1138 1139 typedef union tagEepVcCap3 1140 { 1141 1142 struct 1143 { 1144 UINT32 loadvcarbitrationtable : 1 ; 1145 UINT32 vcarbitrationselect : 3 ; 1146 UINT32 Reserved_53 : 12 ; 1147 UINT32 arbitrationtablestatus : 1 ; 1148 UINT32 Reserved_52 : 15 ; 1149 } Bits; 1150 1151 1152 UINT32 UInt32; 1153 1154 } PCIE_EEP_VC_CAP3_U; 1155 1156 1157 1158 1159 typedef union tagEepVcCap4 1160 { 1161 1162 struct 1163 { 1164 UINT32 portarbitrationcapability : 8 ; 1165 UINT32 Reserved_56 : 6 ; 1166 UINT32 Reserved_55 : 1 ; 1167 UINT32 rejectsnooptransactions : 1 ; 1168 UINT32 maximumtimeslots : 7 ; 1169 UINT32 Reserved_54 : 1 ; 1170 UINT32 vc_res_cap : 8 ; 1171 } Bits; 1172 1173 1174 UINT32 UInt32; 1175 1176 } PCIE_EEP_VC_CAP4_U; 1177 1178 1179 1180 1181 typedef union tagEepVcCap5 1182 { 1183 1184 struct 1185 { 1186 UINT32 tc_vcmap : 8 ; 1187 UINT32 Reserved_59 : 8 ; 1188 UINT32 loadportarbitrationtable : 1 ; 1189 UINT32 portarbitrationselec : 3 ; 1190 UINT32 Reserved_58 : 4 ; 1191 UINT32 vcid : 3 ; 1192 UINT32 Reserved_57 : 4 ; 1193 UINT32 vc_res_ctrl : 1 ; 1194 } Bits; 1195 1196 1197 UINT32 UInt32; 1198 1199 } PCIE_EEP_VC_CAP5_U; 1200 1201 1202 1203 1204 typedef union tagEepVcCap6 1205 { 1206 1207 struct 1208 { 1209 UINT32 Reserved_60 : 16 ; 1210 UINT32 portarbitrationtablestatus : 1 ; 1211 UINT32 vcnegotiationpending : 1 ; 1212 UINT32 vc_res_status : 14 ; 1213 } Bits; 1214 1215 1216 UINT32 UInt32; 1217 1218 } PCIE_EEP_VC_CAP6_U; 1219 1220 1221 1222 1223 typedef union tagEepVcCap7 1224 { 1225 1226 struct 1227 { 1228 UINT32 portarbitrationcapability : 8 ; 1229 UINT32 Reserved_63 : 6 ; 1230 UINT32 Reserved_62 : 1 ; 1231 UINT32 rejectsnooptransactions : 1 ; 1232 UINT32 maximumtimeslots : 7 ; 1233 UINT32 Reserved_61 : 1 ; 1234 UINT32 vc_res_cap0 : 8 ; 1235 } Bits; 1236 1237 1238 UINT32 UInt32; 1239 1240 } PCIE_EEP_VC_CAP7_U; 1241 1242 1243 1244 1245 typedef union tagEepVcCap8 1246 { 1247 1248 struct 1249 { 1250 UINT32 tc_vcmap : 8 ; 1251 UINT32 Reserved_66 : 8 ; 1252 UINT32 loadportarbitrationtable : 1 ; 1253 UINT32 portarbitrationselect : 3 ; 1254 UINT32 Reserved_65 : 4 ; 1255 UINT32 vcid : 3 ; 1256 UINT32 Reserved_64 : 4 ; 1257 UINT32 vc_res_ctrl0 : 1 ; 1258 } Bits; 1259 1260 1261 UINT32 UInt32; 1262 1263 } PCIE_EEP_VC_CAP8_U; 1264 1265 1266 1267 1268 typedef union tagEepVcCap9 1269 { 1270 1271 struct 1272 { 1273 UINT32 Reserved_67 : 16 ; 1274 UINT32 arbitrationtablestatus : 1 ; 1275 UINT32 vcnegotiationpending : 1 ; 1276 UINT32 vc_res_status0 : 14 ; 1277 } Bits; 1278 1279 1280 UINT32 UInt32; 1281 1282 } PCIE_EEP_VC_CAP9_U; 1283 1284 1285 1286 1287 typedef union tagEepPortLogic0 1288 { 1289 1290 struct 1291 { 1292 UINT32 ack_lat_timer : 16 ; 1293 UINT32 replay_timer : 16 ; 1294 } Bits; 1295 1296 1297 UINT32 UInt32; 1298 1299 } PCIE_EEP_PORT_LOGIC0_U; 1300 1301 1302 1303 1304 typedef union tagEepPortLogic2 1305 { 1306 1307 struct 1308 { 1309 UINT32 linknumber : 8 ; 1310 UINT32 Reserved_70 : 7 ; 1311 UINT32 forcelink : 1 ; 1312 UINT32 linkstate : 6 ; 1313 UINT32 Reserved_69 : 2 ; 1314 UINT32 port_force_link : 8 ; 1315 } Bits; 1316 1317 1318 UINT32 UInt32; 1319 1320 } PCIE_EEP_PORT_LOGIC2_U; 1321 1322 1323 1324 1325 typedef union tagEepPortLogic3 1326 { 1327 1328 struct 1329 { 1330 UINT32 ackfrequency : 8 ; 1331 UINT32 n_fts : 8 ; 1332 UINT32 commonclockn_fts : 8 ; 1333 UINT32 l0sentrancelatency : 3 ; 1334 UINT32 l1entrancelatency : 3 ; 1335 UINT32 enteraspml1withoutreceiveinl0s : 1 ; 1336 UINT32 ack_aspm : 1 ; 1337 } Bits; 1338 1339 1340 UINT32 UInt32; 1341 1342 } PCIE_EEP_PORT_LOGIC3_U; 1343 1344 1345 1346 1347 typedef union tagEepPortLogic4 1348 { 1349 1350 struct 1351 { 1352 UINT32 vendorspecificdllprequest : 1 ; 1353 UINT32 scrambledisable : 1 ; 1354 UINT32 loopbackenable : 1 ; 1355 UINT32 resetassert : 1 ; 1356 UINT32 Reserved_73 : 1 ; 1357 UINT32 dlllinkenable : 1 ; 1358 UINT32 Reserved_72 : 1 ; 1359 UINT32 fastlinkmode : 1 ; 1360 UINT32 Reserved_71 : 8 ; 1361 UINT32 linkmodeenable : 6 ; 1362 UINT32 crosslinkenable : 1 ; 1363 UINT32 crosslinkactive : 1 ; 1364 UINT32 port_link_ctrl : 8 ; 1365 } Bits; 1366 1367 1368 UINT32 UInt32; 1369 1370 } PCIE_EEP_PORT_LOGIC4_U; 1371 1372 1373 1374 1375 typedef union tagEepPortLogic5 1376 { 1377 1378 struct 1379 { 1380 UINT32 insertlaneskewfortransmit : 24 ; 1381 UINT32 flowcontroldisable : 1 ; 1382 UINT32 ack_nakdisable : 1 ; 1383 UINT32 Reserved_74 : 5 ; 1384 UINT32 lane_skew : 1 ; 1385 } Bits; 1386 1387 1388 UINT32 UInt32; 1389 1390 } PCIE_EEP_PORT_LOGIC5_U; 1391 1392 1393 1394 1395 typedef union tagEepPortLogic6 1396 { 1397 1398 struct 1399 { 1400 UINT32 numberoftssymbols : 4 ; 1401 UINT32 Reserved_76 : 4 ; 1402 UINT32 numberofskpsymbols : 3 ; 1403 UINT32 Reserved_75 : 3 ; 1404 UINT32 timermodifierforreplaytimer : 5 ; 1405 UINT32 timermodifierforack_naklatencytimer : 5 ; 1406 UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ; 1407 UINT32 sym_num : 3 ; 1408 } Bits; 1409 1410 1411 UINT32 UInt32; 1412 1413 } PCIE_EEP_PORT_LOGIC6_U; 1414 1415 1416 1417 1418 typedef union tagEepPortLogic7 1419 { 1420 1421 struct 1422 { 1423 UINT32 vc0posteddataqueuedepth : 11 ; 1424 UINT32 Reserved_77 : 4 ; 1425 UINT32 sym_timer : 1 ; 1426 UINT32 maskfunctionmismatchfilteringfo : 1 ; 1427 UINT32 maskpoisonedtlpfiltering : 1 ; 1428 UINT32 maskbarmatchfiltering : 1 ; 1429 UINT32 masktype1configurationrequestfiltering : 1 ; 1430 UINT32 masklockedrequestfiltering : 1 ; 1431 UINT32 masktagerrorrulesforreceivedcompletions : 1 ; 1432 UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ; 1433 UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ; 1434 UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ; 1435 UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ; 1436 UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ; 1437 UINT32 maske_crcerror_filtering : 1 ; 1438 UINT32 maske_crcerror_filtering_forcompletions : 1 ; 1439 UINT32 message_control : 1 ; 1440 UINT32 maskfilteringofreceived : 1 ; 1441 UINT32 flt_mask1 : 1 ; 1442 } Bits; 1443 1444 1445 UINT32 UInt32; 1446 1447 } PCIE_EEP_PORT_LOGIC7_U; 1448 1449 1450 1451 1452 typedef union tagEepPortLogic8 1453 { 1454 1455 struct 1456 { 1457 UINT32 cx_flt_mask_venmsg0_drop : 1 ; 1458 UINT32 cx_flt_mask_venmsg1_drop : 1 ; 1459 UINT32 cx_flt_mask_dabort_4ucpl : 1 ; 1460 UINT32 cx_flt_mask_handle_flush : 1 ; 1461 UINT32 flt_mask2 : 28 ; 1462 } Bits; 1463 1464 1465 UINT32 UInt32; 1466 1467 } PCIE_EEP_PORT_LOGIC8_U; 1468 1469 1470 1471 1472 typedef union tagEepPortLogic9 1473 { 1474 1475 struct 1476 { 1477 UINT32 amba_multi_outbound_decomp_np : 1 ; 1478 UINT32 amba_obnp_ctrl : 31 ; 1479 } Bits; 1480 1481 1482 UINT32 UInt32; 1483 1484 } PCIE_EEP_PORT_LOGIC9_U; 1485 1486 1487 1488 1489 typedef union tagEepPortLogic12 1490 { 1491 1492 struct 1493 { 1494 UINT32 transmitposteddatafccredits : 12 ; 1495 UINT32 transmitpostedheaderfccredits : 8 ; 1496 UINT32 tx_pfc_status : 12 ; 1497 } Bits; 1498 1499 1500 UINT32 UInt32; 1501 1502 } PCIE_EEP_PORT_LOGIC12_U; 1503 1504 1505 1506 1507 typedef union tagEepPortLogic13 1508 { 1509 1510 struct 1511 { 1512 UINT32 transmitnon_posteddatafccredits : 12 ; 1513 UINT32 transmitnon_postedheaderfccredits : 8 ; 1514 UINT32 tx_npfc_status : 12 ; 1515 } Bits; 1516 1517 1518 UINT32 UInt32; 1519 1520 } PCIE_EEP_PORT_LOGIC13_U; 1521 1522 1523 1524 1525 typedef union tagEepPortLogic14 1526 { 1527 1528 struct 1529 { 1530 UINT32 transmitcompletiondatafccredits : 12 ; 1531 UINT32 transmitcompletionheaderfccredits : 8 ; 1532 UINT32 tx_cplfc_status : 12 ; 1533 } Bits; 1534 1535 1536 UINT32 UInt32; 1537 1538 } PCIE_EEP_PORT_LOGIC14_U; 1539 1540 1541 1542 1543 typedef union tagEepPortLogic15 1544 { 1545 1546 struct 1547 { 1548 UINT32 rx_tlp_fc_credit_not_retured : 1 ; 1549 UINT32 tx_retry_buf_not_empty : 1 ; 1550 UINT32 rx_queue_not_empty : 1 ; 1551 UINT32 Reserved_79 : 13 ; 1552 UINT32 fc_latency_timer_override_value : 13 ; 1553 UINT32 Reserved_78 : 2 ; 1554 UINT32 fc_latency_timer_override_en : 1 ; 1555 } Bits; 1556 1557 1558 UINT32 UInt32; 1559 1560 } PCIE_EEP_PORT_LOGIC15_U; 1561 1562 1563 1564 1565 typedef union tagEepPortLogic16 1566 { 1567 1568 struct 1569 { 1570 UINT32 vc0posteddatacredits : 12 ; 1571 UINT32 vc0postedheadercredits : 8 ; 1572 UINT32 Reserved_81 : 1 ; 1573 UINT32 vc0_postedtlpqueuemode : 1 ; 1574 UINT32 vc0postedtlpqueuemode : 1 ; 1575 UINT32 vc0postedtlpqueuemo : 1 ; 1576 UINT32 Reserved_80 : 6 ; 1577 UINT32 tlptypeorderingforvc0 : 1 ; 1578 UINT32 rx_pque_ctrl : 1 ; 1579 } Bits; 1580 1581 1582 UINT32 UInt32; 1583 1584 } PCIE_EEP_PORT_LOGIC16_U; 1585 1586 1587 1588 1589 typedef union tagEepPortLogic17 1590 { 1591 1592 struct 1593 { 1594 UINT32 vc0non_posteddatacredits : 12 ; 1595 UINT32 vc0non_postedheadercredits : 8 ; 1596 UINT32 rx_npque_ctrl : 12 ; 1597 } Bits; 1598 1599 1600 UINT32 UInt32; 1601 1602 } PCIE_EEP_PORT_LOGIC17_U; 1603 1604 1605 1606 1607 typedef union tagEepPortLogic18 1608 { 1609 1610 struct 1611 { 1612 UINT32 vco_comp_data_credits : 12 ; 1613 UINT32 vc0_cpl_header_credt : 8 ; 1614 UINT32 Reserved_83 : 12 ; 1615 } Bits; 1616 1617 1618 UINT32 UInt32; 1619 1620 } PCIE_EEP_PORT_LOGIC18_U; 1621 1622 1623 1624 1625 typedef union tagEepPortLogic19 1626 { 1627 1628 struct 1629 { 1630 UINT32 vco_posted_data_que_path : 14 ; 1631 UINT32 Reserved_84 : 2 ; 1632 UINT32 vco_posted_head_queue_depth : 10 ; 1633 UINT32 vc_pbuf_ctrl : 6 ; 1634 } Bits; 1635 1636 1637 UINT32 UInt32; 1638 1639 } PCIE_EEP_PORT_LOGIC19_U; 1640 1641 1642 1643 1644 typedef union tagEepPortLogic20 1645 { 1646 1647 struct 1648 { 1649 UINT32 vco_np_data_que_depth : 14 ; 1650 UINT32 Reserved_86 : 2 ; 1651 UINT32 vco_np_header_que_depth : 10 ; 1652 UINT32 vc_npbuf_ctrl : 6 ; 1653 } Bits; 1654 1655 1656 UINT32 UInt32; 1657 1658 } PCIE_EEP_PORT_LOGIC20_U; 1659 1660 1661 1662 1663 typedef union tagEepPortLogic21 1664 { 1665 1666 struct 1667 { 1668 UINT32 vco_comp_data_queue_depth : 14 ; 1669 UINT32 Reserved_88 : 2 ; 1670 UINT32 vco_posted_head_queue_depth : 10 ; 1671 UINT32 Reserved_87 : 6 ; 1672 } Bits; 1673 1674 1675 UINT32 UInt32; 1676 1677 } PCIE_EEP_PORT_LOGIC21_U; 1678 1679 1680 1681 1682 typedef union tagEepPortLogic22 1683 { 1684 1685 struct 1686 { 1687 UINT32 n_fts : 8 ; 1688 UINT32 pre_determ_num_of_lane : 9 ; 1689 UINT32 det_sp_change : 1 ; 1690 UINT32 config_phy_tx_sw : 1 ; 1691 UINT32 config_tx_comp_rcv_bit : 1 ; 1692 UINT32 set_emp_level : 1 ; 1693 UINT32 Reserved_89 : 11 ; 1694 } Bits; 1695 1696 1697 UINT32 UInt32; 1698 1699 } PCIE_EEP_PORT_LOGIC22_U; 1700 1701 1702 1703 1704 typedef union tagEepPortlogic25 1705 { 1706 1707 struct 1708 { 1709 UINT32 remote_rd_req_size : 3 ; 1710 UINT32 Reserved_92 : 5 ; 1711 UINT32 remote_max_brd_tag : 8 ; 1712 UINT32 Reserved_91 : 16 ; 1713 } Bits; 1714 1715 1716 UINT32 UInt32; 1717 1718 } PCIE_EEP_PORTLOGIC25_U; 1719 1720 1721 1722 1723 typedef union tagEepPortlogic26 1724 { 1725 1726 struct 1727 { 1728 UINT32 resize_master_resp_compser : 1 ; 1729 UINT32 axi_ctrl1 : 31 ; 1730 } Bits; 1731 1732 1733 UINT32 UInt32; 1734 1735 } PCIE_EEP_PORTLOGIC26_U; 1736 1737 1738 1739 1740 typedef union tagEepPortlogic54 1741 { 1742 1743 struct 1744 { 1745 UINT32 region_index : 4 ; 1746 UINT32 Reserved_93 : 27 ; 1747 UINT32 iatu_view : 1 ; 1748 } Bits; 1749 1750 1751 UINT32 UInt32; 1752 1753 } PCIE_EEP_PORTLOGIC54_U; 1754 1755 1756 1757 1758 typedef union tagEepPortlogic55 1759 { 1760 1761 struct 1762 { 1763 UINT32 iatu1_type : 5 ; 1764 UINT32 iatu1_tc : 3 ; 1765 UINT32 iatu1_td : 1 ; 1766 UINT32 iatu1_attr : 2 ; 1767 UINT32 Reserved_97 : 5 ; 1768 UINT32 iatu1_at : 2 ; 1769 UINT32 Reserved_96 : 2 ; 1770 UINT32 iatu1_id : 3 ; 1771 UINT32 Reserved_95 : 9 ; 1772 } Bits; 1773 1774 1775 UINT32 UInt32; 1776 1777 } PCIE_EEP_PORTLOGIC55_U; 1778 1779 1780 1781 1782 typedef union tagEepPortlogic56 1783 { 1784 1785 struct 1786 { 1787 UINT32 iatu2_type : 8 ; 1788 UINT32 iatu2_bar_num : 3 ; 1789 UINT32 Reserved_101 : 3 ; 1790 UINT32 iatu2_tc_match_en : 1 ; 1791 UINT32 iatu2_td_match_en : 1 ; 1792 UINT32 iatu2_attr_match_en : 1 ; 1793 UINT32 Reserved_100 : 1 ; 1794 UINT32 iatu2_at_match_en : 1 ; 1795 UINT32 iatu2_func_num_match_en : 1 ; 1796 UINT32 iatu2_virtual_func_num_match_en : 1 ; 1797 UINT32 message_code_match_en : 1 ; 1798 UINT32 Reserved_99 : 2 ; 1799 UINT32 iatu2_response_code : 2 ; 1800 UINT32 Reserved_98 : 1 ; 1801 UINT32 iatu2_fuzzy_type_match_mode : 1 ; 1802 UINT32 iatu2_cfg_shift_mode : 1 ; 1803 UINT32 iatu2_ivert_mode : 1 ; 1804 UINT32 iatu2_match_mode : 1 ; 1805 UINT32 iatu2_region_en : 1 ; 1806 } Bits; 1807 1808 1809 UINT32 UInt32; 1810 1811 } PCIE_EEP_PORTLOGIC56_U; 1812 1813 1814 1815 1816 typedef union tagEepPortlogic57 1817 { 1818 1819 struct 1820 { 1821 UINT32 iatu_start_low : 12 ; 1822 UINT32 iatu_start_high : 20 ; 1823 } Bits; 1824 1825 1826 UINT32 UInt32; 1827 1828 } PCIE_EEP_PORTLOGIC57_U; 1829 1830 1831 1832 1833 typedef union tagEepPortlogic59 1834 { 1835 1836 struct 1837 { 1838 UINT32 iatu_limit_low : 12 ; 1839 UINT32 iatu_limit_high : 20 ; 1840 } Bits; 1841 1842 1843 UINT32 UInt32; 1844 1845 } PCIE_EEP_PORTLOGIC59_U; 1846 1847 1848 1849 1850 typedef union tagEepPortlogic60 1851 { 1852 1853 struct 1854 { 1855 UINT32 xlated_addr_high : 12 ; 1856 UINT32 xlated_addr_low : 20 ; 1857 } Bits; 1858 1859 1860 UINT32 UInt32; 1861 1862 } PCIE_EEP_PORTLOGIC60_U; 1863 1864 1865 1866 1867 typedef union tagEepPortlogic62 1868 { 1869 1870 struct 1871 { 1872 UINT32 dma_wr_eng_en : 1 ; 1873 UINT32 dma_wr_ena : 31 ; 1874 } Bits; 1875 1876 1877 UINT32 UInt32; 1878 1879 } PCIE_EEP_PORTLOGIC62_U; 1880 1881 1882 1883 1884 typedef union tagEepPortlogic63 1885 { 1886 1887 struct 1888 { 1889 UINT32 wr_doorbell_num : 3 ; 1890 UINT32 Reserved_103 : 28 ; 1891 UINT32 dma_wr_dbell_stop : 1 ; 1892 } Bits; 1893 1894 1895 UINT32 UInt32; 1896 1897 } PCIE_EEP_PORTLOGIC63_U; 1898 1899 1900 1901 1902 typedef union tagEepPortlogic64 1903 { 1904 1905 struct 1906 { 1907 UINT32 dma_read_eng_en : 1 ; 1908 UINT32 Reserved_104 : 31 ; 1909 } Bits; 1910 1911 1912 UINT32 UInt32; 1913 1914 } PCIE_EEP_PORTLOGIC64_U; 1915 1916 1917 1918 1919 typedef union tagEepPortlogic65 1920 { 1921 1922 struct 1923 { 1924 UINT32 rd_doorbell_num : 3 ; 1925 UINT32 Reserved_106 : 28 ; 1926 UINT32 dma_rd_dbell_stop : 1 ; 1927 } Bits; 1928 1929 1930 UINT32 UInt32; 1931 1932 } PCIE_EEP_PORTLOGIC65_U; 1933 1934 1935 1936 1937 typedef union tagEepPortlogic66 1938 { 1939 1940 struct 1941 { 1942 UINT32 done_int_status : 8 ; 1943 UINT32 Reserved_108 : 8 ; 1944 UINT32 abort_int_status : 8 ; 1945 UINT32 Reserved_107 : 8 ; 1946 } Bits; 1947 1948 1949 UINT32 UInt32; 1950 1951 } PCIE_EEP_PORTLOGIC66_U; 1952 1953 1954 1955 1956 typedef union tagEepPortlogic67 1957 { 1958 1959 struct 1960 { 1961 UINT32 done_int_mask : 8 ; 1962 UINT32 Reserved_111 : 8 ; 1963 UINT32 abort_int_mask : 8 ; 1964 UINT32 Reserved_110 : 8 ; 1965 } Bits; 1966 1967 1968 UINT32 UInt32; 1969 1970 } PCIE_EEP_PORTLOGIC67_U; 1971 1972 1973 1974 1975 typedef union tagEepPortlogic68 1976 { 1977 1978 struct 1979 { 1980 UINT32 done_int_clr : 8 ; 1981 UINT32 Reserved_114 : 8 ; 1982 UINT32 abort_int_clr : 8 ; 1983 UINT32 Reserved_113 : 8 ; 1984 } Bits; 1985 1986 1987 UINT32 UInt32; 1988 1989 } PCIE_EEP_PORTLOGIC68_U; 1990 1991 1992 1993 1994 typedef union tagEepPortlogic69 1995 { 1996 1997 struct 1998 { 1999 UINT32 app_rd_err_det : 8 ; 2000 UINT32 Reserved_116 : 8 ; 2001 UINT32 ll_element_fetch_err_det : 8 ; 2002 UINT32 Reserved_115 : 8 ; 2003 } Bits; 2004 2005 2006 UINT32 UInt32; 2007 2008 } PCIE_EEP_PORTLOGIC69_U; 2009 2010 2011 2012 2013 typedef union tagEepPortlogic74 2014 { 2015 2016 struct 2017 { 2018 UINT32 dma_wr_c0_imwr_data : 16 ; 2019 UINT32 dma_wr_c1_imwr_data : 16 ; 2020 } Bits; 2021 2022 2023 UINT32 UInt32; 2024 2025 } PCIE_EEP_PORTLOGIC74_U; 2026 2027 2028 2029 2030 typedef union tagEepPortlogic75 2031 { 2032 2033 struct 2034 { 2035 UINT32 wr_ch_ll_remote_abort_int_en : 8 ; 2036 UINT32 Reserved_118 : 8 ; 2037 UINT32 wr_ch_ll_local_abort_int_en : 8 ; 2038 UINT32 Reserved_117 : 8 ; 2039 } Bits; 2040 2041 2042 UINT32 UInt32; 2043 2044 } PCIE_EEP_PORTLOGIC75_U; 2045 2046 2047 2048 2049 typedef union tagEepPortlogic76 2050 { 2051 2052 struct 2053 { 2054 UINT32 done_int_status : 8 ; 2055 UINT32 Reserved_121 : 8 ; 2056 UINT32 abort_int_status : 8 ; 2057 UINT32 Reserved_120 : 8 ; 2058 } Bits; 2059 2060 2061 UINT32 UInt32; 2062 2063 } PCIE_EEP_PORTLOGIC76_U; 2064 2065 2066 2067 2068 typedef union tagEepPortlogic77 2069 { 2070 2071 struct 2072 { 2073 UINT32 done_int_mask : 8 ; 2074 UINT32 Reserved_123 : 8 ; 2075 UINT32 abort_int_mask : 8 ; 2076 UINT32 dma_rd_int_mask : 8 ; 2077 } Bits; 2078 2079 2080 UINT32 UInt32; 2081 2082 } PCIE_EEP_PORTLOGIC77_U; 2083 2084 2085 2086 2087 typedef union tagEepPortlogic78 2088 { 2089 2090 struct 2091 { 2092 UINT32 done_int_clr : 8 ; 2093 UINT32 Reserved_125 : 8 ; 2094 UINT32 abort_int_clr : 8 ; 2095 UINT32 dma_rd_int_clr : 8 ; 2096 } Bits; 2097 2098 2099 UINT32 UInt32; 2100 2101 } PCIE_EEP_PORTLOGIC78_U; 2102 2103 2104 2105 2106 typedef union tagEepPortlogic79 2107 { 2108 2109 struct 2110 { 2111 UINT32 app_wr_err_det : 8 ; 2112 UINT32 Reserved_126 : 8 ; 2113 UINT32 link_list_fetch_err_det : 8 ; 2114 UINT32 dma_rd_err_low : 8 ; 2115 } Bits; 2116 2117 2118 UINT32 UInt32; 2119 2120 } PCIE_EEP_PORTLOGIC79_U; 2121 2122 2123 2124 2125 typedef union tagEepPortlogic80 2126 { 2127 2128 struct 2129 { 2130 UINT32 unspt_request : 8 ; 2131 UINT32 completer_abort : 8 ; 2132 UINT32 cpl_time_out : 8 ; 2133 UINT32 data_poison : 8 ; 2134 } Bits; 2135 2136 2137 UINT32 UInt32; 2138 2139 } PCIE_EEP_PORTLOGIC80_U; 2140 2141 2142 2143 2144 typedef union tagEepPortlogic81 2145 { 2146 2147 struct 2148 { 2149 UINT32 remote_abort_int_en : 8 ; 2150 UINT32 Reserved_128 : 8 ; 2151 UINT32 local_abort_int_en : 8 ; 2152 UINT32 dma_rd_ll_err_ena : 8 ; 2153 } Bits; 2154 2155 2156 UINT32 UInt32; 2157 2158 } PCIE_EEP_PORTLOGIC81_U; 2159 2160 2161 2162 2163 typedef union tagEepPortlogic86 2164 { 2165 2166 struct 2167 { 2168 UINT32 channel_dir : 3 ; 2169 UINT32 Reserved_131 : 28 ; 2170 UINT32 dma_ch_con_idx : 1 ; 2171 } Bits; 2172 2173 2174 UINT32 UInt32; 2175 2176 } PCIE_EEP_PORTLOGIC86_U; 2177 2178 2179 2180 2181 typedef union tagEepPortlogic87 2182 { 2183 2184 struct 2185 { 2186 UINT32 cycle_bit : 1 ; 2187 UINT32 toggle_cycle_bit : 1 ; 2188 UINT32 load_link_pointer : 1 ; 2189 UINT32 local_int_en : 1 ; 2190 UINT32 remote_int_en : 1 ; 2191 UINT32 channel_status : 2 ; 2192 UINT32 Reserved_135 : 1 ; 2193 UINT32 consumer_cycle_state : 1 ; 2194 UINT32 linked_list_en : 1 ; 2195 UINT32 Reserved_134 : 2 ; 2196 UINT32 func_num_dma : 5 ; 2197 UINT32 Reserved_133 : 7 ; 2198 UINT32 no_snoop : 1 ; 2199 UINT32 ro : 1 ; 2200 UINT32 td : 1 ; 2201 UINT32 tc : 3 ; 2202 UINT32 dma_ch_ctrl : 2 ; 2203 } Bits; 2204 2205 2206 UINT32 UInt32; 2207 2208 } PCIE_EEP_PORTLOGIC87_U; 2209 2210 2211 2212 2213 typedef union tagEepPortlogic93 2214 { 2215 2216 struct 2217 { 2218 UINT32 Reserved_137 : 2 ; 2219 UINT32 dma_ll_ptr_low : 30 ; 2220 } Bits; 2221 2222 2223 UINT32 UInt32; 2224 2225 } PCIE_EEP_PORTLOGIC93_U; 2226 2227 2228 2229 #define PCIE_MEEP_SBAR23XLAT_LOWER_REG (0x0) 2230 #define PCIE_MEEP_SBAR23XLAT_UPPER_REG (0x4) 2231 #define PCIE_MEEP_SBAR45XLAT_LOWER_REG (0x8) 2232 #define PCIE_MEEP_SBAR45XLAT_UPPER_REG (0xC) 2233 #define PCIE_MEEP_SBAR23LMT_LOWER_REG (0x10) 2234 #define PCIE_MEEP_SBAR23LMT_UPPER_REG (0x14) 2235 #define PCIE_MEEP_SBAR45LMT_LOWER_REG (0x18) 2236 #define PCIE_MEEP_SBAR45LMT_UPPER_REG (0x1C) 2237 #define PCIE_MEEP_SDOORBELL_REG (0x20) 2238 #define PCIE_MEEP_SDOORBELL_MASK_REG (0x24) 2239 #define PCIE_MEEP_CBDF_SBDF_REG (0x28) 2240 #define PCIE_MEEP_NTB_CNTL_REG (0x2C) 2241 #define PCIE_MEEP_PCI_CFG_HDR0_REG (0x1000) 2242 #define PCIE_MEEP_PCI_CFG_HDR1_REG (0x1004) 2243 #define PCIE_MEEP_PCI_CFG_HDR2_REG (0x1008) 2244 #define PCIE_MEEP_PCI_CFG_HDR3_REG (0x100C) 2245 #define PCIE_MEEP_PCI_CFG_HDR4_REG (0x1010) 2246 #define PCIE_MEEP_PCI_CFG_HDR5_REG (0x1014) 2247 #define PCIE_MEEP_PCI_CFG_HDR6_REG (0x1018) 2248 #define PCIE_MEEP_PCI_CFG_HDR7_REG (0x101C) 2249 #define PCIE_MEEP_PCI_CFG_HDR8_REG (0x1020) 2250 #define PCIE_MEEP_PCI_CFG_HDR9_REG (0x1024) 2251 #define PCIE_MEEP_PCI_CFG_HDR10_REG (0x1028) 2252 #define PCIE_MEEP_PCI_CFG_HDR11_REG (0x102C) 2253 #define PCIE_MEEP_PCI_CFG_HDR12_REG (0x1030) 2254 #define PCIE_MEEP_PCI_CFG_HDR13_REG (0x1034) 2255 #define PCIE_MEEP_PCI_CFG_HDR14_REG (0x1038) 2256 #define PCIE_MEEP_PCI_CFG_HDR15_REG (0x103C) 2257 #define PCIE_MEEP_PCI_PM_CAP0_REG (0x1040) 2258 #define PCIE_MEEP_PCI_PM_CAP1_REG (0x1044) 2259 #define PCIE_MEEP_PCI_MSI_CAP0_REG (0x1050) 2260 #define PCIE_MEEP_PCI_MSI_CAP1_REG (0x1054) 2261 #define PCIE_MEEP_PCI_MSI_CAP2_REG (0x1058) 2262 #define PCIE_MEEP_PCI_MSI_CAP3_REG (0x105C) 2263 #define PCIE_MEEP_PCIE_CAP0_REG (0x1070) 2264 #define PCIE_MEEP_PCIE_CAP1_REG (0x1074) 2265 #define PCIE_MEEP_PCIE_CAP2_REG (0x1078) 2266 #define PCIE_MEEP_PCIE_CAP3_REG (0x107C) 2267 #define PCIE_MEEP_PCIE_CAP4_REG (0x1080) 2268 #define PCIE_MEEP_PCIE_CAP5_REG (0x1084) 2269 #define PCIE_MEEP_PCIE_CAP6_REG (0x1088) 2270 #define PCIE_MEEP_PCIE_CAP7_REG (0x108C) 2271 #define PCIE_MEEP_PCIE_CAP8_REG (0x1090) 2272 #define PCIE_MEEP_PCIE_CAP9_REG (0x1094) 2273 #define PCIE_MEEP_PCIE_CAP10_REG (0x1098) 2274 #define PCIE_MEEP_PCIE_CAP11_REG (0x109C) 2275 #define PCIE_MEEP_PCIE_CAP12_REG (0x10A0) 2276 #define PCIE_MEEP_SLOT_CAP_REG (0x10C0) 2277 #define PCIE_MEEP_AER_CAP0_REG (0x1100) 2278 #define PCIE_MEEP_AER_CAP1_REG (0x1104) 2279 #define PCIE_MEEP_AER_CAP2_REG (0x1108) 2280 #define PCIE_MEEP_AER_CAP3_REG (0x110C) 2281 #define PCIE_MEEP_AER_CAP4_REG (0x1110) 2282 #define PCIE_MEEP_AER_CAP5_REG (0x1114) 2283 #define PCIE_MEEP_AER_CAP6_REG (0x1118) 2284 #define PCIE_MEEP_AER_CAP7_REG (0x11C) 2285 #define PCIE_MEEP_AER_CAP8_REG (0x120) 2286 #define PCIE_MEEP_AER_CAP9_REG (0x124) 2287 #define PCIE_MEEP_AER_CAP10_REG (0x128) 2288 #define PCIE_MEEP_AER_CAP11_REG (0x112C) 2289 #define PCIE_MEEP_AER_CAP12_REG (0x1130) 2290 #define PCIE_MEEP_AER_CAP13_REG (0x1134) 2291 #define PCIE_MEEP_VC_CAP0_REG (0x1140) 2292 #define PCIE_MEEP_VC_CAP1_REG (0x1144) 2293 #define PCIE_MEEP_VC_CAP2_REG (0x1148) 2294 #define PCIE_MEEP_VC_CAP3_REG (0x114C) 2295 #define PCIE_MEEP_VC_CAP4_REG (0x1150) 2296 #define PCIE_MEEP_VC_CAP5_REG (0x1154) 2297 #define PCIE_MEEP_VC_CAP6_REG (0x1158) 2298 #define PCIE_MEEP_VC_CAP7_REG (0x115C) 2299 #define PCIE_MEEP_VC_CAP8_REG (0x1160) 2300 #define PCIE_MEEP_VC_CAP9_REG (0x1164) 2301 #define PCIE_MEEP_PORT_LOGIC0_REG (0x1700) 2302 #define PCIE_MEEP_PORT_LOGIC1_REG (0x1704) 2303 #define PCIE_MEEP_PORT_LOGIC2_REG (0x1708) 2304 #define PCIE_MEEP_PORT_LOGIC3_REG (0x170C) 2305 #define PCIE_MEEP_PORT_LOGIC4_REG (0x1710) 2306 #define PCIE_MEEP_PORT_LOGIC5_REG (0x1714) 2307 #define PCIE_MEEP_PORT_LOGIC6_REG (0x1718) 2308 #define PCIE_MEEP_PORT_LOGIC7_REG (0x171C) 2309 #define PCIE_MEEP_PORT_LOGIC8_REG (0x1720) 2310 #define PCIE_MEEP_PORT_LOGIC9_REG (0x1724) 2311 #define PCIE_MEEP_PORT_LOGIC10_REG (0x1728) 2312 #define PCIE_MEEP_PORT_LOGIC11_REG (0x172C) 2313 #define PCIE_MEEP_PORT_LOGIC12_REG (0x1730) 2314 #define PCIE_MEEP_PORT_LOGIC13_REG (0x1734) 2315 #define PCIE_MEEP_PORT_LOGIC14_REG (0x1738) 2316 #define PCIE_MEEP_PORT_LOGIC15_REG (0x173C) 2317 #define PCIE_MEEP_PORT_LOGIC16_REG (0x1748) 2318 #define PCIE_MEEP_PORT_LOGIC17_REG (0x174C) 2319 #define PCIE_MEEP_PORT_LOGIC18_REG (0x1750) 2320 #define PCIE_MEEP_PORT_LOGIC19_REG (0x17A8) 2321 #define PCIE_MEEP_PORT_LOGIC20_REG (0x17AC) 2322 #define PCIE_MEEP_PORT_LOGIC21_REG (0x17B0) 2323 #define PCIE_MEEP_PORT_LOGIC22_REG (0x180C) 2324 #define PCIE_MEEP_PORTLOGIC23_REG (0x1810) 2325 #define PCIE_MEEP_PORTLOGIC24_REG (0x1814) 2326 #define PCIE_MEEP_PORTLOGIC25_REG (0x1818) 2327 #define PCIE_MEEP_PORTLOGIC26_REG (0x181C) 2328 #define PCIE_MEEP_PORTLOGIC27_REG (0x1820) 2329 #define PCIE_MEEP_PORTLOGIC28_REG (0x1824) 2330 #define PCIE_MEEP_PORTLOGIC29_REG (0x1828) 2331 #define PCIE_MEEP_PORTLOGIC30_REG (0x182C) 2332 #define PCIE_MEEP_PORTLOGIC31_REG (0x1830) 2333 #define PCIE_MEEP_PORTLOGIC32_REG (0x1834) 2334 #define PCIE_MEEP_PORTLOGIC33_REG (0x1838) 2335 #define PCIE_MEEP_PORTLOGIC34_REG (0x183C) 2336 #define PCIE_MEEP_PORTLOGIC35_REG (0x1840) 2337 #define PCIE_MEEP_PORTLOGIC36_REG (0x1844) 2338 #define PCIE_MEEP_PORTLOGIC37_REG (0x1848) 2339 #define PCIE_MEEP_PORTLOGIC38_REG (0x184C) 2340 #define PCIE_MEEP_PORTLOGIC39_REG (0x1850) 2341 #define PCIE_MEEP_PORTLOGIC40_REG (0x1854) 2342 #define PCIE_MEEP_PORTLOGIC41_REG (0x1858) 2343 #define PCIE_MEEP_PORTLOGIC42_REG (0x185C) 2344 #define PCIE_MEEP_PORTLOGIC43_REG (0x1860) 2345 #define PCIE_MEEP_PORTLOGIC44_REG (0x1864) 2346 #define PCIE_MEEP_PORTLOGIC45_REG (0x1868) 2347 #define PCIE_MEEP_PORTLOGIC46_REG (0x186C) 2348 #define PCIE_MEEP_PORTLOGIC47_REG (0x1870) 2349 #define PCIE_MEEP_PORTLOGIC48_REG (0x1874) 2350 #define PCIE_MEEP_PORTLOGIC49_REG (0x1878) 2351 #define PCIE_MEEP_PORTLOGIC50_REG (0x187C) 2352 #define PCIE_MEEP_PORTLOGIC51_REG (0x1880) 2353 #define PCIE_MEEP_PORTLOGIC52_REG (0x1884) 2354 #define PCIE_MEEP_PORTLOGIC53_REG (0x1888) 2355 #define PCIE_MEEP_PORTLOGIC54_REG (0x1900) 2356 #define PCIE_MEEP_PORTLOGIC55_REG (0x1904) 2357 #define PCIE_MEEP_PORTLOGIC56_REG (0x908) 2358 #define PCIE_MEEP_PORTLOGIC57_REG (0x190C) 2359 #define PCIE_MEEP_PORTLOGIC58_REG (0x1910) 2360 #define PCIE_MEEP_PORTLOGIC59_REG (0x1914) 2361 #define PCIE_MEEP_PORTLOGIC60_REG (0x1918) 2362 #define PCIE_MEEP_PORTLOGIC61_REG (0x191C) 2363 #define PCIE_MEEP_PORTLOGIC62_REG (0x197C) 2364 #define PCIE_MEEP_PORTLOGIC63_REG (0x1980) 2365 #define PCIE_MEEP_PORTLOGIC64_REG (0x199C) 2366 #define PCIE_MEEP_PORTLOGIC65_REG (0x19A0) 2367 #define PCIE_MEEP_PORTLOGIC66_REG (0x19BC) 2368 #define PCIE_MEEP_PORTLOGIC67_REG (0x19C4) 2369 #define PCIE_MEEP_PORTLOGIC68_REG (0x19C8) 2370 #define PCIE_MEEP_PORTLOGIC69_REG (0x19CC) 2371 #define PCIE_MEEP_PORTLOGIC70_REG (0x19D0) 2372 #define PCIE_MEEP_PORTLOGIC71_REG (0x19D4) 2373 #define PCIE_MEEP_PORTLOGIC72_REG (0x19D8) 2374 #define PCIE_MEEP_PORTLOGIC73_REG (0x19DC) 2375 #define PCIE_MEEP_PORTLOGIC74_REG (0x19E0) 2376 #define PCIE_MEEP_PORTLOGIC75_REG (0x1A00) 2377 #define PCIE_MEEP_PORTLOGIC76_REG (0x1A10) 2378 #define PCIE_MEEP_PORTLOGIC77_REG (0x1A18) 2379 #define PCIE_MEEP_PORTLOGIC78_REG (0x1A1C) 2380 #define PCIE_MEEP_PORTLOGIC79_REG (0x1A24) 2381 #define PCIE_MEEP_PORTLOGIC80_REG (0x1A28) 2382 #define PCIE_MEEP_PORTLOGIC81_REG (0x1A34) 2383 #define PCIE_MEEP_PORTLOGIC82_REG (0x1A3C) 2384 #define PCIE_MEEP_PORTLOGIC83_REG (0x1A40) 2385 #define PCIE_MEEP_PORTLOGIC84_REG (0x1A44) 2386 #define PCIE_MEEP_PORTLOGIC85_REG (0xA48) 2387 #define PCIE_MEEP_PORTLOGIC86_REG (0xA6C) 2388 #define PCIE_MEEP_PORTLOGIC87_REG (0x1A70) 2389 #define PCIE_MEEP_PORTLOGIC88_REG (0x1A78) 2390 #define PCIE_MEEP_PORTLOGIC89_REG (0x1A7C) 2391 #define PCIE_MEEP_PORTLOGIC90_REG (0x1A80) 2392 #define PCIE_MEEP_PORTLOGIC91_REG (0x1A84) 2393 #define PCIE_MEEP_PORTLOGIC92_REG (0x1A88) 2394 #define PCIE_MEEP_PORTLOGIC93_REG (0x1A8C) 2395 #define PCIE_MEEP_PORTLOGIC94_REG (0x1A90) 2396 #define PCIE_MEEP_PBAR23XLAT_LOWER_REG (0x8000) 2397 #define PCIE_MEEP_PBAR23XLAT_UPPER_REG (0x8004) 2398 #define PCIE_MEEP_PBAR45XLAT_LOWER_REG (0x8008) 2399 #define PCIE_MEEP_PBAR45XLAT_UPPER_REG (0x800C) 2400 #define PCIE_MEEP_PBAR23LMT_LOWER_REG (0x8010) 2401 #define PCIE_MEEP_PBAR23LMT_UPPER_REG (0x8014) 2402 #define PCIE_MEEP_PBAR45LMT_LOWER_REG (0x8018) 2403 #define PCIE_MEEP_PBAR45LMT_UPPER_REG (0x801C) 2404 #define PCIE_MEEP_PDOORBELL_REG (0x8020) 2405 #define PCIE_MEEP_PDOORBELL_MASK_REG (0x8024) 2406 #define PCIE_MEEP_B2B_BAR01XLAT_LOWER_REG (0x8028) 2407 #define PCIE_MEEP_B2B_BAR01XLAT_UPPER_REG (0x802C) 2408 #define PCIE_MEEP_B2B_DOORBELL_REG (0x8030) 2409 #define PCIE_MEEP_SPAD0_REG (0x8038) 2410 #define PCIE_MEEP_SPAD1_REG (0x803C) 2411 #define PCIE_MEEP_SPAD2_REG (0x8040) 2412 #define PCIE_MEEP_SPAD3_REG (0x8044) 2413 #define PCIE_MEEP_SPAD4_REG (0x8048) 2414 #define PCIE_MEEP_SPAD5_REG (0x804C) 2415 #define PCIE_MEEP_SPAD6_REG (0x8050) 2416 #define PCIE_MEEP_SPAD7_REG (0x8054) 2417 #define PCIE_MEEP_SPAD8_REG (0x8058) 2418 #define PCIE_MEEP_SPAD9_REG (0x805C) 2419 #define PCIE_MEEP_SPAD10_REG (0x8060) 2420 #define PCIE_MEEP_SPAD11_REG (0x8064) 2421 #define PCIE_MEEP_SPAD12_REG (0x8068) 2422 #define PCIE_MEEP_SPAD13_REG (0x806C) 2423 #define PCIE_MEEP_SPAD14_REG (0x8070) 2424 #define PCIE_MEEP_SPAD15_REG (0x8074) 2425 #define PCIE_MEEP_SPAD16_REG (0x8078) 2426 #define PCIE_MEEP_SPAD17_REG (0x807C) 2427 #define PCIE_MEEP_SPAD18_REG (0x8080) 2428 #define PCIE_MEEP_SPAD19_REG (0x8084) 2429 #define PCIE_MEEP_SPAD20_REG (0x8088) 2430 #define PCIE_MEEP_SPAD21_REG (0x808C) 2431 #define PCIE_MEEP_SPAD22_REG (0x8090) 2432 #define PCIE_MEEP_SPAD23_REG (0x8094) 2433 #define PCIE_MEEP_SPAD24_REG (0x8098) 2434 #define PCIE_MEEP_SPAD25_REG (0x809C) 2435 #define PCIE_MEEP_SPAD26_REG (0x80A0) 2436 #define PCIE_MEEP_SPAD27_REG (0x80A4) 2437 #define PCIE_MEEP_SPAD28_REG (0x80A8) 2438 #define PCIE_MEEP_SPAD29_REG (0x80AC) 2439 #define PCIE_MEEP_SPAD30_REG (0x80B0) 2440 #define PCIE_MEEP_SPAD31_REG (0x80B4) 2441 #define PCIE_MEEP_PPD_REG (0x8138) 2442 #define PCIE_MEEP_DEVICE_VENDOR_ID_REG (0x9000) 2443 #define PCIE_MEEP_PCISTS_PCICMD_REG (0x9004) 2444 #define PCIE_MEEP_CCR_RID_REG (0x9008) 2445 #define PCIE_MEEP_PBAR01_BASE_LOWER_REG (0x9010) 2446 #define PCIE_MEEP_PBAR01_BASE_UPPER_REG (0x9014) 2447 #define PCIE_MEEP_PBAR23_BASE_LOWER_REG (0x9018) 2448 #define PCIE_MEEP_PBAR23_BASE_UPPER_REG (0x901C) 2449 #define PCIE_MEEP_PBAR45_BASE_LOWER_REG (0x9020) 2450 #define PCIE_MEEP_PBAR45_BASE_UPPER_REG (0x9024) 2451 #define PCIE_MEEP_CARDBUSCISPTR_REG (0x9028) 2452 #define PCIE_MEEP_SUBSYSTEMID_REG (0x902C) 2453 #define PCIE_MEEP_EXPANSIONROM_BASE_ADDR_REG (0x9030) 2454 #define PCIE_MEEP_CAPPTR_REG (0x9034) 2455 #define PCIE_MEEP_INTERRUPT_REG (0x903C) 2456 #define PCIE_MEEP_MSI_CAPABILITY_REGISTER_REG (0x9050) 2457 #define PCIE_MEEP_MSI_LOWER32_BITADDRESS_REG (0x9054) 2458 #define PCIE_MEEP_MSI_UPPER32_BIT_ADDRESS_REG (0x9058) 2459 #define PCIE_MEEP_MSI_DATA_REG (0x905C) 2460 #define PCIE_MEEP_MSI_MASK_REG (0x9060) 2461 #define PCIE_MEEP_MSI_PENDING_REG (0x9064) 2462 #define PCIE_MEEP_PCIE_CAPABILITY_REGISTER_REG (0x9070) 2463 #define PCIE_MEEP_DEVICE_CAPABILITIES_REGISTER_REG (0x9074) 2464 #define PCIE_MEEP_DEVICE_STATUS_REGISTER_REG (0x9078) 2465 #define PCIE_MEEP_LINK_CAPABILITY_REG (0x907C) 2466 #define PCIE_MEEP_LINK_CONTROL_STATUS_REG (0x9080) 2467 #define PCIE_MEEP_AER_CAP_HEADER_REG (0x9100) 2468 #define PCIE_MEEP_UC_ERROR_STATUS_REG (0x9104) 2469 #define PCIE_MEEP_UC_ERROR_MASK_REG (0x9108) 2470 #define PCIE_MEEP_UC_ERROR_SEVERITY_REG (0x910C) 2471 #define PCIE_MEEP_C_ERROR_STATUS_REG (0x9110) 2472 #define PCIE_MEEP_C_ERROR_MASK_REG (0x9114) 2473 #define PCIE_MEEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG (0x9118) 2474 #define PCIE_MEEP_HEADER_LOG_REGISTERS_1_REG (0x911C) 2475 #define PCIE_MEEP_HEADER_LOG_REGISTERS_2_REG (0x9120) 2476 #define PCIE_MEEP_HEADER_LOG_REGISTERS_3_REG (0x9124) 2477 #define PCIE_MEEP_HEADER_LOG_REGISTERS_4_REG (0x9128) 2478 #define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_1_REG (0x9130) 2479 #define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_2_REG (0x9134) 2480 #define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_3_REG (0x9138) 2481 #define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_4_REG (0x913C) 2482 #define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_LOWER_REG (0x9700) 2483 #define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_UPPER_REG (0x9704) 2484 #define PCIE_MEEP_NTB_IEP_BAR01_CTRL_REG (0x9708) 2485 #define PCIE_MEEP_NTB_IEP_BAR23_CTRL_REG (0x970C) 2486 #define PCIE_MEEP_NTB_IEP_BAR45_CTRL_REG (0x9710) 2487 #define PCIE_MEEP_MSI_CTRL_ADDRESS_LOWER_REG (0x9714) 2488 #define PCIE_MEEP_MSI_CTRL_ADDRESS_UPPER_REG (0x9718) 2489 #define PCIE_MEEP_MSI_CTRL_INT_EN_REG (0x971C) 2490 #define PCIE_MEEP_MSI_CTRL_INT0_MASK_REG (0x9720) 2491 #define PCIE_MEEP_MSI_CTRL_INT_STATUS_REG (0x9724) 2492 #define PCIE_MEEP_DBI_RO_WR_EN_REG (0x9728) 2493 #define PCIE_MEEP_AXI_ERR_RESPONSE_REG (0x972C) 2494 2495 2496 2497 typedef union tagMeepSbar23xlatLower 2498 { 2499 2500 struct 2501 { 2502 UINT32 Reserved_0 : 12 ; 2503 UINT32 sbar23xlat_lower : 20 ; 2504 } Bits; 2505 2506 2507 UINT32 UInt32; 2508 2509 } PCIE_MEEP_SBAR23XLAT_LOWER_U; 2510 2511 2512 2513 2514 typedef union tagMeepSbar45xlatLower 2515 { 2516 2517 struct 2518 { 2519 UINT32 Reserved_1 : 12 ; 2520 UINT32 sbar45xlat_lower : 20 ; 2521 } Bits; 2522 2523 2524 UINT32 UInt32; 2525 2526 } PCIE_MEEP_SBAR45XLAT_LOWER_U; 2527 2528 2529 2530 2531 typedef union tagMeepSbar23lmtLower 2532 { 2533 2534 struct 2535 { 2536 UINT32 Reserved_2 : 12 ; 2537 UINT32 sbar45limit_lower : 20 ; 2538 } Bits; 2539 2540 2541 UINT32 UInt32; 2542 2543 } PCIE_MEEP_SBAR23LMT_LOWER_U; 2544 2545 2546 2547 2548 typedef union tagMeepSbar45lmtLower 2549 { 2550 2551 struct 2552 { 2553 UINT32 Reserved_3 : 12 ; 2554 UINT32 sbar45limit_lower : 20 ; 2555 } Bits; 2556 2557 2558 UINT32 UInt32; 2559 2560 } PCIE_MEEP_SBAR45LMT_LOWER_U; 2561 2562 2563 2564 2565 typedef union tagMeepSbar45lmtUpper 2566 { 2567 2568 struct 2569 { 2570 UINT32 Reserved_4 : 12 ; 2571 UINT32 sbar45limit_upper : 20 ; 2572 } Bits; 2573 2574 2575 UINT32 UInt32; 2576 2577 } PCIE_MEEP_SBAR45LMT_UPPER_U; 2578 2579 2580 2581 2582 typedef union tagMeepCbdfSbdf 2583 { 2584 2585 struct 2586 { 2587 UINT32 sfunc : 3 ; 2588 UINT32 sdev : 5 ; 2589 UINT32 sbus : 8 ; 2590 UINT32 cap_sfunc : 3 ; 2591 UINT32 cap_sdev : 5 ; 2592 UINT32 cap_sbus : 8 ; 2593 } Bits; 2594 2595 2596 UINT32 UInt32; 2597 2598 } PCIE_MEEP_CBDF_SBDF_U; 2599 2600 2601 2602 2603 typedef union tagMeepNtbCntl 2604 { 2605 2606 struct 2607 { 2608 UINT32 s_link_disable : 1 ; 2609 UINT32 Reserved_6 : 1 ; 2610 UINT32 eep_shadow_en : 1 ; 2611 UINT32 Reserved_5 : 29 ; 2612 } Bits; 2613 2614 2615 UINT32 UInt32; 2616 2617 } PCIE_MEEP_NTB_CNTL_U; 2618 2619 2620 2621 2622 typedef union tagMeepPciCfgHdr0 2623 { 2624 2625 struct 2626 { 2627 UINT32 vendor_id : 16 ; 2628 UINT32 device_id : 16 ; 2629 } Bits; 2630 2631 2632 UINT32 UInt32; 2633 2634 } PCIE_MEEP_PCI_CFG_HDR0_U; 2635 2636 2637 2638 2639 typedef union tagMeepPciCfgHdr1 2640 { 2641 2642 struct 2643 { 2644 UINT32 io_space_enable : 1 ; 2645 UINT32 memory_space_enable : 1 ; 2646 UINT32 bus_master_enable : 1 ; 2647 UINT32 specialcycleenable : 1 ; 2648 UINT32 memory_write_and_invalidate : 1 ; 2649 UINT32 vga_palette_snoop_enable : 1 ; 2650 UINT32 parity_error_response : 1 ; 2651 UINT32 idsel_stepping_waitcycle_control : 1 ; 2652 UINT32 serr_enable : 1 ; 2653 UINT32 fastback_to_backenable : 1 ; 2654 UINT32 interrupt_disable : 1 ; 2655 UINT32 Reserved_10 : 5 ; 2656 UINT32 Reserved_9 : 3 ; 2657 UINT32 intx_status : 1 ; 2658 UINT32 capabilitieslist : 1 ; 2659 UINT32 pcibus66mhzcapable : 1 ; 2660 UINT32 Reserved_8 : 1 ; 2661 UINT32 fastback_to_back : 1 ; 2662 UINT32 masterdataparityerror : 1 ; 2663 UINT32 devsel_timing : 2 ; 2664 UINT32 signaled_target_abort : 1 ; 2665 UINT32 received_target_abort : 1 ; 2666 UINT32 received_master_abort : 1 ; 2667 UINT32 signaled_system_error : 1 ; 2668 UINT32 detected_parity_error : 1 ; 2669 } Bits; 2670 2671 2672 UINT32 UInt32; 2673 2674 } PCIE_MEEP_PCI_CFG_HDR1_U; 2675 2676 2677 2678 2679 typedef union tagMeepPciCfgHdr2 2680 { 2681 2682 struct 2683 { 2684 UINT32 revision_identification : 8 ; 2685 UINT32 Reserved_11 : 8 ; 2686 UINT32 sub_class : 8 ; 2687 UINT32 baseclass : 8 ; 2688 } Bits; 2689 2690 2691 UINT32 UInt32; 2692 2693 } PCIE_MEEP_PCI_CFG_HDR2_U; 2694 2695 2696 2697 2698 typedef union tagMeepPciCfgHdr3 2699 { 2700 2701 struct 2702 { 2703 UINT32 cache_line_size : 8 ; 2704 UINT32 mstr_lat_tmr : 8 ; 2705 UINT32 multi_function_device : 7 ; 2706 UINT32 hdr_type : 1 ; 2707 UINT32 bist : 8 ; 2708 } Bits; 2709 2710 2711 UINT32 UInt32; 2712 2713 } PCIE_MEEP_PCI_CFG_HDR3_U; 2714 2715 2716 2717 2718 typedef union tagMeepPciCfgHdr4 2719 { 2720 2721 struct 2722 { 2723 UINT32 sbar01_space_inicator : 1 ; 2724 UINT32 sbar01_type : 2 ; 2725 UINT32 sbar01_prefetchable : 1 ; 2726 UINT32 sbar01_lower : 28 ; 2727 } Bits; 2728 2729 2730 UINT32 UInt32; 2731 2732 } PCIE_MEEP_PCI_CFG_HDR4_U; 2733 2734 2735 2736 2737 typedef union tagMeepPciCfgHdr6 2738 { 2739 2740 struct 2741 { 2742 UINT32 sbar23_space_inicator : 1 ; 2743 UINT32 sbar23_type : 2 ; 2744 UINT32 sbar23_prefetchable : 1 ; 2745 UINT32 Reserved_12 : 8 ; 2746 UINT32 sbar23_lower : 20 ; 2747 } Bits; 2748 2749 2750 UINT32 UInt32; 2751 2752 } PCIE_MEEP_PCI_CFG_HDR6_U; 2753 2754 2755 2756 2757 typedef union tagMeepPciCfgHdr8 2758 { 2759 2760 struct 2761 { 2762 UINT32 sbar45_space_inicator : 1 ; 2763 UINT32 sbar45_type : 2 ; 2764 UINT32 sbar45_prefetchable : 1 ; 2765 UINT32 Reserved_13 : 8 ; 2766 UINT32 sbar45_lower : 20 ; 2767 } Bits; 2768 2769 2770 UINT32 UInt32; 2771 2772 } PCIE_MEEP_PCI_CFG_HDR8_U; 2773 2774 2775 2776 2777 typedef union tagMeepPciCfgHdr11 2778 { 2779 2780 struct 2781 { 2782 UINT32 subsystem_vendor_id : 16 ; 2783 UINT32 subsystemid : 16 ; 2784 } Bits; 2785 2786 2787 UINT32 UInt32; 2788 2789 } PCIE_MEEP_PCI_CFG_HDR11_U; 2790 2791 2792 2793 2794 typedef union tagMeepPciCfgHdr13 2795 { 2796 2797 struct 2798 { 2799 UINT32 cap_ptr : 8 ; 2800 UINT32 Reserved_14 : 24 ; 2801 } Bits; 2802 2803 2804 UINT32 UInt32; 2805 2806 } PCIE_MEEP_PCI_CFG_HDR13_U; 2807 2808 2809 2810 2811 typedef union tagMeepPciCfgHdr15 2812 { 2813 2814 struct 2815 { 2816 UINT32 int_line : 8 ; 2817 UINT32 int_pin : 8 ; 2818 UINT32 Min_Grant : 8 ; 2819 UINT32 Max_Latency : 8 ; 2820 } Bits; 2821 2822 2823 UINT32 UInt32; 2824 2825 } PCIE_MEEP_PCI_CFG_HDR15_U; 2826 2827 2828 2829 2830 typedef union tagMeepPciMsiCap0 2831 { 2832 2833 struct 2834 { 2835 UINT32 msi_cap_id : 8 ; 2836 UINT32 next_capability_pointer : 8 ; 2837 UINT32 msi_enabled : 1 ; 2838 UINT32 multiple_message_capable : 3 ; 2839 UINT32 multiple_message_enabled : 3 ; 2840 UINT32 msi_64_en : 1 ; 2841 UINT32 pvm : 1 ; 2842 UINT32 Reserved_18 : 7 ; 2843 } Bits; 2844 2845 2846 UINT32 UInt32; 2847 2848 } PCIE_MEEP_PCI_MSI_CAP0_U; 2849 2850 2851 2852 2853 typedef union tagMeepPciMsiCap1 2854 { 2855 2856 struct 2857 { 2858 UINT32 Reserved_20 : 2 ; 2859 UINT32 msi_addr_low : 30 ; 2860 } Bits; 2861 2862 2863 UINT32 UInt32; 2864 2865 } PCIE_MEEP_PCI_MSI_CAP1_U; 2866 2867 2868 2869 2870 typedef union tagMeepPciMsiCap3 2871 { 2872 2873 struct 2874 { 2875 UINT32 msi_data : 16 ; 2876 UINT32 Reserved_21 : 16 ; 2877 } Bits; 2878 2879 2880 UINT32 UInt32; 2881 2882 } PCIE_MEEP_PCI_MSI_CAP3_U; 2883 2884 2885 2886 2887 typedef union tagMeepPcieCap0 2888 { 2889 2890 struct 2891 { 2892 UINT32 pcie_cap_id : 8 ; 2893 UINT32 pcie_next_ptr : 8 ; 2894 UINT32 pcie_capability_version : 4 ; 2895 UINT32 device_port_type : 4 ; 2896 UINT32 slot_implemented : 1 ; 2897 UINT32 interrupt_message_number : 5 ; 2898 UINT32 Reserved_22 : 2 ; 2899 } Bits; 2900 2901 2902 UINT32 UInt32; 2903 2904 } PCIE_MEEP_PCIE_CAP0_U; 2905 2906 2907 2908 2909 typedef union tagMeepPcieCap1 2910 { 2911 2912 struct 2913 { 2914 UINT32 max_payload_size_supported : 3 ; 2915 UINT32 phantom_function_supported : 2 ; 2916 UINT32 extended_tagfield_supported : 1 ; 2917 UINT32 endpoint_l0sacceptable_latency : 3 ; 2918 UINT32 endpoint_l1acceptable_latency : 3 ; 2919 UINT32 undefined : 3 ; 2920 UINT32 Reserved_24 : 3 ; 2921 UINT32 captured_slot_power_limit_value : 8 ; 2922 UINT32 captured_slot_power_limit_scale : 2 ; 2923 UINT32 function_level_reset : 1 ; 2924 UINT32 dev_cap : 3 ; 2925 } Bits; 2926 2927 2928 UINT32 UInt32; 2929 2930 } PCIE_MEEP_PCIE_CAP1_U; 2931 2932 2933 2934 2935 typedef union tagMeepPcieCap2 2936 { 2937 2938 struct 2939 { 2940 UINT32 correctable_error_reporting_enable : 1 ; 2941 UINT32 non_fatal_error_reporting_enable : 1 ; 2942 UINT32 fatal_error_reporting_enable : 1 ; 2943 UINT32 urenable : 1 ; 2944 UINT32 enable_relaxed_ordering : 1 ; 2945 UINT32 max_payload_size : 3 ; 2946 UINT32 extended_tagfieldenable : 1 ; 2947 UINT32 phantom_function_enable : 1 ; 2948 UINT32 auxpowerpmenable : 1 ; 2949 UINT32 enablenosnoop : 1 ; 2950 UINT32 max_read_request_size : 3 ; 2951 UINT32 Reserved_26 : 1 ; 2952 UINT32 correctableerrordetected : 1 ; 2953 UINT32 non_fatalerrordetected : 1 ; 2954 UINT32 fatalerrordetected : 1 ; 2955 UINT32 unsupportedrequestdetected : 1 ; 2956 UINT32 auxpowerdetected : 1 ; 2957 UINT32 transactionpending : 1 ; 2958 UINT32 Reserved_25 : 10 ; 2959 } Bits; 2960 2961 2962 UINT32 UInt32; 2963 2964 } PCIE_MEEP_PCIE_CAP2_U; 2965 2966 2967 2968 2969 typedef union tagMeepPcieCap3 2970 { 2971 2972 struct 2973 { 2974 UINT32 max_link_speed : 4 ; 2975 UINT32 max_link_width : 6 ; 2976 UINT32 active_state_power_management : 2 ; 2977 UINT32 l0s_exitlatency : 3 ; 2978 UINT32 l1_exit_latency : 3 ; 2979 UINT32 clock_power_management : 1 ; 2980 UINT32 surprise_down_error_report_cap : 1 ; 2981 UINT32 data_link_layer_active_report_cap : 1 ; 2982 UINT32 link_bandwidth_noti_cap : 1 ; 2983 UINT32 aspm_option_compliance : 1 ; 2984 UINT32 Reserved_27 : 1 ; 2985 UINT32 port_number : 8 ; 2986 } Bits; 2987 2988 2989 UINT32 UInt32; 2990 2991 } PCIE_MEEP_PCIE_CAP3_U; 2992 2993 2994 2995 2996 typedef union tagMeepPcieCap4 2997 { 2998 2999 struct 3000 { 3001 UINT32 active_state_power_management : 2 ; 3002 UINT32 Reserved_30 : 1 ; 3003 UINT32 rcb : 1 ; 3004 UINT32 link_disable : 1 ; 3005 UINT32 retrain_link : 1 ; 3006 UINT32 common_clock_config : 1 ; 3007 UINT32 extended_sync : 1 ; 3008 UINT32 enable_clock_pwr_management : 1 ; 3009 UINT32 hw_auto_width_disable : 1 ; 3010 UINT32 link_bandwidth_management_int_en : 1 ; 3011 UINT32 link_auto_bandwidth_int_en : 1 ; 3012 UINT32 Reserved_29 : 4 ; 3013 UINT32 current_link_speed : 4 ; 3014 UINT32 negotiated_link_width : 6 ; 3015 UINT32 Reserved_28 : 1 ; 3016 UINT32 link_training : 1 ; 3017 UINT32 slot_clock_configration : 1 ; 3018 UINT32 data_link_layer_active : 1 ; 3019 UINT32 link_bandwidth_management_status : 1 ; 3020 UINT32 link_auto_bandwidth_status : 1 ; 3021 } Bits; 3022 3023 3024 UINT32 UInt32; 3025 3026 } PCIE_MEEP_PCIE_CAP4_U; 3027 3028 3029 3030 3031 typedef union tagMeepPcieCap5 3032 { 3033 3034 struct 3035 { 3036 UINT32 attentionbuttonpresent : 1 ; 3037 UINT32 powercontrollerpresent : 1 ; 3038 UINT32 mrlsensorpresent : 1 ; 3039 UINT32 attentionindicatorpresent : 1 ; 3040 UINT32 powerindicatorpresent : 1 ; 3041 UINT32 hot_plugsurprise : 1 ; 3042 UINT32 hot_plugcapable : 1 ; 3043 UINT32 slotpowerlimitvalue : 8 ; 3044 UINT32 slotpowerlimitscale : 2 ; 3045 UINT32 electromechanicalinterlockpresen : 1 ; 3046 UINT32 no_cmd_complete_support : 1 ; 3047 UINT32 phy_slot_number : 13 ; 3048 } Bits; 3049 3050 3051 UINT32 UInt32; 3052 3053 } PCIE_MEEP_PCIE_CAP5_U; 3054 3055 3056 3057 3058 typedef union tagMeepPcieCap6 3059 { 3060 3061 struct 3062 { 3063 UINT32 attentionbuttonpressedenable : 1 ; 3064 UINT32 powerfaultdetectedenable : 1 ; 3065 UINT32 mrlsensorchangedenable : 1 ; 3066 UINT32 presencedetectchangedenable : 1 ; 3067 UINT32 commandcompletedinterruptenable : 1 ; 3068 UINT32 hot_pluginterruptenable : 1 ; 3069 UINT32 attentionindicatorcontrol : 2 ; 3070 UINT32 powerindicatorcontrol : 2 ; 3071 UINT32 powercontrollercontrol : 1 ; 3072 UINT32 electromechanicalinterlockcontrol : 1 ; 3073 UINT32 datalinklayerstatechangedenable : 1 ; 3074 UINT32 Reserved_31 : 3 ; 3075 UINT32 attentionbuttonpressed : 1 ; 3076 UINT32 powerfaultdetected : 1 ; 3077 UINT32 mrlsensorchanged : 1 ; 3078 UINT32 presencedetectchanged : 1 ; 3079 UINT32 commandcompleted : 1 ; 3080 UINT32 mrlsensorstate : 1 ; 3081 UINT32 presencedetectstate : 1 ; 3082 UINT32 electromechanicalinterlockstatus : 1 ; 3083 UINT32 datalinklayerstatechanged : 1 ; 3084 UINT32 slot_ctrl_status : 7 ; 3085 } Bits; 3086 3087 3088 UINT32 UInt32; 3089 3090 } PCIE_MEEP_PCIE_CAP6_U; 3091 3092 3093 3094 3095 typedef union tagMeepPcieCap7 3096 { 3097 3098 struct 3099 { 3100 UINT32 systemerroroncorrectableerrorenable : 1 ; 3101 UINT32 systemerroronnon_fatalerrorenable : 1 ; 3102 UINT32 systemerroronfatalerrorenable : 1 ; 3103 UINT32 pmeinterruptenable : 1 ; 3104 UINT32 crssoftwarevisibilityenable : 1 ; 3105 UINT32 Reserved_32 : 11 ; 3106 UINT32 crssoftwarevisibility : 1 ; 3107 UINT32 root_cap : 15 ; 3108 } Bits; 3109 3110 3111 UINT32 UInt32; 3112 3113 } PCIE_MEEP_PCIE_CAP7_U; 3114 3115 3116 3117 3118 typedef union tagMeepPcieCap8 3119 { 3120 3121 struct 3122 { 3123 UINT32 pmerequesterid : 16 ; 3124 UINT32 pmestatus : 1 ; 3125 UINT32 pmepending : 1 ; 3126 UINT32 root_status : 14 ; 3127 } Bits; 3128 3129 3130 UINT32 UInt32; 3131 3132 } PCIE_MEEP_PCIE_CAP8_U; 3133 3134 3135 3136 3137 typedef union tagMeepPcieCap9 3138 { 3139 3140 struct 3141 { 3142 UINT32 completiontimeoutrangessupported : 4 ; 3143 UINT32 completiontimeoutdisablesupported : 1 ; 3144 UINT32 ariforwardingsupported : 1 ; 3145 UINT32 atomicoproutingsupported : 1 ; 3146 UINT32 _2_bitatomicopcompletersupported : 1 ; 3147 UINT32 _4_bitatomicopcompletersupported : 1 ; 3148 UINT32 _28_bitcascompletersupported : 1 ; 3149 UINT32 noro_enabledpr_prpassing : 1 ; 3150 UINT32 Reserved_33 : 1 ; 3151 UINT32 tphcompletersupported : 2 ; 3152 UINT32 dev_cap2 : 18 ; 3153 } Bits; 3154 3155 3156 UINT32 UInt32; 3157 3158 } PCIE_MEEP_PCIE_CAP9_U; 3159 3160 3161 3162 3163 typedef union tagMeepPcieCap10 3164 { 3165 3166 struct 3167 { 3168 UINT32 completiontimeoutvalue : 4 ; 3169 UINT32 completiontimeoutdisable : 1 ; 3170 UINT32 ariforwardingsupported : 1 ; 3171 UINT32 atomicoprequesterenable : 1 ; 3172 UINT32 atomicopegressblocking : 1 ; 3173 UINT32 idorequestenable : 1 ; 3174 UINT32 idocompletionenable : 1 ; 3175 UINT32 dev_ctrl2 : 22 ; 3176 } Bits; 3177 3178 3179 UINT32 UInt32; 3180 3181 } PCIE_MEEP_PCIE_CAP10_U; 3182 3183 3184 3185 3186 typedef union tagMeepPcieCap11 3187 { 3188 3189 struct 3190 { 3191 UINT32 Reserved_35 : 1 ; 3192 UINT32 gen1_suport : 1 ; 3193 UINT32 gen2_suport : 1 ; 3194 UINT32 gen3_suport : 1 ; 3195 UINT32 Reserved_34 : 4 ; 3196 UINT32 crosslink_supported : 1 ; 3197 UINT32 link_cap2 : 23 ; 3198 } Bits; 3199 3200 3201 UINT32 UInt32; 3202 3203 } PCIE_MEEP_PCIE_CAP11_U; 3204 3205 3206 3207 3208 typedef union tagMeepPcieCap12 3209 { 3210 3211 struct 3212 { 3213 UINT32 targetlinkspeed : 4 ; 3214 UINT32 entercompliance : 1 ; 3215 UINT32 hardwareautonomousspeeddisa : 1 ; 3216 UINT32 selectablede_empha : 1 ; 3217 UINT32 transmitmargin : 3 ; 3218 UINT32 _entermodifiedcompliance : 1 ; 3219 UINT32 compliancesos : 1 ; 3220 UINT32 de_emphasislevel : 4 ; 3221 UINT32 currentde_emphasislevel : 1 ; 3222 UINT32 equalizationcomplete : 1 ; 3223 UINT32 equalizationphase1successful : 1 ; 3224 UINT32 equalizationphase2successful : 1 ; 3225 UINT32 equalizationphase3successful : 1 ; 3226 UINT32 linkequalizationrequest : 1 ; 3227 UINT32 link_ctrl2_status2 : 10 ; 3228 } Bits; 3229 3230 3231 UINT32 UInt32; 3232 3233 } PCIE_MEEP_PCIE_CAP12_U; 3234 3235 3236 3237 3238 typedef union tagMeepSlotCap 3239 { 3240 3241 struct 3242 { 3243 UINT32 slotnumberingcapabilitiesid : 8 ; 3244 UINT32 nextcapabilitypointer : 8 ; 3245 UINT32 add_incardslotsprovided : 5 ; 3246 UINT32 firstinchassis : 1 ; 3247 UINT32 Reserved_36 : 2 ; 3248 UINT32 slot_cap : 8 ; 3249 } Bits; 3250 3251 3252 UINT32 UInt32; 3253 3254 } PCIE_MEEP_SLOT_CAP_U; 3255 3256 3257 3258 3259 typedef union tagMeepAerCap0 3260 { 3261 3262 struct 3263 { 3264 UINT32 pciexpressextendedcapabilityid : 16 ; 3265 UINT32 capabilityversion : 4 ; 3266 UINT32 aer_cap_hdr : 12 ; 3267 } Bits; 3268 3269 3270 UINT32 UInt32; 3271 3272 } PCIE_MEEP_AER_CAP0_U; 3273 3274 3275 3276 3277 typedef union tagMeepAerCap1 3278 { 3279 3280 struct 3281 { 3282 UINT32 Reserved_42 : 1 ; 3283 UINT32 Reserved_41 : 3 ; 3284 UINT32 datalinkprotocolerrorsta : 1 ; 3285 UINT32 surprisedownerrorstatus : 1 ; 3286 UINT32 Reserved_40 : 6 ; 3287 UINT32 poisonedtlpstatu : 1 ; 3288 UINT32 flowcontrolprotocolerrorst : 1 ; 3289 UINT32 completiontimeouts : 1 ; 3290 UINT32 completerabortstatus : 1 ; 3291 UINT32 receiveroverflowstatus : 1 ; 3292 UINT32 malformedtlpstatus : 1 ; 3293 UINT32 ecrcerrorstatus : 1 ; 3294 UINT32 ecrcerrorstat : 1 ; 3295 UINT32 unsupportedrequesterrorstatus : 1 ; 3296 UINT32 Reserved_39 : 3 ; 3297 UINT32 atomicopegressblockedstatus : 1 ; 3298 UINT32 uncorr_err_status : 7 ; 3299 } Bits; 3300 3301 3302 UINT32 UInt32; 3303 3304 } PCIE_MEEP_AER_CAP1_U; 3305 3306 3307 3308 3309 typedef union tagMeepAerCap2 3310 { 3311 3312 struct 3313 { 3314 UINT32 Reserved_46 : 1 ; 3315 UINT32 Reserved_45 : 3 ; 3316 UINT32 datalinkprotocolerrormask : 1 ; 3317 UINT32 surprisedownerrormask : 1 ; 3318 UINT32 Reserved_44 : 6 ; 3319 UINT32 poisonedtlpmask : 1 ; 3320 UINT32 flowcontrolprotocolerrormask : 1 ; 3321 UINT32 completiontimeoutmask : 1 ; 3322 UINT32 completerabortmask : 1 ; 3323 UINT32 unexpectedcompletionmask : 1 ; 3324 UINT32 receiveroverflowmask : 1 ; 3325 UINT32 malformedtlpmask : 1 ; 3326 UINT32 ecrcerrormask : 1 ; 3327 UINT32 unsupportedrequesterrormask : 1 ; 3328 UINT32 Reserved_43 : 3 ; 3329 UINT32 atomicopegressblockedmask : 1 ; 3330 UINT32 uncorr_err_mask : 7 ; 3331 } Bits; 3332 3333 3334 UINT32 UInt32; 3335 3336 } PCIE_MEEP_AER_CAP2_U; 3337 3338 3339 3340 3341 typedef union tagMeepAerCap3 3342 { 3343 3344 struct 3345 { 3346 UINT32 Reserved_50 : 1 ; 3347 UINT32 Reserved_49 : 3 ; 3348 UINT32 datalinkprotocolerrorsever : 1 ; 3349 UINT32 surprisedownerrorseverity : 1 ; 3350 UINT32 Reserved_48 : 6 ; 3351 UINT32 poisonedtlpseverity : 1 ; 3352 UINT32 flowcontrolprotocolerrorseveri : 1 ; 3353 UINT32 completiontimeoutseverity : 1 ; 3354 UINT32 completerabortseverity : 1 ; 3355 UINT32 unexpectedcompletionseverity : 1 ; 3356 UINT32 receiveroverflowseverity : 1 ; 3357 UINT32 malformedtlpseverity : 1 ; 3358 UINT32 ecrcerrorseverity : 1 ; 3359 UINT32 unsupportedrequesterrorseverity : 1 ; 3360 UINT32 Reserved_47 : 3 ; 3361 UINT32 atomicopegressblockedseverity : 1 ; 3362 UINT32 uncorr_err_ser : 7 ; 3363 } Bits; 3364 3365 3366 UINT32 UInt32; 3367 3368 } PCIE_MEEP_AER_CAP3_U; 3369 3370 3371 3372 3373 typedef union tagMeepAerCap4 3374 { 3375 3376 struct 3377 { 3378 UINT32 receivererrorstatus : 1 ; 3379 UINT32 Reserved_52 : 5 ; 3380 UINT32 badtlpstatus : 1 ; 3381 UINT32 baddllpstatus : 1 ; 3382 UINT32 replay_numrolloverstatus : 1 ; 3383 UINT32 Reserved_51 : 3 ; 3384 UINT32 replytimertimeoutstatus : 1 ; 3385 UINT32 advisorynon_fatalerrorstatus : 1 ; 3386 UINT32 corr_err_status : 18 ; 3387 } Bits; 3388 3389 3390 UINT32 UInt32; 3391 3392 } PCIE_MEEP_AER_CAP4_U; 3393 3394 3395 3396 3397 typedef union tagMeepAerCap5 3398 { 3399 3400 struct 3401 { 3402 UINT32 receivererrormask : 1 ; 3403 UINT32 Reserved_54 : 5 ; 3404 UINT32 badtlpmask : 1 ; 3405 UINT32 baddllpmask : 1 ; 3406 UINT32 replay_numrollovermask : 1 ; 3407 UINT32 Reserved_53 : 3 ; 3408 UINT32 replytimertimeoutmask : 1 ; 3409 UINT32 advisorynon_fatalerrormask : 1 ; 3410 UINT32 corr_err_mask : 18 ; 3411 } Bits; 3412 3413 3414 UINT32 UInt32; 3415 3416 } PCIE_MEEP_AER_CAP5_U; 3417 3418 3419 3420 3421 typedef union tagMeepAerCap6 3422 { 3423 3424 struct 3425 { 3426 UINT32 firsterrorpointer : 5 ; 3427 UINT32 ecrcgenerationcapability : 1 ; 3428 UINT32 ecrcgenerationenable : 1 ; 3429 UINT32 ecrccheckcapable : 1 ; 3430 UINT32 ecrccheckenable : 1 ; 3431 UINT32 adv_cap_ctrl : 23 ; 3432 } Bits; 3433 3434 3435 UINT32 UInt32; 3436 3437 } PCIE_MEEP_AER_CAP6_U; 3438 3439 3440 3441 3442 typedef union tagMeepAerCap11 3443 { 3444 3445 struct 3446 { 3447 UINT32 correctableerrorreportingenable : 1 ; 3448 UINT32 non_fatalerrorreportingenable : 1 ; 3449 UINT32 fatalerrorreportingenable : 1 ; 3450 UINT32 root_err_cmd : 29 ; 3451 } Bits; 3452 3453 3454 UINT32 UInt32; 3455 3456 } PCIE_MEEP_AER_CAP11_U; 3457 3458 3459 3460 3461 typedef union tagMeepAerCap12 3462 { 3463 3464 struct 3465 { 3466 UINT32 err_correceived : 1 ; 3467 UINT32 multipleerr_correceived : 1 ; 3468 UINT32 err_fatal_nonfatalreceived : 1 ; 3469 UINT32 multipleerr_fatal_nonfatalreceived : 1 ; 3470 UINT32 firstuncorrectablefatal : 1 ; 3471 UINT32 non_fatalerrormessagesreceived : 1 ; 3472 UINT32 fatalerrormessagesreceived : 1 ; 3473 UINT32 Reserved_57 : 20 ; 3474 UINT32 root_err_status : 5 ; 3475 } Bits; 3476 3477 3478 UINT32 UInt32; 3479 3480 } PCIE_MEEP_AER_CAP12_U; 3481 3482 3483 3484 3485 typedef union tagMeepAerCap13 3486 { 3487 3488 struct 3489 { 3490 UINT32 err_corsourceidentification : 16 ; 3491 UINT32 err_src_id : 16 ; 3492 } Bits; 3493 3494 3495 UINT32 UInt32; 3496 3497 } PCIE_MEEP_AER_CAP13_U; 3498 3499 3500 3501 3502 typedef union tagMeepVcCap0 3503 { 3504 3505 struct 3506 { 3507 UINT32 pciexpressextendedcapabilityid : 16 ; 3508 UINT32 capabilityversion : 4 ; 3509 UINT32 vc_cap_hdr : 12 ; 3510 } Bits; 3511 3512 3513 UINT32 UInt32; 3514 3515 } PCIE_MEEP_VC_CAP0_U; 3516 3517 3518 3519 3520 typedef union tagMeepVcCap1 3521 { 3522 3523 struct 3524 { 3525 UINT32 extendedvccount : 3 ; 3526 UINT32 Reserved_60 : 1 ; 3527 UINT32 lowpriorityextendedvccount : 3 ; 3528 UINT32 Reserved_59 : 1 ; 3529 UINT32 referenceclock : 2 ; 3530 UINT32 portarbitrationtableentrysize : 2 ; 3531 UINT32 vc_cap1 : 20 ; 3532 } Bits; 3533 3534 3535 UINT32 UInt32; 3536 3537 } PCIE_MEEP_VC_CAP1_U; 3538 3539 3540 3541 3542 typedef union tagMeepVcCap2 3543 { 3544 3545 struct 3546 { 3547 UINT32 vcarbitrationcapability : 8 ; 3548 UINT32 Reserved_61 : 16 ; 3549 UINT32 vc_cap2 : 8 ; 3550 } Bits; 3551 3552 3553 UINT32 UInt32; 3554 3555 } PCIE_MEEP_VC_CAP2_U; 3556 3557 3558 3559 3560 typedef union tagMeepVcCap3 3561 { 3562 3563 struct 3564 { 3565 UINT32 loadvcarbitrationtable : 1 ; 3566 UINT32 vcarbitrationselect : 3 ; 3567 UINT32 Reserved_63 : 12 ; 3568 UINT32 arbitrationtablestatus : 1 ; 3569 UINT32 Reserved_62 : 15 ; 3570 } Bits; 3571 3572 3573 UINT32 UInt32; 3574 3575 } PCIE_MEEP_VC_CAP3_U; 3576 3577 3578 3579 3580 typedef union tagMeepVcCap4 3581 { 3582 3583 struct 3584 { 3585 UINT32 portarbitrationcapability : 8 ; 3586 UINT32 Reserved_66 : 6 ; 3587 UINT32 Reserved_65 : 1 ; 3588 UINT32 rejectsnooptransactions : 1 ; 3589 UINT32 maximumtimeslots : 7 ; 3590 UINT32 Reserved_64 : 1 ; 3591 UINT32 vc_res_cap : 8 ; 3592 } Bits; 3593 3594 3595 UINT32 UInt32; 3596 3597 } PCIE_MEEP_VC_CAP4_U; 3598 3599 3600 3601 3602 typedef union tagMeepVcCap5 3603 { 3604 3605 struct 3606 { 3607 UINT32 tc_vcmap : 8 ; 3608 UINT32 Reserved_69 : 8 ; 3609 UINT32 loadportarbitrationtable : 1 ; 3610 UINT32 portarbitrationselec : 3 ; 3611 UINT32 Reserved_68 : 4 ; 3612 UINT32 vcid : 3 ; 3613 UINT32 Reserved_67 : 4 ; 3614 UINT32 vc_res_ctrl : 1 ; 3615 } Bits; 3616 3617 3618 UINT32 UInt32; 3619 3620 } PCIE_MEEP_VC_CAP5_U; 3621 3622 3623 3624 3625 typedef union tagMeepVcCap6 3626 { 3627 3628 struct 3629 { 3630 UINT32 Reserved_70 : 16 ; 3631 UINT32 portarbitrationtablestatus : 1 ; 3632 UINT32 vcnegotiationpending : 1 ; 3633 UINT32 vc_res_status : 14 ; 3634 } Bits; 3635 3636 3637 UINT32 UInt32; 3638 3639 } PCIE_MEEP_VC_CAP6_U; 3640 3641 3642 3643 3644 typedef union tagMeepVcCap7 3645 { 3646 3647 struct 3648 { 3649 UINT32 portarbitrationcapability : 8 ; 3650 UINT32 Reserved_73 : 6 ; 3651 UINT32 Reserved_72 : 1 ; 3652 UINT32 rejectsnooptransactions : 1 ; 3653 UINT32 maximumtimeslots : 7 ; 3654 UINT32 Reserved_71 : 1 ; 3655 UINT32 vc_res_cap0 : 8 ; 3656 } Bits; 3657 3658 3659 UINT32 UInt32; 3660 3661 } PCIE_MEEP_VC_CAP7_U; 3662 3663 3664 3665 3666 typedef union tagMeepVcCap8 3667 { 3668 3669 struct 3670 { 3671 UINT32 tc_vcmap : 8 ; 3672 UINT32 Reserved_76 : 8 ; 3673 UINT32 loadportarbitrationtable : 1 ; 3674 UINT32 portarbitrationselect : 3 ; 3675 UINT32 Reserved_75 : 4 ; 3676 UINT32 vcid : 3 ; 3677 UINT32 Reserved_74 : 4 ; 3678 UINT32 vc_res_ctrl0 : 1 ; 3679 } Bits; 3680 3681 3682 UINT32 UInt32; 3683 3684 } PCIE_MEEP_VC_CAP8_U; 3685 3686 3687 3688 3689 typedef union tagMeepVcCap9 3690 { 3691 3692 struct 3693 { 3694 UINT32 Reserved_77 : 16 ; 3695 UINT32 arbitrationtablestatus : 1 ; 3696 UINT32 vcnegotiationpending : 1 ; 3697 UINT32 vc_res_status0 : 14 ; 3698 } Bits; 3699 3700 3701 UINT32 UInt32; 3702 3703 } PCIE_MEEP_VC_CAP9_U; 3704 3705 3706 3707 3708 typedef union tagMeepPortLogic0 3709 { 3710 3711 struct 3712 { 3713 UINT32 ack_lat_timer : 16 ; 3714 UINT32 replay_timer : 16 ; 3715 } Bits; 3716 3717 3718 UINT32 UInt32; 3719 3720 } PCIE_MEEP_PORT_LOGIC0_U; 3721 3722 3723 3724 3725 typedef union tagMeepPortLogic2 3726 { 3727 3728 struct 3729 { 3730 UINT32 linknumber : 8 ; 3731 UINT32 Reserved_80 : 7 ; 3732 UINT32 forcelink : 1 ; 3733 UINT32 linkstate : 6 ; 3734 UINT32 Reserved_79 : 2 ; 3735 UINT32 port_force_link : 8 ; 3736 } Bits; 3737 3738 3739 UINT32 UInt32; 3740 3741 } PCIE_MEEP_PORT_LOGIC2_U; 3742 3743 3744 3745 3746 typedef union tagMeepPortLogic3 3747 { 3748 3749 struct 3750 { 3751 UINT32 ackfrequency : 8 ; 3752 UINT32 n_fts : 8 ; 3753 UINT32 commonclockn_fts : 8 ; 3754 UINT32 l0sentrancelatency : 3 ; 3755 UINT32 l1entrancelatency : 3 ; 3756 UINT32 enteraspml1withoutreceiveinl0s : 1 ; 3757 UINT32 ack_aspm : 1 ; 3758 } Bits; 3759 3760 3761 UINT32 UInt32; 3762 3763 } PCIE_MEEP_PORT_LOGIC3_U; 3764 3765 3766 3767 3768 typedef union tagMeepPortLogic4 3769 { 3770 3771 struct 3772 { 3773 UINT32 vendorspecificdllprequest : 1 ; 3774 UINT32 scrambledisable : 1 ; 3775 UINT32 loopbackenable : 1 ; 3776 UINT32 resetassert : 1 ; 3777 UINT32 Reserved_83 : 1 ; 3778 UINT32 dlllinkenable : 1 ; 3779 UINT32 Reserved_82 : 1 ; 3780 UINT32 fastlinkmode : 1 ; 3781 UINT32 Reserved_81 : 8 ; 3782 UINT32 linkmodeenable : 6 ; 3783 UINT32 crosslinkenable : 1 ; 3784 UINT32 crosslinkactive : 1 ; 3785 UINT32 port_link_ctrl : 8 ; 3786 } Bits; 3787 3788 3789 UINT32 UInt32; 3790 3791 } PCIE_MEEP_PORT_LOGIC4_U; 3792 3793 3794 3795 3796 typedef union tagMeepPortLogic5 3797 { 3798 3799 struct 3800 { 3801 UINT32 insertlaneskewfortransmit : 24 ; 3802 UINT32 flowcontroldisable : 1 ; 3803 UINT32 ack_nakdisable : 1 ; 3804 UINT32 Reserved_84 : 5 ; 3805 UINT32 lane_skew : 1 ; 3806 } Bits; 3807 3808 3809 UINT32 UInt32; 3810 3811 } PCIE_MEEP_PORT_LOGIC5_U; 3812 3813 3814 3815 3816 typedef union tagMeepPortLogic6 3817 { 3818 3819 struct 3820 { 3821 UINT32 numberoftssymbols : 4 ; 3822 UINT32 Reserved_86 : 4 ; 3823 UINT32 numberofskpsymbols : 3 ; 3824 UINT32 Reserved_85 : 3 ; 3825 UINT32 timermodifierforreplaytimer : 5 ; 3826 UINT32 timermodifierforack_naklatencytimer : 5 ; 3827 UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ; 3828 UINT32 sym_num : 3 ; 3829 } Bits; 3830 3831 3832 UINT32 UInt32; 3833 3834 } PCIE_MEEP_PORT_LOGIC6_U; 3835 3836 3837 3838 3839 typedef union tagMeepPortLogic7 3840 { 3841 3842 struct 3843 { 3844 UINT32 vc0posteddataqueuedepth : 11 ; 3845 UINT32 Reserved_87 : 4 ; 3846 UINT32 sym_timer : 1 ; 3847 UINT32 maskfunctionmismatchfilteringfo : 1 ; 3848 UINT32 maskpoisonedtlpfiltering : 1 ; 3849 UINT32 maskbarmatchfiltering : 1 ; 3850 UINT32 masktype1configurationrequestfiltering : 1 ; 3851 UINT32 masklockedrequestfiltering : 1 ; 3852 UINT32 masktagerrorrulesforreceivedcompletions : 1 ; 3853 UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ; 3854 UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ; 3855 UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ; 3856 UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ; 3857 UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ; 3858 UINT32 maske_crcerror_filtering : 1 ; 3859 UINT32 maske_crcerror_filtering_forcompletions : 1 ; 3860 UINT32 message_control : 1 ; 3861 UINT32 maskfilteringofreceived : 1 ; 3862 UINT32 flt_mask1 : 1 ; 3863 } Bits; 3864 3865 3866 UINT32 UInt32; 3867 3868 } PCIE_MEEP_PORT_LOGIC7_U; 3869 3870 3871 3872 3873 typedef union tagMeepPortLogic8 3874 { 3875 3876 struct 3877 { 3878 UINT32 cx_flt_mask_venmsg0_drop : 1 ; 3879 UINT32 cx_flt_mask_venmsg1_drop : 1 ; 3880 UINT32 cx_flt_mask_dabort_4ucpl : 1 ; 3881 UINT32 cx_flt_mask_handle_flush : 1 ; 3882 UINT32 flt_mask2 : 28 ; 3883 } Bits; 3884 3885 3886 UINT32 UInt32; 3887 3888 } PCIE_MEEP_PORT_LOGIC8_U; 3889 3890 3891 3892 3893 typedef union tagMeepPortLogic9 3894 { 3895 3896 struct 3897 { 3898 UINT32 amba_multi_outbound_decomp_np : 1 ; 3899 UINT32 amba_obnp_ctrl : 31 ; 3900 } Bits; 3901 3902 3903 UINT32 UInt32; 3904 3905 } PCIE_MEEP_PORT_LOGIC9_U; 3906 3907 3908 3909 3910 typedef union tagMeepPortLogic12 3911 { 3912 3913 struct 3914 { 3915 UINT32 transmitposteddatafccredits : 12 ; 3916 UINT32 transmitpostedheaderfccredits : 8 ; 3917 UINT32 tx_pfc_status : 12 ; 3918 } Bits; 3919 3920 3921 UINT32 UInt32; 3922 3923 } PCIE_MEEP_PORT_LOGIC12_U; 3924 3925 3926 3927 3928 typedef union tagMeepPortLogic13 3929 { 3930 3931 struct 3932 { 3933 UINT32 transmitnon_posteddatafccredits : 12 ; 3934 UINT32 transmitnon_postedheaderfccredits : 8 ; 3935 UINT32 tx_npfc_status : 12 ; 3936 } Bits; 3937 3938 3939 UINT32 UInt32; 3940 3941 } PCIE_MEEP_PORT_LOGIC13_U; 3942 3943 3944 3945 3946 typedef union tagMeepPortLogic14 3947 { 3948 3949 struct 3950 { 3951 UINT32 transmitcompletiondatafccredits : 12 ; 3952 UINT32 transmitcompletionheaderfccredits : 8 ; 3953 UINT32 tx_cplfc_status : 12 ; 3954 } Bits; 3955 3956 3957 UINT32 UInt32; 3958 3959 } PCIE_MEEP_PORT_LOGIC14_U; 3960 3961 3962 3963 3964 typedef union tagMeepPortLogic15 3965 { 3966 3967 struct 3968 { 3969 UINT32 rx_tlp_fc_credit_not_retured : 1 ; 3970 UINT32 tx_retry_buf_not_empty : 1 ; 3971 UINT32 rx_queue_not_empty : 1 ; 3972 UINT32 Reserved_89 : 13 ; 3973 UINT32 fc_latency_timer_override_value : 13 ; 3974 UINT32 Reserved_88 : 2 ; 3975 UINT32 fc_latency_timer_override_en : 1 ; 3976 } Bits; 3977 3978 3979 UINT32 UInt32; 3980 3981 } PCIE_MEEP_PORT_LOGIC15_U; 3982 3983 3984 3985 3986 typedef union tagMeepPortLogic16 3987 { 3988 3989 struct 3990 { 3991 UINT32 vc0posteddatacredits : 12 ; 3992 UINT32 vc0postedheadercredits : 8 ; 3993 UINT32 Reserved_91 : 1 ; 3994 UINT32 vc0_postedtlpqueuemode : 1 ; 3995 UINT32 vc0postedtlpqueuemode : 1 ; 3996 UINT32 vc0postedtlpqueuemo : 1 ; 3997 UINT32 Reserved_90 : 6 ; 3998 UINT32 tlptypeorderingforvc0 : 1 ; 3999 UINT32 rx_pque_ctrl : 1 ; 4000 } Bits; 4001 4002 4003 UINT32 UInt32; 4004 4005 } PCIE_MEEP_PORT_LOGIC16_U; 4006 4007 4008 4009 4010 typedef union tagMeepPortLogic17 4011 { 4012 4013 struct 4014 { 4015 UINT32 vc0non_posteddatarcredits : 12 ; 4016 UINT32 vc0non_postedheadercredits : 8 ; 4017 UINT32 Reserved_93 : 12 ; 4018 } Bits; 4019 4020 4021 UINT32 UInt32; 4022 4023 } PCIE_MEEP_PORT_LOGIC17_U; 4024 4025 4026 4027 4028 typedef union tagMeepPortLogic18 4029 { 4030 4031 struct 4032 { 4033 UINT32 vco_comp_data_credits : 12 ; 4034 UINT32 vc0_cpl_header_credt : 8 ; 4035 UINT32 Reserved_94 : 12 ; 4036 } Bits; 4037 4038 4039 UINT32 UInt32; 4040 4041 } PCIE_MEEP_PORT_LOGIC18_U; 4042 4043 4044 4045 4046 typedef union tagMeepPortLogic19 4047 { 4048 4049 struct 4050 { 4051 UINT32 vco_posted_data_que_path : 14 ; 4052 UINT32 Reserved_95 : 2 ; 4053 UINT32 vco_posted_head_queue_depth : 10 ; 4054 UINT32 vc_pbuf_ctrl : 6 ; 4055 } Bits; 4056 4057 4058 UINT32 UInt32; 4059 4060 } PCIE_MEEP_PORT_LOGIC19_U; 4061 4062 4063 4064 4065 typedef union tagMeepPortLogic20 4066 { 4067 4068 struct 4069 { 4070 UINT32 vco_np_data_que_depth : 14 ; 4071 UINT32 Reserved_97 : 2 ; 4072 UINT32 vco_np_header_que_depth : 10 ; 4073 UINT32 vc_npbuf_ctrl : 6 ; 4074 } Bits; 4075 4076 4077 UINT32 UInt32; 4078 4079 } PCIE_MEEP_PORT_LOGIC20_U; 4080 4081 4082 4083 4084 typedef union tagMeepPortLogic21 4085 { 4086 4087 struct 4088 { 4089 UINT32 vco_comp_data_queue_depth : 14 ; 4090 UINT32 Reserved_99 : 2 ; 4091 UINT32 vco_posted_head_queue_depth : 10 ; 4092 UINT32 Reserved_98 : 6 ; 4093 } Bits; 4094 4095 4096 UINT32 UInt32; 4097 4098 } PCIE_MEEP_PORT_LOGIC21_U; 4099 4100 4101 4102 4103 typedef union tagMeepPortLogic22 4104 { 4105 4106 struct 4107 { 4108 UINT32 n_fts : 8 ; 4109 UINT32 pre_determ_num_of_lane : 9 ; 4110 UINT32 det_sp_change : 1 ; 4111 UINT32 config_phy_tx_sw : 1 ; 4112 UINT32 config_tx_comp_rcv_bit : 1 ; 4113 UINT32 set_emp_level : 1 ; 4114 UINT32 Reserved_100 : 11 ; 4115 } Bits; 4116 4117 4118 UINT32 UInt32; 4119 4120 } PCIE_MEEP_PORT_LOGIC22_U; 4121 4122 4123 4124 4125 typedef union tagMeepPortlogic25 4126 { 4127 4128 struct 4129 { 4130 UINT32 remote_rd_req_size : 3 ; 4131 UINT32 Reserved_103 : 5 ; 4132 UINT32 remote_max_brd_tag : 8 ; 4133 UINT32 Reserved_102 : 16 ; 4134 } Bits; 4135 4136 4137 UINT32 UInt32; 4138 4139 } PCIE_MEEP_PORTLOGIC25_U; 4140 4141 4142 4143 4144 typedef union tagMeepPortlogic26 4145 { 4146 4147 struct 4148 { 4149 UINT32 resize_master_resp_compser : 1 ; 4150 UINT32 axi_ctrl1 : 31 ; 4151 } Bits; 4152 4153 4154 UINT32 UInt32; 4155 4156 } PCIE_MEEP_PORTLOGIC26_U; 4157 4158 4159 4160 4161 typedef union tagMeepPortlogic55 4162 { 4163 4164 struct 4165 { 4166 UINT32 iatu1_type : 5 ; 4167 UINT32 iatu1_tc : 3 ; 4168 UINT32 iatu1_td : 1 ; 4169 UINT32 iatu1_attr : 2 ; 4170 UINT32 Reserved_107 : 5 ; 4171 UINT32 iatu1_at : 2 ; 4172 UINT32 Reserved_106 : 2 ; 4173 UINT32 iatu1_id : 3 ; 4174 UINT32 Reserved_105 : 9 ; 4175 } Bits; 4176 4177 4178 UINT32 UInt32; 4179 4180 } PCIE_MEEP_PORTLOGIC55_U; 4181 4182 4183 4184 4185 typedef union tagMeepPortlogic56 4186 { 4187 4188 struct 4189 { 4190 UINT32 iatu2_type : 8 ; 4191 UINT32 iatu2_bar_num : 3 ; 4192 UINT32 Reserved_111 : 3 ; 4193 UINT32 iatu2_tc_match_en : 1 ; 4194 UINT32 iatu2_td_match_en : 1 ; 4195 UINT32 iatu2_attr_match_en : 1 ; 4196 UINT32 Reserved_110 : 1 ; 4197 UINT32 iatu2_at_match_en : 1 ; 4198 UINT32 iatu2_func_num_match_en : 1 ; 4199 UINT32 iatu2_virtual_func_num_match_en : 1 ; 4200 UINT32 message_code_match_en : 1 ; 4201 UINT32 Reserved_109 : 2 ; 4202 UINT32 iatu2_response_code : 2 ; 4203 UINT32 Reserved_108 : 1 ; 4204 UINT32 iatu2_fuzzy_type_match_mode : 1 ; 4205 UINT32 iatu2_cfg_shift_mode : 1 ; 4206 UINT32 iatu2_ivert_mode : 1 ; 4207 UINT32 iatu2_match_mode : 1 ; 4208 UINT32 iatu2_region_en : 1 ; 4209 } Bits; 4210 4211 4212 UINT32 UInt32; 4213 4214 } PCIE_MEEP_PORTLOGIC56_U; 4215 4216 4217 4218 4219 typedef union tagMeepPortlogic57 4220 { 4221 4222 struct 4223 { 4224 UINT32 iatu_start_low : 12 ; 4225 UINT32 iatu_start_high : 20 ; 4226 } Bits; 4227 4228 4229 UINT32 UInt32; 4230 4231 } PCIE_MEEP_PORTLOGIC57_U; 4232 4233 4234 4235 4236 typedef union tagMeepPortlogic59 4237 { 4238 4239 struct 4240 { 4241 UINT32 iatu_limit_low : 12 ; 4242 UINT32 iatu_limit_high : 20 ; 4243 } Bits; 4244 4245 4246 UINT32 UInt32; 4247 4248 } PCIE_MEEP_PORTLOGIC59_U; 4249 4250 4251 4252 4253 typedef union tagMeepPortlogic60 4254 { 4255 4256 struct 4257 { 4258 UINT32 xlated_addr_high : 12 ; 4259 UINT32 xlated_addr_low : 20 ; 4260 } Bits; 4261 4262 4263 UINT32 UInt32; 4264 4265 } PCIE_MEEP_PORTLOGIC60_U; 4266 4267 4268 4269 4270 typedef union tagMeepPortlogic62 4271 { 4272 4273 struct 4274 { 4275 UINT32 dma_wr_eng_en : 1 ; 4276 UINT32 dma_wr_ena : 31 ; 4277 } Bits; 4278 4279 4280 UINT32 UInt32; 4281 4282 } PCIE_MEEP_PORTLOGIC62_U; 4283 4284 4285 4286 4287 typedef union tagMeepPortlogic63 4288 { 4289 4290 struct 4291 { 4292 UINT32 wr_doorbell_num : 3 ; 4293 UINT32 Reserved_115 : 28 ; 4294 UINT32 dma_wr_dbell_stop : 1 ; 4295 } Bits; 4296 4297 4298 UINT32 UInt32; 4299 4300 } PCIE_MEEP_PORTLOGIC63_U; 4301 4302 4303 4304 4305 typedef union tagMeepPortlogic64 4306 { 4307 4308 struct 4309 { 4310 UINT32 dma_read_eng_en : 1 ; 4311 UINT32 dma_rd_ena : 31 ; 4312 } Bits; 4313 4314 4315 UINT32 UInt32; 4316 4317 } PCIE_MEEP_PORTLOGIC64_U; 4318 4319 4320 4321 4322 typedef union tagMeepPortlogic65 4323 { 4324 4325 struct 4326 { 4327 UINT32 rd_doorbell_num : 3 ; 4328 UINT32 Reserved_117 : 28 ; 4329 UINT32 dma_rd_dbell_stop : 1 ; 4330 } Bits; 4331 4332 4333 UINT32 UInt32; 4334 4335 } PCIE_MEEP_PORTLOGIC65_U; 4336 4337 4338 4339 4340 typedef union tagMeepPortlogic66 4341 { 4342 4343 struct 4344 { 4345 UINT32 done_int_status : 1 ; 4346 UINT32 Reserved_119 : 15 ; 4347 UINT32 abort_int_status : 1 ; 4348 UINT32 Reserved_118 : 15 ; 4349 } Bits; 4350 4351 4352 UINT32 UInt32; 4353 4354 } PCIE_MEEP_PORTLOGIC66_U; 4355 4356 4357 4358 4359 typedef union tagMeepPortlogic67 4360 { 4361 4362 struct 4363 { 4364 UINT32 done_int_mask : 1 ; 4365 UINT32 Reserved_122 : 15 ; 4366 UINT32 abort_int_mask : 1 ; 4367 UINT32 Reserved_121 : 15 ; 4368 } Bits; 4369 4370 4371 UINT32 UInt32; 4372 4373 } PCIE_MEEP_PORTLOGIC67_U; 4374 4375 4376 4377 4378 typedef union tagMeepPortlogic68 4379 { 4380 4381 struct 4382 { 4383 UINT32 done_int_clr : 1 ; 4384 UINT32 Reserved_125 : 15 ; 4385 UINT32 abort_int_clr : 1 ; 4386 UINT32 Reserved_124 : 15 ; 4387 } Bits; 4388 4389 4390 UINT32 UInt32; 4391 4392 } PCIE_MEEP_PORTLOGIC68_U; 4393 4394 4395 4396 4397 typedef union tagMeepPortlogic69 4398 { 4399 4400 struct 4401 { 4402 UINT32 app_rd_err_det : 1 ; 4403 UINT32 Reserved_127 : 15 ; 4404 UINT32 ll_element_fetch_err_det : 1 ; 4405 UINT32 Reserved_126 : 15 ; 4406 } Bits; 4407 4408 4409 UINT32 UInt32; 4410 4411 } PCIE_MEEP_PORTLOGIC69_U; 4412 4413 4414 4415 4416 typedef union tagMeepPortlogic74 4417 { 4418 4419 struct 4420 { 4421 UINT32 dma_wr_c0_imwr_data : 16 ; 4422 UINT32 dma_wr_c1_imwr_data : 16 ; 4423 } Bits; 4424 4425 4426 UINT32 UInt32; 4427 4428 } PCIE_MEEP_PORTLOGIC74_U; 4429 4430 4431 4432 4433 typedef union tagMeepPortlogic75 4434 { 4435 4436 struct 4437 { 4438 UINT32 wr_ch_ll_remote_abort_int_en : 1 ; 4439 UINT32 Reserved_129 : 15 ; 4440 UINT32 wr_ch_ll_local_abort_int_en : 1 ; 4441 UINT32 Reserved_128 : 15 ; 4442 } Bits; 4443 4444 4445 UINT32 UInt32; 4446 4447 } PCIE_MEEP_PORTLOGIC75_U; 4448 4449 4450 4451 4452 typedef union tagMeepPortlogic76 4453 { 4454 4455 struct 4456 { 4457 UINT32 done_int_status : 1 ; 4458 UINT32 Reserved_132 : 15 ; 4459 UINT32 abort_int_status : 1 ; 4460 UINT32 Reserved_131 : 15 ; 4461 } Bits; 4462 4463 4464 UINT32 UInt32; 4465 4466 } PCIE_MEEP_PORTLOGIC76_U; 4467 4468 4469 4470 4471 typedef union tagMeepPortlogic77 4472 { 4473 4474 struct 4475 { 4476 UINT32 done_int_mask : 1 ; 4477 UINT32 Reserved_134 : 15 ; 4478 UINT32 abort_int_mask : 1 ; 4479 UINT32 dma_rd_int_mask : 15 ; 4480 } Bits; 4481 4482 4483 UINT32 UInt32; 4484 4485 } PCIE_MEEP_PORTLOGIC77_U; 4486 4487 4488 4489 4490 typedef union tagMeepPortlogic78 4491 { 4492 4493 struct 4494 { 4495 UINT32 done_int_clr : 1 ; 4496 UINT32 Reserved_136 : 15 ; 4497 UINT32 abort_int_clr : 1 ; 4498 UINT32 dma_rd_int_clr : 15 ; 4499 } Bits; 4500 4501 4502 UINT32 UInt32; 4503 4504 } PCIE_MEEP_PORTLOGIC78_U; 4505 4506 4507 4508 4509 typedef union tagMeepPortlogic79 4510 { 4511 4512 struct 4513 { 4514 UINT32 app_wr_err_det : 1 ; 4515 UINT32 Reserved_137 : 15 ; 4516 UINT32 link_list_fetch_err_det : 1 ; 4517 UINT32 dma_rd_err_low : 15 ; 4518 } Bits; 4519 4520 4521 UINT32 UInt32; 4522 4523 } PCIE_MEEP_PORTLOGIC79_U; 4524 4525 4526 4527 4528 typedef union tagMeepPortlogic80 4529 { 4530 4531 struct 4532 { 4533 UINT32 unspt_request : 8 ; 4534 UINT32 completer_abort : 8 ; 4535 UINT32 cpl_time_out : 8 ; 4536 UINT32 data_poison : 8 ; 4537 } Bits; 4538 4539 4540 UINT32 UInt32; 4541 4542 } PCIE_MEEP_PORTLOGIC80_U; 4543 4544 4545 4546 4547 typedef union tagMeepPortlogic81 4548 { 4549 4550 struct 4551 { 4552 UINT32 remote_abort_int_en : 1 ; 4553 UINT32 Reserved_139 : 15 ; 4554 UINT32 local_abort_int_en : 1 ; 4555 UINT32 dma_rd_ll_err_ena : 15 ; 4556 } Bits; 4557 4558 4559 UINT32 UInt32; 4560 4561 } PCIE_MEEP_PORTLOGIC81_U; 4562 4563 4564 4565 4566 typedef union tagMeepPortlogic86 4567 { 4568 4569 struct 4570 { 4571 UINT32 channel_dir : 3 ; 4572 UINT32 Reserved_143 : 28 ; 4573 UINT32 dma_ch_con_idx : 1 ; 4574 } Bits; 4575 4576 4577 UINT32 UInt32; 4578 4579 } PCIE_MEEP_PORTLOGIC86_U; 4580 4581 4582 4583 4584 typedef union tagMeepPortlogic87 4585 { 4586 4587 struct 4588 { 4589 UINT32 cycle_bit : 1 ; 4590 UINT32 toggle_cycle_bit : 1 ; 4591 UINT32 load_link_pointer : 1 ; 4592 UINT32 local_int_en : 1 ; 4593 UINT32 remote_int_en : 1 ; 4594 UINT32 channel_status : 2 ; 4595 UINT32 Reserved_147 : 1 ; 4596 UINT32 consumer_cycle_state : 1 ; 4597 UINT32 linked_list_en : 1 ; 4598 UINT32 Reserved_146 : 2 ; 4599 UINT32 func_num_dma : 5 ; 4600 UINT32 Reserved_145 : 7 ; 4601 UINT32 no_snoop : 1 ; 4602 UINT32 ro : 1 ; 4603 UINT32 td : 1 ; 4604 UINT32 tc : 3 ; 4605 UINT32 dma_ch_ctrl : 2 ; 4606 } Bits; 4607 4608 4609 UINT32 UInt32; 4610 4611 } PCIE_MEEP_PORTLOGIC87_U; 4612 4613 4614 4615 4616 typedef union tagMeepPortlogic93 4617 { 4618 4619 struct 4620 { 4621 UINT32 Reserved_150 : 2 ; 4622 UINT32 dma_ll_ptr_low : 30 ; 4623 } Bits; 4624 4625 4626 UINT32 UInt32; 4627 4628 } PCIE_MEEP_PORTLOGIC93_U; 4629 4630 4631 4632 4633 typedef union tagMeepPbar23xlatLower 4634 { 4635 4636 struct 4637 { 4638 UINT32 Reserved_151 : 12 ; 4639 UINT32 PBAR23_Xlat_Lower : 20 ; 4640 } Bits; 4641 4642 4643 UINT32 UInt32; 4644 4645 } PCIE_MEEP_PBAR23XLAT_LOWER_U; 4646 4647 4648 4649 4650 typedef union tagMeepPbar45xlatLower 4651 { 4652 4653 struct 4654 { 4655 UINT32 Reserved_153 : 12 ; 4656 UINT32 PBAR45_Xlat_Lower : 20 ; 4657 } Bits; 4658 4659 4660 UINT32 UInt32; 4661 4662 } PCIE_MEEP_PBAR45XLAT_LOWER_U; 4663 4664 4665 4666 4667 typedef union tagMeepPbar23lmtLower 4668 { 4669 4670 struct 4671 { 4672 UINT32 Reserved_154 : 12 ; 4673 UINT32 PBAR23_Limit_Lower : 20 ; 4674 } Bits; 4675 4676 4677 UINT32 UInt32; 4678 4679 } PCIE_MEEP_PBAR23LMT_LOWER_U; 4680 4681 4682 4683 4684 typedef union tagMeepPbar45lmtLower 4685 { 4686 4687 struct 4688 { 4689 UINT32 Reserved_155 : 12 ; 4690 UINT32 PBAR45_Limit_Lower : 20 ; 4691 } Bits; 4692 4693 4694 UINT32 UInt32; 4695 4696 } PCIE_MEEP_PBAR45LMT_LOWER_U; 4697 4698 4699 4700 4701 typedef union tagMeepPbar45lmtUpper 4702 { 4703 4704 struct 4705 { 4706 UINT32 Reserved_156 : 12 ; 4707 UINT32 PBAR45_Limit_Upper : 20 ; 4708 } Bits; 4709 4710 4711 UINT32 UInt32; 4712 4713 } PCIE_MEEP_PBAR45LMT_UPPER_U; 4714 4715 4716 4717 4718 typedef union tagMeepB2bBar01xlatLower 4719 { 4720 4721 struct 4722 { 4723 UINT32 Reserved_157 : 17 ; 4724 UINT32 B2B_PBAR01_Xlat_Lower : 15 ; 4725 } Bits; 4726 4727 4728 UINT32 UInt32; 4729 4730 } PCIE_MEEP_B2B_BAR01XLAT_Lower_U; 4731 4732 4733 4734 4735 typedef union tagMeepPpd 4736 { 4737 4738 struct 4739 { 4740 UINT32 port_def : 1 ; 4741 UINT32 Reserved_159 : 31 ; 4742 } Bits; 4743 4744 4745 UINT32 UInt32; 4746 4747 } PCIE_MEEP_PPD_U; 4748 4749 4750 4751 4752 typedef union tagMeepDeviceVendorId 4753 { 4754 4755 struct 4756 { 4757 UINT32 Vendor_ID : 16 ; 4758 UINT32 Device_ID : 16 ; 4759 } Bits; 4760 4761 4762 UINT32 UInt32; 4763 4764 } PCIE_MEEP_Device_Vendor_ID_U; 4765 4766 4767 4768 4769 typedef union tagMeepPcistsPcicmd 4770 { 4771 4772 struct 4773 { 4774 UINT32 io_space_enable : 1 ; 4775 UINT32 memory_space_enable : 1 ; 4776 UINT32 bus_master_enable : 1 ; 4777 UINT32 specialcycleenable : 1 ; 4778 UINT32 memory_write_and_invalidate : 1 ; 4779 UINT32 vga_palette_snoop_enable : 1 ; 4780 UINT32 parity_error_response : 1 ; 4781 UINT32 idsel_stepping_waitcycle_control : 1 ; 4782 UINT32 serr_enable : 1 ; 4783 UINT32 fastback_to_backenable : 1 ; 4784 UINT32 Interrupt_Disable : 1 ; 4785 UINT32 Reserved_164 : 5 ; 4786 UINT32 Reserved_163 : 3 ; 4787 UINT32 intx_status : 1 ; 4788 UINT32 capabilitieslist : 1 ; 4789 UINT32 pcibus66mhzcapable : 1 ; 4790 UINT32 Reserved_162 : 1 ; 4791 UINT32 fastback_to_back : 1 ; 4792 UINT32 masterdataparityerror : 1 ; 4793 UINT32 devsel_timing : 2 ; 4794 UINT32 Signaled_Target_Abort : 1 ; 4795 UINT32 Received_Target_Abort : 1 ; 4796 UINT32 Received_Master_Abort : 1 ; 4797 UINT32 Signaled_System_Error : 1 ; 4798 UINT32 Detected_Parity_Error : 1 ; 4799 } Bits; 4800 4801 4802 UINT32 UInt32; 4803 4804 } PCIE_MEEP_PCISTS_PCICMD_U; 4805 4806 4807 4808 4809 typedef union tagMeepCcrRid 4810 { 4811 4812 struct 4813 { 4814 UINT32 revision_identification : 8 ; 4815 UINT32 Reserved_165 : 8 ; 4816 UINT32 sub_class : 8 ; 4817 UINT32 baseclass : 8 ; 4818 } Bits; 4819 4820 4821 UINT32 UInt32; 4822 4823 } PCIE_MEEP_CCR_RID_U; 4824 4825 4826 4827 4828 typedef union tagMeepPbar01BaseLower 4829 { 4830 4831 struct 4832 { 4833 UINT32 BAR01_Space_Inicator : 1 ; 4834 UINT32 BAR01_Type : 2 ; 4835 UINT32 BAR01_Prefetchable : 1 ; 4836 UINT32 Reserved_166 : 13 ; 4837 UINT32 base_address_register_01_lower : 15 ; 4838 } Bits; 4839 4840 4841 UINT32 UInt32; 4842 4843 } PCIE_MEEP_PBAR01_BASE_LOWER_U; 4844 4845 4846 4847 4848 typedef union tagMeepPbar23BaseLower 4849 { 4850 4851 struct 4852 { 4853 UINT32 BAR23_Space_Inicator : 1 ; 4854 UINT32 BAR23_Type : 2 ; 4855 UINT32 BAR23_Prefetchable : 1 ; 4856 UINT32 Reserved_168 : 8 ; 4857 UINT32 Base_Address_Register_23_Lower : 20 ; 4858 } Bits; 4859 4860 4861 UINT32 UInt32; 4862 4863 } PCIE_MEEP_PBAR23_BASE_LOWER_U; 4864 4865 4866 4867 4868 typedef union tagMeepPbar45BaseLower 4869 { 4870 4871 struct 4872 { 4873 UINT32 BAR45_Space_Inicator : 1 ; 4874 UINT32 BAR45_Type : 2 ; 4875 UINT32 BAR45_Prefetchable : 1 ; 4876 UINT32 Reserved_169 : 8 ; 4877 UINT32 Base_Address_Register_45_Lower : 20 ; 4878 } Bits; 4879 4880 4881 UINT32 UInt32; 4882 4883 } PCIE_MEEP_PBAR45_BASE_LOWER_U; 4884 4885 4886 4887 4888 typedef union tagMeepSubsystemid 4889 { 4890 4891 struct 4892 { 4893 UINT32 SubsystemID : 16 ; 4894 UINT32 SubsystemVendorID : 16 ; 4895 } Bits; 4896 4897 4898 UINT32 UInt32; 4899 4900 } PCIE_MEEP_SubSystemId_U; 4901 4902 4903 4904 4905 typedef union tagMeepCapptr 4906 { 4907 4908 struct 4909 { 4910 UINT32 CapPtr : 8 ; 4911 UINT32 Reserved_172 : 24 ; 4912 } Bits; 4913 4914 4915 UINT32 UInt32; 4916 4917 } PCIE_MEEP_CapPtr_U; 4918 4919 4920 4921 4922 typedef union tagMeepInterrupt 4923 { 4924 4925 struct 4926 { 4927 UINT32 Interrupt_Line : 8 ; 4928 UINT32 interrupt_pin : 8 ; 4929 UINT32 min_grant : 8 ; 4930 UINT32 Max_Latency : 8 ; 4931 } Bits; 4932 4933 4934 UINT32 UInt32; 4935 4936 } PCIE_MEEP_Interrupt_U; 4937 4938 4939 4940 4941 typedef union tagMeepMsiCapabilityRegister 4942 { 4943 4944 struct 4945 { 4946 UINT32 CapabilityID : 8 ; 4947 UINT32 Next_Capability_Pointer : 8 ; 4948 UINT32 MSI_Enabled : 1 ; 4949 UINT32 Multiple_Message_Capable : 3 ; 4950 UINT32 Multiple_Message_Enabled : 3 ; 4951 UINT32 MSI_64_EN : 1 ; 4952 UINT32 PVM_EN : 1 ; 4953 UINT32 Message_Control_Register : 7 ; 4954 } Bits; 4955 4956 4957 UINT32 UInt32; 4958 4959 } PCIE_MEEP_MSI_Capability_Register_U; 4960 4961 4962 4963 4964 typedef union tagMeepMsiLower32Bitaddress 4965 { 4966 4967 struct 4968 { 4969 UINT32 Reserved_175 : 2 ; 4970 UINT32 Lower32_bitAddress : 30 ; 4971 } Bits; 4972 4973 4974 UINT32 UInt32; 4975 4976 } PCIE_MEEP_MSI_Lower32_bitAddress_U; 4977 4978 4979 4980 4981 typedef union tagMeepMsiData 4982 { 4983 4984 struct 4985 { 4986 UINT32 MSI_Data : 16 ; 4987 UINT32 Reserved_176 : 16 ; 4988 } Bits; 4989 4990 4991 UINT32 UInt32; 4992 4993 } PCIE_MEEP_MSI_Data_U; 4994 4995 4996 4997 4998 typedef union tagMeepMsiMask 4999 { 5000 5001 struct 5002 { 5003 UINT32 MsiMask : 1 ; 5004 UINT32 Reserved_177 : 31 ; 5005 } Bits; 5006 5007 5008 UINT32 UInt32; 5009 5010 } PCIE_MEEP_MSI_MASK_U; 5011 5012 5013 5014 5015 typedef union tagMeepMsiPending 5016 { 5017 5018 struct 5019 { 5020 UINT32 MsiPending : 1 ; 5021 UINT32 Reserved_178 : 31 ; 5022 } Bits; 5023 5024 5025 UINT32 UInt32; 5026 5027 } PCIE_MEEP_MSI_Pending_U; 5028 5029 5030 5031 5032 typedef union tagMeepPcieCapabilityRegister 5033 { 5034 5035 struct 5036 { 5037 UINT32 Capability_ID : 8 ; 5038 UINT32 Next_Capability_Pointer : 8 ; 5039 UINT32 PCIE_Capability_Version : 4 ; 5040 UINT32 Device_Port_Type : 4 ; 5041 UINT32 Slot_Implemented : 1 ; 5042 UINT32 Interrupt_Message_Number : 5 ; 5043 UINT32 Reserved_179 : 2 ; 5044 } Bits; 5045 5046 5047 UINT32 UInt32; 5048 5049 } PCIE_MEEP_PCIE_Capability_Register_U; 5050 5051 5052 5053 5054 typedef union tagMeepDeviceCapabilitiesRegister 5055 { 5056 5057 struct 5058 { 5059 UINT32 Max_Payload_Size_Supported : 3 ; 5060 UINT32 Phantom_Function_Supported : 2 ; 5061 UINT32 Extended_TagField_Supported : 1 ; 5062 UINT32 Endpoint_L0sAcceptable_Latency : 3 ; 5063 UINT32 Endpoint_L1Acceptable_Latency : 3 ; 5064 UINT32 Undefined : 3 ; 5065 UINT32 Reserved_182 : 3 ; 5066 UINT32 Captured_Slot_Power_Limit_Value : 8 ; 5067 UINT32 Captured_Slot_Power_Limit_Scale : 2 ; 5068 UINT32 Function_Level_Reset : 1 ; 5069 UINT32 Reserved_181 : 3 ; 5070 } Bits; 5071 5072 5073 UINT32 UInt32; 5074 5075 } PCIE_MEEP_Device_Capabilities_Register_U; 5076 5077 5078 5079 5080 typedef union tagMeepDeviceStatusRegister 5081 { 5082 5083 struct 5084 { 5085 UINT32 Correctable_Error_Reporting_Enable : 1 ; 5086 UINT32 Non_Fatal_Error_Reporting_Enable : 1 ; 5087 UINT32 Fatal_Error_Reporting_Enable : 1 ; 5088 UINT32 UREnable : 1 ; 5089 UINT32 Enable_Relaxed_Ordering : 1 ; 5090 UINT32 Max_Payload_Size : 3 ; 5091 UINT32 Extended_TagFieldEnable : 1 ; 5092 UINT32 Phantom_Function_Enable : 1 ; 5093 UINT32 AUXPowerPMEnable : 1 ; 5094 UINT32 EnableNoSnoop : 1 ; 5095 UINT32 Max_Read_Request_Size : 3 ; 5096 UINT32 Reserved_184 : 1 ; 5097 UINT32 CorrectableErrorDetected : 1 ; 5098 UINT32 Non_FatalErrordetected : 1 ; 5099 UINT32 FatalErrorDetected : 1 ; 5100 UINT32 UnsupportedRequestDetected : 1 ; 5101 UINT32 AuxPowerDetected : 1 ; 5102 UINT32 TransactionPending : 1 ; 5103 UINT32 Reserved_183 : 10 ; 5104 } Bits; 5105 5106 5107 UINT32 UInt32; 5108 5109 } PCIE_MEEP_Device_Status_Register_U; 5110 5111 5112 5113 5114 typedef union tagMeepLinkCapability 5115 { 5116 5117 struct 5118 { 5119 UINT32 Max_Link_Speed : 4 ; 5120 UINT32 Max_Link_Width : 6 ; 5121 UINT32 Active_State_Power_Management : 2 ; 5122 UINT32 L0s_ExitLatency : 3 ; 5123 UINT32 L1_Exit_Latency : 3 ; 5124 UINT32 Clock_Power_Management : 1 ; 5125 UINT32 Surprise_Down_Error_Report_Cap : 1 ; 5126 UINT32 Data_Link_Layer_Active_Report_Cap : 1 ; 5127 UINT32 Link_Bandwidth_Noti_Cap : 1 ; 5128 UINT32 ASPM_Option_Compliance : 1 ; 5129 UINT32 Reserved_185 : 1 ; 5130 UINT32 Port_Number : 8 ; 5131 } Bits; 5132 5133 5134 UINT32 UInt32; 5135 5136 } PCIE_MEEP_Link_Capability_U; 5137 5138 5139 5140 5141 typedef union tagMeepLinkControlStatus 5142 { 5143 5144 struct 5145 { 5146 UINT32 active_state_power_management : 2 ; 5147 UINT32 Reserved_188 : 1 ; 5148 UINT32 rcb : 1 ; 5149 UINT32 link_disable : 1 ; 5150 UINT32 retrain_link : 1 ; 5151 UINT32 common_clock_config : 1 ; 5152 UINT32 extended_sync : 1 ; 5153 UINT32 enable_clock_pwr_management : 1 ; 5154 UINT32 hw_auto_width_disable : 1 ; 5155 UINT32 link_bandwidth_management_int_en : 1 ; 5156 UINT32 link_auto_bandwidth_int_en : 1 ; 5157 UINT32 Reserved_187 : 4 ; 5158 UINT32 current_link_speed : 4 ; 5159 UINT32 negotiated_link_width : 6 ; 5160 UINT32 Reserved_186 : 1 ; 5161 UINT32 link_training : 1 ; 5162 UINT32 slot_clock_configration : 1 ; 5163 UINT32 data_link_layer_active : 1 ; 5164 UINT32 link_bandwidth_management_status : 1 ; 5165 UINT32 link_auto_bandwidth_status : 1 ; 5166 } Bits; 5167 5168 5169 UINT32 UInt32; 5170 5171 } PCIE_MEEP_Link_Control_Status_U; 5172 5173 5174 5175 5176 typedef union tagMeepAerCapHeader 5177 { 5178 5179 struct 5180 { 5181 UINT32 PCIE_Extended_Capability_ID : 16 ; 5182 UINT32 Capability_Version : 4 ; 5183 UINT32 Next_Capability_Offset : 12 ; 5184 } Bits; 5185 5186 5187 UINT32 UInt32; 5188 5189 } PCIE_MEEP_AER_Cap_header_U; 5190 5191 5192 5193 5194 typedef union tagMeepUcErrorStatus 5195 { 5196 5197 struct 5198 { 5199 UINT32 Reserved_193 : 1 ; 5200 UINT32 Reserved_192 : 3 ; 5201 UINT32 DataLinkProtocolErrorStatus : 1 ; 5202 UINT32 SurpriseDownErrorStatus : 1 ; 5203 UINT32 Reserved_191 : 6 ; 5204 UINT32 PoisonedTLPStatus : 1 ; 5205 UINT32 FlowControlProtocolErrorStatus : 1 ; 5206 UINT32 CompletionTimeoutStatus : 1 ; 5207 UINT32 CompleterAbortStatus : 1 ; 5208 UINT32 UnexpectedCompletionStatus : 1 ; 5209 UINT32 ReceiverOverflowStatus : 1 ; 5210 UINT32 MalformedTLPStatus : 1 ; 5211 UINT32 ECRCErrorStatus : 1 ; 5212 UINT32 UnsupportedRequestErrorStatus : 1 ; 5213 UINT32 Reserved_190 : 11 ; 5214 } Bits; 5215 5216 5217 UINT32 UInt32; 5218 5219 } PCIE_MEEP_UC_Error_Status_U; 5220 5221 5222 5223 5224 typedef union tagMeepUcErrorMask 5225 { 5226 5227 struct 5228 { 5229 UINT32 Reserved_197 : 1 ; 5230 UINT32 Reserved_196 : 3 ; 5231 UINT32 DataLinkProtocolErrorMask : 1 ; 5232 UINT32 SurpriseDownErrorMask : 1 ; 5233 UINT32 Reserved_195 : 6 ; 5234 UINT32 PoisonedTLPMask : 1 ; 5235 UINT32 FlowControlProtocolErrorMask : 1 ; 5236 UINT32 CompletionTimeoutMask : 1 ; 5237 UINT32 CompleterAbortMask : 1 ; 5238 UINT32 UnexpectedCompletionMask : 1 ; 5239 UINT32 ReceiverOverflowMask : 1 ; 5240 UINT32 MalformedTLPMask : 1 ; 5241 UINT32 ECRCErrorMask : 1 ; 5242 UINT32 UnsupportedRequestErrorMask : 1 ; 5243 UINT32 Reserved_194 : 11 ; 5244 } Bits; 5245 5246 5247 UINT32 UInt32; 5248 5249 } PCIE_MEEP_UC_Error_Mask_U; 5250 5251 5252 5253 5254 typedef union tagMeepUcErrorSeverity 5255 { 5256 5257 struct 5258 { 5259 UINT32 Reserved_201 : 1 ; 5260 UINT32 Reserved_200 : 3 ; 5261 UINT32 DataLinkProtocolErrorSeverity : 1 ; 5262 UINT32 SurpriseDownErrorSeverity : 1 ; 5263 UINT32 Reserved_199 : 6 ; 5264 UINT32 PoisonedTLPSeverity : 1 ; 5265 UINT32 FlowControlProtocolErrorSeverity : 1 ; 5266 UINT32 CompletionTimeoutSeverity : 1 ; 5267 UINT32 CompleterAbortSeverity : 1 ; 5268 UINT32 UnexpectedCompletionSeverity : 1 ; 5269 UINT32 ReceiverOverflowSeverity : 1 ; 5270 UINT32 MalformedTLPSeverity : 1 ; 5271 UINT32 ECRCErrorSeverity : 1 ; 5272 UINT32 UnsupportedRequestErrorSeverity : 1 ; 5273 UINT32 Reserved_198 : 11 ; 5274 } Bits; 5275 5276 5277 UINT32 UInt32; 5278 5279 } PCIE_MEEP_UC_Error_Severity_U; 5280 5281 5282 5283 5284 typedef union tagMeepCErrorStatus 5285 { 5286 5287 struct 5288 { 5289 UINT32 Receiver_Error_Status : 1 ; 5290 UINT32 Reserved_204 : 5 ; 5291 UINT32 Bad_TLP_Status : 1 ; 5292 UINT32 Bad_DLLP_Status : 1 ; 5293 UINT32 REPLAY_NUM_Rollover_Status : 1 ; 5294 UINT32 Reserved_203 : 3 ; 5295 UINT32 Replay_Timer_Timeout_Status : 1 ; 5296 UINT32 Advisory_Non_Fatal_Error_Status : 1 ; 5297 UINT32 Reserved_202 : 18 ; 5298 } Bits; 5299 5300 5301 UINT32 UInt32; 5302 5303 } PCIE_MEEP_C_Error_Status_U; 5304 5305 5306 5307 5308 typedef union tagMeepCErrorMask 5309 { 5310 5311 struct 5312 { 5313 UINT32 Receiver_Error_Mask : 1 ; 5314 UINT32 Reserved_207 : 5 ; 5315 UINT32 Bad_TLP_Mask : 1 ; 5316 UINT32 Bad_DLLP_Mask : 1 ; 5317 UINT32 REPLAY_NUMRollover_Mask : 1 ; 5318 UINT32 Reserved_206 : 3 ; 5319 UINT32 Replay_Timer_Timeout_Mask : 1 ; 5320 UINT32 Advisory_Non_Fatal_Error_Mask : 1 ; 5321 UINT32 Reserved_205 : 18 ; 5322 } Bits; 5323 5324 5325 UINT32 UInt32; 5326 5327 } PCIE_MEEP_C_Error_Mask_U; 5328 5329 5330 5331 5332 typedef union tagMeepAdvancedErrorCapabilitiesAndControl 5333 { 5334 5335 struct 5336 { 5337 UINT32 First_Error_Pointer : 5 ; 5338 UINT32 ECRC_Generation_Capability : 1 ; 5339 UINT32 ECRC_Generation_Enable : 1 ; 5340 UINT32 ECRC_Check_Capable : 1 ; 5341 UINT32 ECRC_Check_Enable : 1 ; 5342 UINT32 Reserved_209 : 2 ; 5343 UINT32 TLP_Prefix_Log_Present : 1 ; 5344 UINT32 Reserved_208 : 20 ; 5345 } Bits; 5346 5347 5348 UINT32 UInt32; 5349 5350 } PCIE_MEEP_Advanced_Error_Capabilities_and_Control_U; 5351 5352 5353 5354 5355 typedef union tagMeepNtbIepBar01Ctrl 5356 { 5357 5358 struct 5359 { 5360 UINT32 bar01_type : 5 ; 5361 UINT32 bar01_tc : 3 ; 5362 UINT32 bar01_td : 1 ; 5363 UINT32 bar01_attr : 2 ; 5364 UINT32 Reserved_213 : 5 ; 5365 UINT32 bar01_at : 2 ; 5366 UINT32 bar01_match_en : 1 ; 5367 UINT32 Reserved_212 : 13 ; 5368 } Bits; 5369 5370 5371 UINT32 UInt32; 5372 5373 } PCIE_MEEP_NTB_IEP_BAR01_CTRL_U; 5374 5375 5376 5377 5378 typedef union tagMeepNtbIepBar23Ctrl 5379 { 5380 5381 struct 5382 { 5383 UINT32 bar23_type : 5 ; 5384 UINT32 bar23_tc : 3 ; 5385 UINT32 bar23_td : 1 ; 5386 UINT32 bar23_attr : 2 ; 5387 UINT32 Reserved_215 : 5 ; 5388 UINT32 bar23_at : 2 ; 5389 UINT32 bar23_match_en : 1 ; 5390 UINT32 Reserved_214 : 13 ; 5391 } Bits; 5392 5393 5394 UINT32 UInt32; 5395 5396 } PCIE_MEEP_NTB_IEP_BAR23_CTRL_U; 5397 5398 5399 5400 5401 typedef union tagMeepNtbIepBar45Ctrl 5402 { 5403 5404 struct 5405 { 5406 UINT32 bar45_type : 5 ; 5407 UINT32 bar45_tc : 3 ; 5408 UINT32 bar45_td : 1 ; 5409 UINT32 bar45_attr : 2 ; 5410 UINT32 Reserved_217 : 5 ; 5411 UINT32 bar45_at : 2 ; 5412 UINT32 bar45_match_en : 1 ; 5413 UINT32 Reserved_216 : 13 ; 5414 } Bits; 5415 5416 5417 UINT32 UInt32; 5418 5419 } PCIE_MEEP_NTB_IEP_BAR45_CTRL_U; 5420 5421 5422 5423 5424 typedef union tagMeepMsiCtrlIntEn 5425 { 5426 5427 struct 5428 { 5429 UINT32 msi_int_en : 1 ; 5430 UINT32 Reserved_218 : 31 ; 5431 } Bits; 5432 5433 5434 UINT32 UInt32; 5435 5436 } PCIE_MEEP_MSI_CTRL_INT_EN_U; 5437 5438 5439 5440 5441 typedef union tagMeepMsiCtrlInt0Mask 5442 { 5443 5444 struct 5445 { 5446 UINT32 msi_int_mask : 1 ; 5447 UINT32 Reserved_219 : 31 ; 5448 } Bits; 5449 5450 5451 UINT32 UInt32; 5452 5453 } PCIE_MEEP_MSI_CTRL_INT0_MASK_U; 5454 5455 5456 5457 5458 typedef union tagMeepMsiCtrlIntStatus 5459 { 5460 5461 struct 5462 { 5463 UINT32 msi_int : 1 ; 5464 UINT32 Reserved_220 : 31 ; 5465 } Bits; 5466 5467 5468 UINT32 UInt32; 5469 5470 } PCIE_MEEP_MSI_CTRL_INT_STATUS_U; 5471 5472 5473 5474 5475 typedef union tagMeepDbiRoWrEn 5476 { 5477 5478 struct 5479 { 5480 UINT32 dbi_ro_wr_en : 1 ; 5481 UINT32 Reserved_221 : 31 ; 5482 } Bits; 5483 5484 5485 UINT32 UInt32; 5486 5487 } PCIE_MEEP_DBI_RO_WR_EN_U; 5488 5489 5490 5491 5492 typedef union tagAxiErrResponse 5493 { 5494 5495 struct 5496 { 5497 UINT32 err_resp_mode : 4 ; 5498 UINT32 Reserved_222 : 28 ; 5499 } Bits; 5500 5501 5502 UINT32 UInt32; 5503 5504 } PCIE_MEEP_AXI_ERR_RESPONSE_U; 5505 5506 5507 5508 5509 5510 5511 5512 #define PCIE_MIEP_PBAR23XLAT_LOWER_REG (0x0) 5513 #define PCIE_MIEP_PBAR23XLAT_UPPER_REG (0x4) 5514 #define PCIE_MIEP_PBAR45XLAT_LOWER_REG (0x8) 5515 #define PCIE_MIEP_PBAR45XLAT_UPPER_REG (0xC) 5516 #define PCIE_MIEP_PBAR23LMT_LOWER_REG (0x10) 5517 #define PCIE_MIEP_PBAR23LMT_UPPER_REG (0x14) 5518 #define PCIE_MIEP_PBAR45LMT_LOWER_REG (0x18) 5519 #define PCIE_MIEP_PBAR45LMT_UPPER_REG (0x1C) 5520 #define PCIE_MIEP_PDOORBELL_REG (0x20) 5521 #define PCIE_MIEP_PDOORBELL_MASK_REG (0x24) 5522 #define PCIE_MIEP_B2B_BAR01XLAT_LOWER_REG (0x28) 5523 #define PCIE_MIEP_B2B_BAR01XLAT_UPPER_REG (0x2C) 5524 #define PCIE_MIEP_B2BDOORBELL_REG (0x30) 5525 #define PCIE_MIEP_SPAD0_REG (0x38) 5526 #define PCIE_MIEP_SPAD1_REG (0x3C) 5527 #define PCIE_MIEP_SPAD2_REG (0x40) 5528 #define PCIE_MIEP_SPAD3_REG (0x44) 5529 #define PCIE_MIEP_SPAD4_REG (0x48) 5530 #define PCIE_MIEP_SPAD5_REG (0x4C) 5531 #define PCIE_MIEP_SPAD6_REG (0x50) 5532 #define PCIE_MIEP_SPAD7_REG (0x54) 5533 #define PCIE_MIEP_SPAD8_REG (0x58) 5534 #define PCIE_MIEP_SPAD9_REG (0x5C) 5535 #define PCIE_MIEP_SPAD10_REG (0x60) 5536 #define PCIE_MIEP_SPAD11_REG (0x64) 5537 #define PCIE_MIEP_SPAD12_REG (0x68) 5538 #define PCIE_MIEP_SPAD13_REG (0x6C) 5539 #define PCIE_MIEP_SPAD14_REG (0x70) 5540 #define PCIE_MIEP_SPAD15_REG (0x74) 5541 #define PCIE_MIEP_SPAD16_REG (0x78) 5542 #define PCIE_MIEP_SPAD17_REG (0x7C) 5543 #define PCIE_MIEP_SPAD18_REG (0x80) 5544 #define PCIE_MIEP_SPAD19_REG (0x84) 5545 #define PCIE_MIEP_SPAD20_REG (0x88) 5546 #define PCIE_MIEP_SPAD21_REG (0x8C) 5547 #define PCIE_MIEP_SPAD22_REG (0x90) 5548 #define PCIE_MIEP_SPAD23_REG (0x94) 5549 #define PCIE_MIEP_SPAD24_REG (0x98) 5550 #define PCIE_MIEP_SPAD25_REG (0x9C) 5551 #define PCIE_MIEP_SPAD26_REG (0xA0) 5552 #define PCIE_MIEP_SPAD27_REG (0xA4) 5553 #define PCIE_MIEP_SPAD28_REG (0xA8) 5554 #define PCIE_MIEP_SPAD29_REG (0xAC) 5555 #define PCIE_MIEP_SPAD30_REG (0xB0) 5556 #define PCIE_MIEP_SPAD31_REG (0xB4) 5557 #define PCIE_MIEP_B2BSPAD0_REG (0xB8) 5558 #define PCIE_MIEP_B2BSPAD1_REG (0xBC) 5559 #define PCIE_MIEP_B2BSPAD2_REG (0xC0) 5560 #define PCIE_MIEP_B2BSPAD3_REG (0xC4) 5561 #define PCIE_MIEP_B2BSPAD4_REG (0xC8) 5562 #define PCIE_MIEP_B2BSPAD5_REG (0xCC) 5563 #define PCIE_MIEP_B2BSPAD6_REG (0xD0) 5564 #define PCIE_MIEP_B2BSPAD7_REG (0xD4) 5565 #define PCIE_MIEP_B2BSPAD8_REG (0xD8) 5566 #define PCIE_MIEP_B2BSPAD9_REG (0xDC) 5567 #define PCIE_MIEP_B2BSPAD10_REG (0xE0) 5568 #define PCIE_MIEP_B2BSPAD11_REG (0xE4) 5569 #define PCIE_MIEP_B2BSPAD12_REG (0xE8) 5570 #define PCIE_MIEP_B2BSPAD13_REG (0xEC) 5571 #define PCIE_MIEP_B2BSPAD14_REG (0xF0) 5572 #define PCIE_MIEP_B2BSPAD15_REG (0xF4) 5573 #define PCIE_MIEP_B2BSPAD16_REG (0xF8) 5574 #define PCIE_MIEP_B2BSPAD17_REG (0xFC) 5575 #define PCIE_MIEP_B2BSPAD18_REG (0x100) 5576 #define PCIE_MIEP_B2BSPAD19_REG (0x104) 5577 #define PCIE_MIEP_B2BSPAD20_REG (0x108) 5578 #define PCIE_MIEP_B2BSPAD21_REG (0x10C) 5579 #define PCIE_MIEP_B2BSPAD22_REG (0x110) 5580 #define PCIE_MIEP_B2BSPAD23_REG (0x114) 5581 #define PCIE_MIEP_B2BSPAD24_REG (0x118) 5582 #define PCIE_MIEP_B2BSPAD25_REG (0x11C) 5583 #define PCIE_MIEP_B2BSPAD26_REG (0x120) 5584 #define PCIE_MIEP_B2BSPAD27_REG (0x124) 5585 #define PCIE_MIEP_B2BSPAD28_REG (0x128) 5586 #define PCIE_MIEP_B2BSPAD29_REG (0x12C) 5587 #define PCIE_MIEP_B2BSPAD30_REG (0x130) 5588 #define PCIE_MIEP_B2BSPAD31_REG (0x134) 5589 #define PCIE_MIEP_PPD_REG (0x138) 5590 #define PCIE_MIEP_P_DEVICE_VENDOR_ID_REG (0x1000) 5591 #define PCIE_MIEP_P_PCISTS_PCICMD_REG (0x1004) 5592 #define PCIE_MIEP_P_CCR_RID_REG (0x1008) 5593 #define PCIE_MIEP_P_BIST_TYPE_REG (0x100C) 5594 #define PCIE_MIEP_PBAR01_BASE_LOWER_REG (0x1010) 5595 #define PCIE_MIEP_PBAR01_BASE_UPPER_REG (0x1014) 5596 #define PCIE_MIEP_PBAR23_BASE_LOWER_REG (0x1018) 5597 #define PCIE_MIEP_PBAR23_BASE_UPPER_REG (0x101C) 5598 #define PCIE_MIEP_PBAR45_BASE_LOWER_REG (0x1020) 5599 #define PCIE_MIEP_PBAR45_BASE_UPPER_REG (0x1024) 5600 #define PCIE_MIEP_P_SUBSYSTEMID_REG (0x102C) 5601 #define PCIE_MIEP_P_INTERRUPT_REG (0x103C) 5602 #define PCIE_MIEP_P_MSI_LOWER32_BITADDRESS_REG (0x1054) 5603 #define PCIE_MIEP_P_MSI_UPPER32_BIT_ADDRESS_REG (0x1058) 5604 #define PCIE_MIEP_P_LINK_CAPABILITY_REG (0x107C) 5605 #define PCIE_MIEP_P_AER_CAP_HEADER_REG (0x1100) 5606 #define PCIE_MIEP_P_HEADER_LOG_REGISTERS_1_REG (0x111C) 5607 #define PCIE_MIEP_P_HEADER_LOG_REGISTERS_2_REG (0x1120) 5608 #define PCIE_MIEP_P_HEADER_LOG_REGISTERS_3_REG (0x1124) 5609 #define PCIE_MIEP_P_HEADER_LOG_REGISTERS_4_REG (0x1128) 5610 #define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_1_REG (0x1130) 5611 #define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_2_REG (0x1134) 5612 #define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_3_REG (0x1138) 5613 #define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_4_REG (0x113C) 5614 #define PCIE_MIEP_P_NTB_IEP_CONFIG_SPACE_LOWER_REG (0x1700) 5615 #define PCIE_MIEP_P_NTB_IEP_CONFIG_SPACE_UPPER_REG (0x1704) 5616 #define PCIE_MIEP_P_MSI_CTRL_ADDRESS_LOWER_REG (0x1714) 5617 #define PCIE_MIEP_P_MSI_CTRL_ADDRESS_UPPER_REG (0x1718) 5618 #define PCIE_MIEP_SBAR23XLAT_LOWER_REG (0x8000) 5619 #define PCIE_MIEP_SBAR23XLAT_UPPER_REG (0x8004) 5620 #define PCIE_MIEP_SBAR45XLAT_LOWER_REG (0x8008) 5621 #define PCIE_MIEP_SBAR45XLAT_UPPER_REG (0x800C) 5622 #define PCIE_MIEP_SBAR23LMT_LOWER_REG (0x8010) 5623 #define PCIE_MIEP_SBAR23LMT_UPPER_REG (0x8014) 5624 #define PCIE_MIEP_SBAR45LMT_LOWER_REG (0x8018) 5625 #define PCIE_MIEP_SBAR45LMT_UPPER_REG (0x801C) 5626 #define PCIE_MIEP_SDOORBELL_REG (0x8020) 5627 #define PCIE_MIEP_SDOORBELL_MASK_REG (0x8024) 5628 #define PCIE_MIEP_CBDF_SBDF_REG (0x8028) 5629 #define PCIE_MIEP_PCI_CFG_HDR0_REG (0x9000) 5630 #define PCIE_MIEP_PCI_CFG_HDR1_REG (0x9004) 5631 #define PCIE_MIEP_PCI_CFG_HDR9_REG (0x9024) 5632 #define PCIE_MIEP_PCI_CFG_HDR10_REG (0x9028) 5633 #define PCIE_MIEP_PCI_CFG_HDR11_REG (0x902C) 5634 #define PCIE_MIEP_PCI_CFG_HDR12_REG (0x9030) 5635 #define PCIE_MIEP_PCI_CFG_HDR13_REG (0x9034) 5636 #define PCIE_MIEP_PCI_CFG_HDR14_REG (0x9038) 5637 #define PCIE_MIEP_PCI_CFG_HDR15_REG (0x903C) 5638 #define PCIE_MIEP_PCI_PM_CAP0_REG (0x9040) 5639 #define PCIE_MIEP_PCI_PM_CAP1_REG (0x9044) 5640 #define PCIE_MIEP_PCI_MSI_CAP0_REG (0x9050) 5641 #define PCIE_MIEP_PCI_MSI_CAP1_REG (0x9054) 5642 #define PCIE_MIEP_PCI_MSI_CAP2_REG (0x9058) 5643 #define PCIE_MIEP_PCI_MSI_CAP3_REG (0x905C) 5644 #define PCIE_MIEP_PCIE_CAP0_REG (0x9070) 5645 #define PCIE_MIEP_PCIE_CAP1_REG (0x9074) 5646 #define PCIE_MIEP_PCIE_CAP2_REG (0x9078) 5647 #define PCIE_MIEP_PCIE_CAP3_REG (0x907C) 5648 #define PCIE_MIEP_PCIE_CAP4_REG (0x9080) 5649 #define PCIE_MIEP_PCIE_CAP5_REG (0x9084) 5650 #define PCIE_MIEP_PCIE_CAP6_REG (0x9088) 5651 #define PCIE_MIEP_PCIE_CAP7_REG (0x908C) 5652 #define PCIE_MIEP_PCIE_CAP8_REG (0x9090) 5653 #define PCIE_MIEP_PCIE_CAP9_REG (0x9094) 5654 #define PCIE_MIEP_PCIE_CAP10_REG (0x9098) 5655 #define PCIE_MIEP_PCIE_CAP11_REG (0x909C) 5656 #define PCIE_MIEP_PCIE_CAP12_REG (0x90A0) 5657 #define PCIE_MIEP_SLOT_CAP_REG (0x90C0) 5658 #define PCIE_MIEP_AER_CAP0_REG (0x9100) 5659 #define PCIE_MIEP_AER_CAP1_REG (0x9104) 5660 #define PCIE_MIEP_AER_CAP2_REG (0x9108) 5661 #define PCIE_MIEP_AER_CAP3_REG (0x910C) 5662 #define PCIE_MIEP_AER_CAP4_REG (0x9110) 5663 #define PCIE_MIEP_AER_CAP5_REG (0x9114) 5664 #define PCIE_MIEP_AER_CAP6_REG (0x9118) 5665 #define PCIE_MIEP_AER_CAP7_REG (0x911C) 5666 #define PCIE_MIEP_AER_CAP8_REG (0x9120) 5667 #define PCIE_MIEP_AER_CAP9_REG (0x9124) 5668 #define PCIE_MIEP_AER_CAP10_REG (0x9128) 5669 #define PCIE_MIEP_AER_CAP11_REG (0x912C) 5670 #define PCIE_MIEP_AER_CAP12_REG (0x9130) 5671 #define PCIE_MIEP_AER_CAP13_REG (0x9134) 5672 #define PCIE_MIEP_VC_CAP0_REG (0x9140) 5673 #define PCIE_MIEP_VC_CAP1_REG (0x9144) 5674 #define PCIE_MIEP_VC_CAP2_REG (0x9148) 5675 #define PCIE_MIEP_VC_CAP3_REG (0x914C) 5676 #define PCIE_MIEP_VC_CAP4_REG (0x9150) 5677 #define PCIE_MIEP_VC_CAP5_REG (0x9154) 5678 #define PCIE_MIEP_VC_CAP6_REG (0x9158) 5679 #define PCIE_MIEP_VC_CAP7_REG (0x915C) 5680 #define PCIE_MIEP_VC_CAP8_REG (0x9160) 5681 #define PCIE_MIEP_VC_CAP9_REG (0x9164) 5682 #define PCIE_MIEP_PORT_LOGIC0_REG (0x9700) 5683 #define PCIE_MIEP_PORT_LOGIC1_REG (0x9704) 5684 #define PCIE_MIEP_PORT_LOGIC2_REG (0x9708) 5685 #define PCIE_MIEP_PORT_LOGIC3_REG (0x970C) 5686 #define PCIE_MIEP_PORT_LOGIC4_REG (0x9710) 5687 #define PCIE_MIEP_PORT_LOGIC5_REG (0x9714) 5688 #define PCIE_MIEP_PORT_LOGIC6_REG (0x9718) 5689 #define PCIE_MIEP_PORT_LOGIC7_REG (0x971C) 5690 #define PCIE_MIEP_PORT_LOGIC8_REG (0x9720) 5691 #define PCIE_MIEP_PORT_LOGIC9_REG (0x9724) 5692 #define PCIE_MIEP_PORT_LOGIC10_REG (0x9728) 5693 #define PCIE_MIEP_PORT_LOGIC11_REG (0x972C) 5694 #define PCIE_MIEP_PORT_LOGIC12_REG (0x9730) 5695 #define PCIE_MIEP_PORT_LOGIC13_REG (0x9734) 5696 #define PCIE_MIEP_PORT_LOGIC14_REG (0x9738) 5697 #define PCIE_MIEP_PORT_LOGIC15_REG (0x973C) 5698 #define PCIE_MIEP_PORT_LOGIC16_REG (0x9748) 5699 #define PCIE_MIEP_PORT_LOGIC17_REG (0x974C) 5700 #define PCIE_MIEP_PORT_LOGIC18_REG (0x9750) 5701 #define PCIE_MIEP_PORT_LOGIC19_REG (0x97A8) 5702 #define PCIE_MIEP_PORT_LOGIC20_REG (0x97AC) 5703 #define PCIE_MIEP_PORT_LOGIC21_REG (0x97B0) 5704 #define PCIE_MIEP_PORT_LOGIC22_REG (0x980C) 5705 #define PCIE_MIEP_PORTLOGIC23_REG (0x9810) 5706 #define PCIE_MIEP_PORTLOGIC24_REG (0x9814) 5707 #define PCIE_MIEP_PORTLOGIC25_REG (0x9818) 5708 #define PCIE_MIEP_PORTLOGIC26_REG (0x981C) 5709 #define PCIE_MIEP_PORTLOGIC27_REG (0x9820) 5710 #define PCIE_MIEP_PORTLOGIC28_REG (0x9824) 5711 #define PCIE_MIEP_PORTLOGIC29_REG (0x9828) 5712 #define PCIE_MIEP_PORTLOGIC30_REG (0x982C) 5713 #define PCIE_MIEP_PORTLOGIC31_REG (0x9830) 5714 #define PCIE_MIEP_PORTLOGIC32_REG (0x9834) 5715 #define PCIE_MIEP_PORTLOGIC33_REG (0x9838) 5716 #define PCIE_MIEP_PORTLOGIC34_REG (0x983C) 5717 #define PCIE_MIEP_PORTLOGIC35_REG (0x9840) 5718 #define PCIE_MIEP_PORTLOGIC36_REG (0x9844) 5719 #define PCIE_MIEP_PORTLOGIC37_REG (0x9848) 5720 #define PCIE_MIEP_PORTLOGIC38_REG (0x984C) 5721 #define PCIE_MIEP_PORTLOGIC39_REG (0x9850) 5722 #define PCIE_MIEP_PORTLOGIC40_REG (0x9854) 5723 #define PCIE_MIEP_PORTLOGIC41_REG (0x9858) 5724 #define PCIE_MIEP_PORTLOGIC42_REG (0x985C) 5725 #define PCIE_MIEP_PORTLOGIC43_REG (0x9860) 5726 #define PCIE_MIEP_PORTLOGIC44_REG (0x9864) 5727 #define PCIE_MIEP_PORTLOGIC45_REG (0x9868) 5728 #define PCIE_MIEP_PORTLOGIC46_REG (0x986C) 5729 #define PCIE_MIEP_PORTLOGIC47_REG (0x9870) 5730 #define PCIE_MIEP_PORTLOGIC48_REG (0x9874) 5731 #define PCIE_MIEP_PORTLOGIC49_REG (0x9878) 5732 #define PCIE_MIEP_PORTLOGIC50_REG (0x987C) 5733 #define PCIE_MIEP_PORTLOGIC51_REG (0x9880) 5734 #define PCIE_MIEP_PORTLOGIC52_REG (0x9884) 5735 #define PCIE_MIEP_PORTLOGIC53_REG (0x9888) 5736 #define PCIE_MIEP_PORTLOGIC54_REG (0x9900) 5737 #define PCIE_MIEP_PORTLOGIC55_REG (0x9904) 5738 #define PCIE_MIEP_PORTLOGIC56_REG (0x9908) 5739 #define PCIE_MIEP_PORTLOGIC57_REG (0x990C) 5740 #define PCIE_MIEP_PORTLOGIC58_REG (0x9910) 5741 #define PCIE_MIEP_PORTLOGIC59_REG (0x9914) 5742 #define PCIE_MIEP_PORTLOGIC60_REG (0x9918) 5743 #define PCIE_MIEP_PORTLOGIC61_REG (0x991C) 5744 #define PCIE_MIEP_PORTLOGIC62_REG (0x997C) 5745 #define PCIE_MIEP_PORTLOGIC63_REG (0x9980) 5746 #define PCIE_MIEP_PORTLOGIC64_REG (0x999C) 5747 #define PCIE_MIEP_PORTLOGIC65_REG (0x99A0) 5748 #define PCIE_MIEP_PORTLOGIC66_REG (0x99BC) 5749 #define PCIE_MIEP_PORTLOGIC67_REG (0x99C4) 5750 #define PCIE_MIEP_PORTLOGIC68_REG (0x99C8) 5751 #define PCIE_MIEP_PORTLOGIC69_REG (0x99CC) 5752 #define PCIE_MIEP_PORTLOGIC70_REG (0x99D0) 5753 #define PCIE_MIEP_PORTLOGIC71_REG (0x99D4) 5754 #define PCIE_MIEP_PORTLOGIC72_REG (0x99D8) 5755 #define PCIE_MIEP_PORTLOGIC73_REG (0x99DC) 5756 #define PCIE_MIEP_PORTLOGIC74_REG (0x99E0) 5757 #define PCIE_MIEP_PORTLOGIC75_REG (0x9A00) 5758 #define PCIE_MIEP_PORTLOGIC76_REG (0x9A10) 5759 #define PCIE_MIEP_PORTLOGIC77_REG (0x9A18) 5760 #define PCIE_MIEP_PORTLOGIC78_REG (0x9A1C) 5761 #define PCIE_MIEP_PORTLOGIC79_REG (0x9A24) 5762 #define PCIE_MIEP_PORTLOGIC80_REG (0x9A28) 5763 #define PCIE_MIEP_PORTLOGIC81_REG (0x9A34) 5764 #define PCIE_MIEP_PORTLOGIC82_REG (0x9A3C) 5765 #define PCIE_MIEP_PORTLOGIC83_REG (0x9A40) 5766 #define PCIE_MIEP_PORTLOGIC84_REG (0x9A44) 5767 #define PCIE_MIEP_PORTLOGIC85_REG (0x9A48) 5768 #define PCIE_MIEP_PORTLOGIC86_REG (0x9A6C) 5769 #define PCIE_MIEP_PORTLOGIC87_REG (0x9A70) 5770 #define PCIE_MIEP_PORTLOGIC88_REG (0x9A78) 5771 #define PCIE_MIEP_PORTLOGIC89_REG (0x9A7C) 5772 #define PCIE_MIEP_PORTLOGIC90_REG (0x9A80) 5773 #define PCIE_MIEP_PORTLOGIC91_REG (0x9A84) 5774 #define PCIE_MIEP_PORTLOGIC92_REG (0x9A88) 5775 #define PCIE_MIEP_PORTLOGIC93_REG (0x9A8C) 5776 #define PCIE_MIEP_PORTLOGIC94_REG (0x9A90) 5777 5778 5779 5780 5781 typedef union tagMiepPbar23xlatLower 5782 { 5783 5784 struct 5785 { 5786 UINT32 Reserved_0 : 12 ; 5787 UINT32 pbar23_xlat_lower : 20 ; 5788 } Bits; 5789 5790 5791 UINT32 UInt32; 5792 5793 } PCIE_MIEP_PBAR23XLAT_LOWER_U; 5794 5795 5796 5797 5798 typedef union tagMiepPbar45xlatLower 5799 { 5800 5801 struct 5802 { 5803 UINT32 Reserved_1 : 12 ; 5804 UINT32 pbar45_xlat_lower : 20 ; 5805 } Bits; 5806 5807 5808 UINT32 UInt32; 5809 5810 } PCIE_MIEP_PBAR45XLAT_LOWER_U; 5811 5812 5813 5814 5815 typedef union tagMiepPbar23lmtLower 5816 { 5817 5818 struct 5819 { 5820 UINT32 Reserved_2 : 12 ; 5821 UINT32 pbar23_limit_lower : 20 ; 5822 } Bits; 5823 5824 5825 UINT32 UInt32; 5826 5827 } PCIE_MIEP_PBAR23LMT_LOWER_U; 5828 5829 5830 5831 5832 typedef union tagMiepPbar45lmtLower 5833 { 5834 5835 struct 5836 { 5837 UINT32 Reserved_3 : 12 ; 5838 UINT32 pbar45_limit_lower : 20 ; 5839 } Bits; 5840 5841 5842 UINT32 UInt32; 5843 5844 } PCIE_MIEP_PBAR45LMT_LOWER_U; 5845 5846 5847 5848 5849 typedef union tagMiepB2bBar01xlatLower 5850 { 5851 5852 struct 5853 { 5854 UINT32 Reserved_4 : 17 ; 5855 UINT32 b2b_pbar01_xlat_lower : 15 ; 5856 } Bits; 5857 5858 5859 UINT32 UInt32; 5860 5861 } PCIE_MIEP_B2B_BAR01XLAT_LOWER_U; 5862 5863 5864 5865 5866 typedef union tagMiepPpd 5867 { 5868 5869 struct 5870 { 5871 UINT32 port_def : 1 ; 5872 UINT32 Reserved_6 : 31 ; 5873 } Bits; 5874 5875 5876 UINT32 UInt32; 5877 5878 } PCIE_MIEP_PPD_U; 5879 5880 5881 5882 5883 typedef union tagMiepPDeviceVendorId 5884 { 5885 5886 struct 5887 { 5888 UINT32 vendor_id : 16 ; 5889 UINT32 device_id : 16 ; 5890 } Bits; 5891 5892 5893 UINT32 UInt32; 5894 5895 } PCIE_MIEP_P_DEVICE_VENDOR_ID_U; 5896 5897 5898 5899 5900 typedef union tagMiepPPcistsPcicmd 5901 { 5902 5903 struct 5904 { 5905 UINT32 io_space_enable : 1 ; 5906 UINT32 memory_space_enable : 1 ; 5907 UINT32 bus_master_enable : 1 ; 5908 UINT32 specialcycleenable : 1 ; 5909 UINT32 memory_write_and_invalidate : 1 ; 5910 UINT32 vga_palette_snoop_enable : 1 ; 5911 UINT32 parity_error_response : 1 ; 5912 UINT32 idsel_stepping_waitcycle_control : 1 ; 5913 UINT32 serr_enable : 1 ; 5914 UINT32 fastback_to_backenable : 1 ; 5915 UINT32 interrupt_disable : 1 ; 5916 UINT32 Reserved_10 : 5 ; 5917 UINT32 Reserved_9 : 3 ; 5918 UINT32 intx_status : 1 ; 5919 UINT32 capabilitieslist : 1 ; 5920 UINT32 pcibus66mhzcapable : 1 ; 5921 UINT32 Reserved_8 : 1 ; 5922 UINT32 fastback_to_back : 1 ; 5923 UINT32 masterdataparityerror : 1 ; 5924 UINT32 devsel_timing : 2 ; 5925 UINT32 signaled_target_abort : 1 ; 5926 UINT32 received_target_abort : 1 ; 5927 UINT32 received_master_abort : 1 ; 5928 UINT32 signaled_system_error : 1 ; 5929 UINT32 detected_parity_error : 1 ; 5930 } Bits; 5931 5932 5933 UINT32 UInt32; 5934 5935 } PCIE_MIEP_P_PCISTS_PCICMD_U; 5936 5937 5938 5939 5940 typedef union tagMiepPCcrRid 5941 { 5942 5943 struct 5944 { 5945 UINT32 revision_id : 8 ; 5946 UINT32 Reserved_11 : 8 ; 5947 UINT32 cfg_sub_class : 8 ; 5948 UINT32 cfg_base_class : 8 ; 5949 } Bits; 5950 5951 5952 UINT32 UInt32; 5953 5954 } PCIE_MIEP_P_CCR_RID_U; 5955 5956 5957 5958 5959 typedef union tagMiepPBistType 5960 { 5961 5962 struct 5963 { 5964 UINT32 cache_line_size : 8 ; 5965 UINT32 primary_latency_timer : 8 ; 5966 UINT32 cfg_hdr_type : 8 ; 5967 UINT32 bist : 8 ; 5968 } Bits; 5969 5970 5971 UINT32 UInt32; 5972 5973 } PCIE_MIEP_P_BIST_TYPE_U; 5974 5975 5976 5977 5978 typedef union tagMiepPbar01BaseLower 5979 { 5980 5981 struct 5982 { 5983 UINT32 cfg_iep_bar0_io : 1 ; 5984 UINT32 cfg_iep_bar0_type : 2 ; 5985 UINT32 cfg_iep_bar0_pref : 1 ; 5986 UINT32 Reserved_12 : 13 ; 5987 UINT32 bar0_low : 15 ; 5988 } Bits; 5989 5990 5991 UINT32 UInt32; 5992 5993 } PCIE_MIEP_PBAR01_BASE_LOWER_U; 5994 5995 5996 5997 5998 typedef union tagMiepPbar23BaseLower 5999 { 6000 6001 struct 6002 { 6003 UINT32 cfg_iep_bar2_io : 1 ; 6004 UINT32 cfg_iep_bar2_type : 2 ; 6005 UINT32 cfg_iep_bar2_pref : 1 ; 6006 UINT32 Reserved_13 : 8 ; 6007 UINT32 bar2_low : 20 ; 6008 } Bits; 6009 6010 6011 UINT32 UInt32; 6012 6013 } PCIE_MIEP_PBAR23_BASE_LOWER_U; 6014 6015 6016 6017 6018 typedef union tagMiepPbar45BaseLower 6019 { 6020 6021 struct 6022 { 6023 UINT32 cfg_iep_bar4_io : 1 ; 6024 UINT32 cfg_iep_bar4_type : 2 ; 6025 UINT32 cfg_iep_bar4_pref : 1 ; 6026 UINT32 Reserved_14 : 8 ; 6027 UINT32 bar4_low : 20 ; 6028 } Bits; 6029 6030 6031 UINT32 UInt32; 6032 6033 } PCIE_MIEP_PBAR45_BASE_LOWER_U; 6034 6035 6036 6037 6038 typedef union tagMiepPSubsystemid 6039 { 6040 6041 struct 6042 { 6043 UINT32 subsystem_device_id : 16 ; 6044 UINT32 subsystem_vendor_id : 16 ; 6045 } Bits; 6046 6047 6048 UINT32 UInt32; 6049 6050 } PCIE_MIEP_P_SUBSYSTEMID_U; 6051 6052 6053 6054 6055 typedef union tagMiepPInterrupt 6056 { 6057 6058 struct 6059 { 6060 UINT32 int_line_reg : 8 ; 6061 UINT32 cfg_int_pin : 8 ; 6062 UINT32 min_gnt : 8 ; 6063 UINT32 max_lat : 8 ; 6064 } Bits; 6065 6066 6067 UINT32 UInt32; 6068 6069 } PCIE_MIEP_P_INTERRUPT_U; 6070 6071 6072 6073 6074 typedef union tagMiepPMsiLower32Bitaddress 6075 { 6076 6077 struct 6078 { 6079 UINT32 Reserved_17 : 2 ; 6080 UINT32 iep_msi_addr_low32 : 30 ; 6081 } Bits; 6082 6083 6084 UINT32 UInt32; 6085 6086 } PCIE_MIEP_P_MSI_LOWER32_BITADDRESS_U; 6087 6088 6089 6090 6091 typedef union tagMiepPLinkCapability 6092 { 6093 6094 struct 6095 { 6096 UINT32 cfg_pcie_max_link_speed : 4 ; 6097 UINT32 cfg_pcie_max_link_width : 6 ; 6098 UINT32 active_state_power_management : 2 ; 6099 UINT32 l0s_exit_latency : 3 ; 6100 UINT32 l1_exit_latency : 3 ; 6101 UINT32 clock_power_management : 1 ; 6102 UINT32 surprise_down_error_report_cap : 1 ; 6103 UINT32 data_link_layer_active_report_cap : 1 ; 6104 UINT32 link_bandwidth_noti_cap : 1 ; 6105 UINT32 aspm_option_compliance : 1 ; 6106 UINT32 Reserved_19 : 1 ; 6107 UINT32 cfg_pcie_port_num : 8 ; 6108 } Bits; 6109 6110 6111 UINT32 UInt32; 6112 6113 } PCIE_MIEP_P_LINK_CAPABILITY_U; 6114 6115 6116 6117 6118 typedef union tagMiepPAerCapHeader 6119 { 6120 6121 struct 6122 { 6123 UINT32 PCIE_Extended_Capability_ID : 16 ; 6124 UINT32 Capability_Version : 4 ; 6125 UINT32 Next_Capability_Offset : 12 ; 6126 } Bits; 6127 6128 6129 UINT32 UInt32; 6130 6131 } PCIE_MIEP_P_AER_CAP_HEADER_U; 6132 6133 6134 6135 6136 typedef union tagMiepSbar23xlatLower 6137 { 6138 6139 struct 6140 { 6141 UINT32 Reserved_26 : 12 ; 6142 UINT32 sbar23_xlat_lower : 20 ; 6143 } Bits; 6144 6145 6146 UINT32 UInt32; 6147 6148 } PCIE_MIEP_SBAR23XLAT_LOWER_U; 6149 6150 6151 6152 6153 typedef union tagMiepSbar45xlatLower 6154 { 6155 6156 struct 6157 { 6158 UINT32 Reserved_28 : 12 ; 6159 UINT32 sbar45_xlat_lower : 20 ; 6160 } Bits; 6161 6162 6163 UINT32 UInt32; 6164 6165 } PCIE_MIEP_SBAR45XLAT_LOWER_U; 6166 6167 6168 6169 6170 typedef union tagMiepSbar23lmtLower 6171 { 6172 6173 struct 6174 { 6175 UINT32 Reserved_29 : 12 ; 6176 UINT32 sbar23_limit_lower : 20 ; 6177 } Bits; 6178 6179 6180 UINT32 UInt32; 6181 6182 } PCIE_MIEP_SBAR23LMT_LOWER_U; 6183 6184 6185 6186 6187 typedef union tagMiepSbar45lmtLower 6188 { 6189 6190 struct 6191 { 6192 UINT32 Reserved_30 : 12 ; 6193 UINT32 sbar45_limit_lower : 20 ; 6194 } Bits; 6195 6196 6197 UINT32 UInt32; 6198 6199 } PCIE_MIEP_SBAR45LMT_LOWER_U; 6200 6201 6202 6203 6204 typedef union tagMiepSbar45lmtUpper 6205 { 6206 6207 struct 6208 { 6209 UINT32 Reserved_31 : 12 ; 6210 UINT32 sbar45_limit_upper : 20 ; 6211 } Bits; 6212 6213 6214 UINT32 UInt32; 6215 6216 } PCIE_MIEP_SBAR45LMT_UPPER_U; 6217 6218 6219 6220 6221 typedef union tagMiepCbdfSbdf 6222 { 6223 6224 struct 6225 { 6226 UINT32 sfunc : 3 ; 6227 UINT32 sdev : 5 ; 6228 UINT32 sbus : 8 ; 6229 UINT32 cap_sfunc_num : 3 ; 6230 UINT32 cap_sdev_num : 5 ; 6231 UINT32 cap_sbus_num : 8 ; 6232 } Bits; 6233 6234 6235 UINT32 UInt32; 6236 6237 } PCIE_MIEP_CBDF_SBDF_U; 6238 6239 6240 6241 6242 typedef union tagMiepPciCfgHdr0 6243 { 6244 6245 struct 6246 { 6247 UINT32 vendor_id : 16 ; 6248 UINT32 device_id : 16 ; 6249 } Bits; 6250 6251 6252 UINT32 UInt32; 6253 6254 } PCIE_MIEP_PCI_CFG_HDR0_U; 6255 6256 6257 6258 6259 typedef union tagMiepPciCfgHdr1 6260 { 6261 6262 struct 6263 { 6264 UINT32 io_space_enable : 1 ; 6265 UINT32 memory_space_enable : 1 ; 6266 UINT32 bus_master_enable : 1 ; 6267 UINT32 specialcycleenable : 1 ; 6268 UINT32 memory_write_and_invalidate : 1 ; 6269 UINT32 vga_palette_snoop_enable : 1 ; 6270 UINT32 parity_error_response : 1 ; 6271 UINT32 idsel_stepping_waitcycle_control : 1 ; 6272 UINT32 serr_enable : 1 ; 6273 UINT32 fastback_to_backenable : 1 ; 6274 UINT32 interrupt_disable : 1 ; 6275 UINT32 Reserved_35 : 5 ; 6276 UINT32 Reserved_34 : 3 ; 6277 UINT32 intx_status : 1 ; 6278 UINT32 capabilitieslist : 1 ; 6279 UINT32 pcibus66mhzcapable : 1 ; 6280 UINT32 Reserved_33 : 1 ; 6281 UINT32 fastback_to_back : 1 ; 6282 UINT32 masterdataparityerror : 1 ; 6283 UINT32 devsel_timing : 2 ; 6284 UINT32 signaled_target_abort : 1 ; 6285 UINT32 received_target_abort : 1 ; 6286 UINT32 received_master_abort : 1 ; 6287 UINT32 signaled_system_error : 1 ; 6288 UINT32 detected_perr : 1 ; 6289 } Bits; 6290 6291 6292 UINT32 UInt32; 6293 6294 } PCIE_MIEP_PCI_CFG_HDR1_U; 6295 6296 6297 6298 6299 typedef union tagMiepPciCfgHdr11 6300 { 6301 6302 struct 6303 { 6304 UINT32 subsystem_vendor_id : 16 ; 6305 UINT32 subsystemid : 16 ; 6306 } Bits; 6307 6308 6309 UINT32 UInt32; 6310 6311 } PCIE_MIEP_PCI_CFG_HDR11_U; 6312 6313 6314 6315 6316 typedef union tagMiepPciCfgHdr13 6317 { 6318 6319 struct 6320 { 6321 UINT32 capptr : 8 ; 6322 UINT32 Reserved_37 : 24 ; 6323 } Bits; 6324 6325 6326 UINT32 UInt32; 6327 6328 } PCIE_MIEP_PCI_CFG_HDR13_U; 6329 6330 6331 6332 6333 typedef union tagMiepPciCfgHdr15 6334 { 6335 6336 struct 6337 { 6338 UINT32 int_line : 8 ; 6339 UINT32 int_pin : 8 ; 6340 UINT32 min_grant : 8 ; 6341 UINT32 max_latency : 8 ; 6342 } Bits; 6343 6344 6345 UINT32 UInt32; 6346 6347 } PCIE_MIEP_PCI_CFG_HDR15_U; 6348 6349 6350 6351 6352 typedef union tagMiepPciMsiCap0 6353 { 6354 6355 struct 6356 { 6357 UINT32 msi_cap_id : 8 ; 6358 UINT32 next_capability_pointer : 8 ; 6359 UINT32 msi_enabled : 1 ; 6360 UINT32 multiple_message_capable : 3 ; 6361 UINT32 multiple_message_enabled : 3 ; 6362 UINT32 msi_64_en : 1 ; 6363 UINT32 pvm_en : 1 ; 6364 UINT32 message_control_register : 7 ; 6365 } Bits; 6366 6367 6368 UINT32 UInt32; 6369 6370 } PCIE_MIEP_PCI_MSI_CAP0_U; 6371 6372 6373 6374 6375 typedef union tagMiepPciMsiCap1 6376 { 6377 6378 struct 6379 { 6380 UINT32 Reserved_42 : 2 ; 6381 UINT32 msi_addr_low : 30 ; 6382 } Bits; 6383 6384 6385 UINT32 UInt32; 6386 6387 } PCIE_MIEP_PCI_MSI_CAP1_U; 6388 6389 6390 6391 6392 typedef union tagMiepPciMsiCap3 6393 { 6394 6395 struct 6396 { 6397 UINT32 msi_data : 16 ; 6398 UINT32 Reserved_43 : 16 ; 6399 } Bits; 6400 6401 6402 UINT32 UInt32; 6403 6404 } PCIE_MIEP_PCI_MSI_CAP3_U; 6405 6406 6407 6408 6409 typedef union tagMiepPcieCap0 6410 { 6411 6412 struct 6413 { 6414 UINT32 pcie_cap_id : 8 ; 6415 UINT32 pcie_next_ptr : 8 ; 6416 UINT32 pcie_capability_version : 4 ; 6417 UINT32 device_port_type : 4 ; 6418 UINT32 slot_implemented : 1 ; 6419 UINT32 interrupt_message_number : 5 ; 6420 UINT32 Reserved_44 : 2 ; 6421 } Bits; 6422 6423 6424 UINT32 UInt32; 6425 6426 } PCIE_MIEP_PCIE_CAP0_U; 6427 6428 6429 6430 6431 typedef union tagMiepPcieCap1 6432 { 6433 6434 struct 6435 { 6436 UINT32 max_payload_size_supported : 3 ; 6437 UINT32 phantom_function_supported : 2 ; 6438 UINT32 extended_tagfield_supported : 1 ; 6439 UINT32 endpoint_l0sacceptable_latency : 3 ; 6440 UINT32 endpoint_l1acceptable_latency : 3 ; 6441 UINT32 undefined : 3 ; 6442 UINT32 Reserved_47 : 3 ; 6443 UINT32 captured_slot_power_limit_value : 8 ; 6444 UINT32 captured_slot_power_limit_scale : 2 ; 6445 UINT32 function_level_reset : 1 ; 6446 UINT32 Reserved_46 : 3 ; 6447 } Bits; 6448 6449 6450 UINT32 UInt32; 6451 6452 } PCIE_MIEP_PCIE_CAP1_U; 6453 6454 6455 6456 6457 typedef union tagMiepPcieCap2 6458 { 6459 6460 struct 6461 { 6462 UINT32 correctable_error_reporting_enable : 1 ; 6463 UINT32 non_fatal_error_reporting_enable : 1 ; 6464 UINT32 fatal_error_reporting_enable : 1 ; 6465 UINT32 urenable : 1 ; 6466 UINT32 enable_relaxed_ordering : 1 ; 6467 UINT32 max_payload_size : 3 ; 6468 UINT32 extended_tagfieldenable : 1 ; 6469 UINT32 phantom_function_enable : 1 ; 6470 UINT32 auxpowerpmenable : 1 ; 6471 UINT32 enablenosnoop : 1 ; 6472 UINT32 max_read_request_size : 3 ; 6473 UINT32 Reserved_49 : 1 ; 6474 UINT32 correctableerrordetected : 1 ; 6475 UINT32 non_fatalerrordetected : 1 ; 6476 UINT32 fatalerrordetected : 1 ; 6477 UINT32 unsupportedrequestdetected : 1 ; 6478 UINT32 auxpowerdetected : 1 ; 6479 UINT32 transactionpending : 1 ; 6480 UINT32 Reserved_48 : 10 ; 6481 } Bits; 6482 6483 6484 UINT32 UInt32; 6485 6486 } PCIE_MIEP_PCIE_CAP2_U; 6487 6488 6489 6490 6491 typedef union tagMiepPcieCap3 6492 { 6493 6494 struct 6495 { 6496 UINT32 max_link_speed : 4 ; 6497 UINT32 max_link_width : 6 ; 6498 UINT32 active_state_power_management : 2 ; 6499 UINT32 l0s_exitlatency : 3 ; 6500 UINT32 l1_exit_latency : 3 ; 6501 UINT32 clock_power_management : 1 ; 6502 UINT32 surprise_down_error_report_cap : 1 ; 6503 UINT32 data_link_layer_active_report_cap : 1 ; 6504 UINT32 link_bandwidth_noti_cap : 1 ; 6505 UINT32 aspm_option_compliance : 1 ; 6506 UINT32 Reserved_50 : 1 ; 6507 UINT32 port_number : 8 ; 6508 } Bits; 6509 6510 6511 UINT32 UInt32; 6512 6513 } PCIE_MIEP_PCIE_CAP3_U; 6514 6515 6516 6517 6518 typedef union tagMiepPcieCap4 6519 { 6520 6521 struct 6522 { 6523 UINT32 active_state_power_management : 2 ; 6524 UINT32 Reserved_53 : 1 ; 6525 UINT32 rcb : 1 ; 6526 UINT32 link_disable : 1 ; 6527 UINT32 retrain_link : 1 ; 6528 UINT32 common_clock_config : 1 ; 6529 UINT32 extended_sync : 1 ; 6530 UINT32 enable_clock_pwr_management : 1 ; 6531 UINT32 hw_auto_width_disable : 1 ; 6532 UINT32 link_bandwidth_management_int_en : 1 ; 6533 UINT32 link_auto_bandwidth_int_en : 1 ; 6534 UINT32 Reserved_52 : 4 ; 6535 UINT32 current_link_speed : 4 ; 6536 UINT32 negotiated_link_width : 6 ; 6537 UINT32 Reserved_51 : 1 ; 6538 UINT32 link_training : 1 ; 6539 UINT32 slot_clock_configration : 1 ; 6540 UINT32 data_link_layer_active : 1 ; 6541 UINT32 link_bandwidth_management_status : 1 ; 6542 UINT32 link_auto_bandwidth_status : 1 ; 6543 } Bits; 6544 6545 6546 UINT32 UInt32; 6547 6548 } PCIE_MIEP_PCIE_CAP4_U; 6549 6550 6551 6552 6553 typedef union tagMiepPcieCap5 6554 { 6555 6556 struct 6557 { 6558 UINT32 attentioonbuttonpresent : 1 ; 6559 UINT32 powercontrollerpresent : 1 ; 6560 UINT32 mrlsensorpresent : 1 ; 6561 UINT32 attentionindicatorpresent : 1 ; 6562 UINT32 powerindicatorpresent : 1 ; 6563 UINT32 hot_plugsurprise : 1 ; 6564 UINT32 hot_plugcapable : 1 ; 6565 UINT32 slotpowerlimitvalue : 8 ; 6566 UINT32 slotpowerlimitscale : 2 ; 6567 UINT32 electromechanicalinterlockpresen : 1 ; 6568 UINT32 no_cmd_complete_support : 1 ; 6569 UINT32 phy_slot_number : 13 ; 6570 } Bits; 6571 6572 6573 UINT32 UInt32; 6574 6575 } PCIE_MIEP_PCIE_CAP5_U; 6576 6577 6578 6579 6580 typedef union tagMiepPcieCap6 6581 { 6582 6583 struct 6584 { 6585 UINT32 attentionbuttonpressedenable : 1 ; 6586 UINT32 powerfaultdetectedenable : 1 ; 6587 UINT32 mrlsensorchangedenable : 1 ; 6588 UINT32 presencedetectchangedenable : 1 ; 6589 UINT32 commandcompletedinterruptenable : 1 ; 6590 UINT32 hot_pluginterruptenable : 1 ; 6591 UINT32 attentionindicatorcontrol : 2 ; 6592 UINT32 powerindicatorcontrol : 2 ; 6593 UINT32 powercontrollercontrol : 1 ; 6594 UINT32 electromechanicalinterlockcontrol : 1 ; 6595 UINT32 datalinklayerstatechangedenable : 1 ; 6596 UINT32 Reserved_54 : 3 ; 6597 UINT32 attentionbuttonpressed : 1 ; 6598 UINT32 powerfaultdetected : 1 ; 6599 UINT32 mrlsensorchanged : 1 ; 6600 UINT32 presencedetectchanged : 1 ; 6601 UINT32 commandcompleted : 1 ; 6602 UINT32 mrlsensorstate : 1 ; 6603 UINT32 presencedetectstate : 1 ; 6604 UINT32 electromechanicalinterlockstatus : 1 ; 6605 UINT32 datalinklayerstatechanged : 1 ; 6606 UINT32 slot_ctrl_status : 7 ; 6607 } Bits; 6608 6609 6610 UINT32 UInt32; 6611 6612 } PCIE_MIEP_PCIE_CAP6_U; 6613 6614 6615 6616 6617 typedef union tagMiepPcieCap7 6618 { 6619 6620 struct 6621 { 6622 UINT32 systemerroroncorrectableerrorenable : 1 ; 6623 UINT32 systemerroronnon_fatalerrorenable : 1 ; 6624 UINT32 systemerroronfatalerrorenable : 1 ; 6625 UINT32 pmeinterruptenable : 1 ; 6626 UINT32 crssoftwarevisibilityenable : 1 ; 6627 UINT32 Reserved_55 : 11 ; 6628 UINT32 crssoftwarevisibility : 1 ; 6629 UINT32 root_cap : 15 ; 6630 } Bits; 6631 6632 6633 UINT32 UInt32; 6634 6635 } PCIE_MIEP_PCIE_CAP7_U; 6636 6637 6638 6639 6640 typedef union tagMiepPcieCap8 6641 { 6642 6643 struct 6644 { 6645 UINT32 pmerequesterid : 16 ; 6646 UINT32 pmestatus : 1 ; 6647 UINT32 pmepending : 1 ; 6648 UINT32 root_status : 14 ; 6649 } Bits; 6650 6651 6652 UINT32 UInt32; 6653 6654 } PCIE_MIEP_PCIE_CAP8_U; 6655 6656 6657 6658 6659 typedef union tagMiepPcieCap9 6660 { 6661 6662 struct 6663 { 6664 UINT32 completiontimeoutrangessupported : 4 ; 6665 UINT32 completiontimeoutdisablesupported : 1 ; 6666 UINT32 ariforwardingsupported : 1 ; 6667 UINT32 atomicoproutingsupported : 1 ; 6668 UINT32 _2_bitatomicopcompletersupported : 1 ; 6669 UINT32 _4_bitatomicopcompletersupported : 1 ; 6670 UINT32 _28_bitcascompletersupported : 1 ; 6671 UINT32 noro_enabledpr_prpassing : 1 ; 6672 UINT32 Reserved_56 : 1 ; 6673 UINT32 tphcompletersupported : 2 ; 6674 UINT32 dev_cap2 : 18 ; 6675 } Bits; 6676 6677 6678 UINT32 UInt32; 6679 6680 } PCIE_MIEP_PCIE_CAP9_U; 6681 6682 6683 6684 6685 typedef union tagMiepPcieCap10 6686 { 6687 6688 struct 6689 { 6690 UINT32 completiontimeoutvalue : 4 ; 6691 UINT32 completiontimeoutdisable : 1 ; 6692 UINT32 ariforwardingsupported : 1 ; 6693 UINT32 atomicoprequesterenable : 1 ; 6694 UINT32 atomicopegressblocking : 1 ; 6695 UINT32 idorequestenable : 1 ; 6696 UINT32 idocompletionenable : 1 ; 6697 UINT32 dev_ctrl2 : 22 ; 6698 } Bits; 6699 6700 6701 UINT32 UInt32; 6702 6703 } PCIE_MIEP_PCIE_CAP10_U; 6704 6705 6706 6707 6708 typedef union tagMiepPcieCap11 6709 { 6710 6711 struct 6712 { 6713 UINT32 Reserved_58 : 1 ; 6714 UINT32 gen1_suport : 1 ; 6715 UINT32 gen2_suport : 1 ; 6716 UINT32 gen3_suport : 1 ; 6717 UINT32 Reserved_57 : 4 ; 6718 UINT32 crosslink_supported : 1 ; 6719 UINT32 link_cap2 : 23 ; 6720 } Bits; 6721 6722 6723 UINT32 UInt32; 6724 6725 } PCIE_MIEP_PCIE_CAP11_U; 6726 6727 6728 6729 6730 typedef union tagMiepPcieCap12 6731 { 6732 6733 struct 6734 { 6735 UINT32 targetlinkspeed : 4 ; 6736 UINT32 entercompliance : 1 ; 6737 UINT32 hardwareautonomousspeeddisa : 1 ; 6738 UINT32 selectablede_empha : 1 ; 6739 UINT32 transmitmargin : 3 ; 6740 UINT32 _entermodifiedcompliance : 1 ; 6741 UINT32 compliancesos : 1 ; 6742 UINT32 de_emphasislevel : 4 ; 6743 UINT32 currentde_emphasislevel : 1 ; 6744 UINT32 equalizationcomplete : 1 ; 6745 UINT32 equalizationphase1successful : 1 ; 6746 UINT32 equalizationphase2successful : 1 ; 6747 UINT32 equalizationphase3successful : 1 ; 6748 UINT32 linkequalizationrequest : 1 ; 6749 UINT32 link_ctrl2_status2 : 10 ; 6750 } Bits; 6751 6752 6753 UINT32 UInt32; 6754 6755 } PCIE_MIEP_PCIE_CAP12_U; 6756 6757 6758 6759 6760 typedef union tagMiepSlotCap 6761 { 6762 6763 struct 6764 { 6765 UINT32 slotnumberingcapabilitiesid : 8 ; 6766 UINT32 nextcapabilitypointer : 8 ; 6767 UINT32 add_incardslotsprovided : 5 ; 6768 UINT32 firstinchassis : 1 ; 6769 UINT32 Reserved_59 : 2 ; 6770 UINT32 slot_cap : 8 ; 6771 } Bits; 6772 6773 6774 UINT32 UInt32; 6775 6776 } PCIE_MIEP_SLOT_CAP_U; 6777 6778 6779 6780 6781 typedef union tagMiepAerCap0 6782 { 6783 6784 struct 6785 { 6786 UINT32 pciexpressextendedcapabilityid : 16 ; 6787 UINT32 capabilityversion : 4 ; 6788 UINT32 aer_cap_hdr : 12 ; 6789 } Bits; 6790 6791 6792 UINT32 UInt32; 6793 6794 } PCIE_MIEP_AER_CAP0_U; 6795 6796 6797 6798 6799 typedef union tagMiepAerCap1 6800 { 6801 6802 struct 6803 { 6804 UINT32 Reserved_65 : 1 ; 6805 UINT32 Reserved_64 : 3 ; 6806 UINT32 datalinkprotocolerrorsta : 1 ; 6807 UINT32 surprisedownerrorstatus : 1 ; 6808 UINT32 Reserved_63 : 6 ; 6809 UINT32 poisonedtlpstatu : 1 ; 6810 UINT32 flowcontrolprotocolerrorst : 1 ; 6811 UINT32 completiontimeouts : 1 ; 6812 UINT32 completerabortstatus : 1 ; 6813 UINT32 receiveroverflowstatus : 1 ; 6814 UINT32 malformedtlpstatus : 1 ; 6815 UINT32 ecrcerrorstatus : 1 ; 6816 UINT32 ecrcerrorstat : 1 ; 6817 UINT32 unsupportedrequesterrorstatus : 1 ; 6818 UINT32 Reserved_62 : 3 ; 6819 UINT32 atomicopegressblockedstatus : 1 ; 6820 UINT32 uncorr_err_status : 7 ; 6821 } Bits; 6822 6823 6824 UINT32 UInt32; 6825 6826 } PCIE_MIEP_AER_CAP1_U; 6827 6828 6829 6830 6831 typedef union tagMiepAerCap2 6832 { 6833 6834 struct 6835 { 6836 UINT32 Reserved_69 : 1 ; 6837 UINT32 Reserved_68 : 3 ; 6838 UINT32 datalinkprotocolerrormask : 1 ; 6839 UINT32 surprisedownerrormask : 1 ; 6840 UINT32 Reserved_67 : 6 ; 6841 UINT32 poisonedtlpmask : 1 ; 6842 UINT32 flowcontrolprotocolerrormask : 1 ; 6843 UINT32 completiontimeoutmask : 1 ; 6844 UINT32 completerabortmask : 1 ; 6845 UINT32 unexpectedcompletionmask : 1 ; 6846 UINT32 receiveroverflowmask : 1 ; 6847 UINT32 malformedtlpmask : 1 ; 6848 UINT32 ecrcerrormask : 1 ; 6849 UINT32 unsupportedrequesterrormask : 1 ; 6850 UINT32 Reserved_66 : 3 ; 6851 UINT32 atomicopegressblockedmask : 1 ; 6852 UINT32 uncorr_err_mask : 7 ; 6853 } Bits; 6854 6855 6856 UINT32 UInt32; 6857 6858 } PCIE_MIEP_AER_CAP2_U; 6859 6860 6861 6862 6863 typedef union tagMiepAerCap3 6864 { 6865 6866 struct 6867 { 6868 UINT32 Reserved_73 : 1 ; 6869 UINT32 Reserved_72 : 3 ; 6870 UINT32 datalinkprotocolerrorsever : 1 ; 6871 UINT32 surprisedownerrorseverity : 1 ; 6872 UINT32 Reserved_71 : 6 ; 6873 UINT32 poisonedtlpseverity : 1 ; 6874 UINT32 flowcontrolprotocolerrorseveri : 1 ; 6875 UINT32 completiontimeoutseverity : 1 ; 6876 UINT32 completerabortseverity : 1 ; 6877 UINT32 unexpectedcompletionseverity : 1 ; 6878 UINT32 receiveroverflowseverity : 1 ; 6879 UINT32 malformedtlpseverity : 1 ; 6880 UINT32 ecrcerrorseverity : 1 ; 6881 UINT32 unsupportedrequesterrorseverity : 1 ; 6882 UINT32 Reserved_70 : 3 ; 6883 UINT32 atomicopegressblockedseverity : 1 ; 6884 UINT32 uncorr_err_ser : 7 ; 6885 } Bits; 6886 6887 6888 UINT32 UInt32; 6889 6890 } PCIE_MIEP_AER_CAP3_U; 6891 6892 6893 6894 6895 typedef union tagMiepAerCap4 6896 { 6897 6898 struct 6899 { 6900 UINT32 receivererrorstatus : 1 ; 6901 UINT32 Reserved_75 : 5 ; 6902 UINT32 badtlpstatus : 1 ; 6903 UINT32 baddllpstatus : 1 ; 6904 UINT32 replay_numrolloverstatus : 1 ; 6905 UINT32 Reserved_74 : 3 ; 6906 UINT32 replytimertimeoutstatus : 1 ; 6907 UINT32 advisorynon_fatalerrorstatus : 1 ; 6908 UINT32 corr_err_status : 18 ; 6909 } Bits; 6910 6911 6912 UINT32 UInt32; 6913 6914 } PCIE_MIEP_AER_CAP4_U; 6915 6916 6917 6918 6919 typedef union tagMiepAerCap5 6920 { 6921 6922 struct 6923 { 6924 UINT32 receivererrormask : 1 ; 6925 UINT32 Reserved_77 : 5 ; 6926 UINT32 badtlpmask : 1 ; 6927 UINT32 baddllpmask : 1 ; 6928 UINT32 replay_numrollovermask : 1 ; 6929 UINT32 Reserved_76 : 3 ; 6930 UINT32 replytimertimeoutmask : 1 ; 6931 UINT32 advisorynon_fatalerrormask : 1 ; 6932 UINT32 corr_err_mask : 18 ; 6933 } Bits; 6934 6935 6936 UINT32 UInt32; 6937 6938 } PCIE_MIEP_AER_CAP5_U; 6939 6940 6941 6942 6943 typedef union tagMiepAerCap6 6944 { 6945 6946 struct 6947 { 6948 UINT32 firsterrorpointer : 5 ; 6949 UINT32 ecrcgenerationcapability : 1 ; 6950 UINT32 ecrcgenerationenable : 1 ; 6951 UINT32 ecrccheckcapable : 1 ; 6952 UINT32 ecrccheckenable : 1 ; 6953 UINT32 adv_cap_ctrl : 23 ; 6954 } Bits; 6955 6956 6957 UINT32 UInt32; 6958 6959 } PCIE_MIEP_AER_CAP6_U; 6960 6961 6962 6963 6964 typedef union tagMiepAerCap11 6965 { 6966 6967 struct 6968 { 6969 UINT32 correctableerrorreportingenable : 1 ; 6970 UINT32 non_fatalerrorreportingenable : 1 ; 6971 UINT32 fatalerrorreportingenable : 1 ; 6972 UINT32 root_err_cmd : 29 ; 6973 } Bits; 6974 6975 6976 UINT32 UInt32; 6977 6978 } PCIE_MIEP_AER_CAP11_U; 6979 6980 6981 6982 6983 typedef union tagMiepAerCap12 6984 { 6985 6986 struct 6987 { 6988 UINT32 err_correceived : 1 ; 6989 UINT32 multipleerr_correceived : 1 ; 6990 UINT32 err_fatal_nonfatalreceived : 1 ; 6991 UINT32 multipleerr_fatal_nonfatalreceived : 1 ; 6992 UINT32 firstuncorrectablefatal : 1 ; 6993 UINT32 non_fatalerrormessagesreceived : 1 ; 6994 UINT32 fatalerrormessagesreceived : 1 ; 6995 UINT32 Reserved_78 : 20 ; 6996 UINT32 root_err_status : 5 ; 6997 } Bits; 6998 6999 7000 UINT32 UInt32; 7001 7002 } PCIE_MIEP_AER_CAP12_U; 7003 7004 7005 7006 7007 typedef union tagMiepAerCap13 7008 { 7009 7010 struct 7011 { 7012 UINT32 err_corsourceidentification : 16 ; 7013 UINT32 err_src_id : 16 ; 7014 } Bits; 7015 7016 7017 UINT32 UInt32; 7018 7019 } PCIE_MIEP_AER_CAP13_U; 7020 7021 7022 7023 7024 typedef union tagMiepVcCap0 7025 { 7026 7027 struct 7028 { 7029 UINT32 pciexpressextendedcapabilityid : 16 ; 7030 UINT32 capabilityversion : 4 ; 7031 UINT32 vc_cap_hdr : 12 ; 7032 } Bits; 7033 7034 7035 UINT32 UInt32; 7036 7037 } PCIE_MIEP_VC_CAP0_U; 7038 7039 7040 7041 7042 typedef union tagMiepVcCap1 7043 { 7044 7045 struct 7046 { 7047 UINT32 extendedvccount : 3 ; 7048 UINT32 Reserved_81 : 1 ; 7049 UINT32 lowpriorityextendedvccount : 3 ; 7050 UINT32 Reserved_80 : 1 ; 7051 UINT32 referenceclock : 2 ; 7052 UINT32 portarbitrationtableentrysize : 2 ; 7053 UINT32 vc_cap1 : 20 ; 7054 } Bits; 7055 7056 7057 UINT32 UInt32; 7058 7059 } PCIE_MIEP_VC_CAP1_U; 7060 7061 7062 7063 7064 typedef union tagMiepVcCap2 7065 { 7066 7067 struct 7068 { 7069 UINT32 vcarbitrationcapability : 8 ; 7070 UINT32 Reserved_82 : 16 ; 7071 UINT32 vc_cap2 : 8 ; 7072 } Bits; 7073 7074 7075 UINT32 UInt32; 7076 7077 } PCIE_MIEP_VC_CAP2_U; 7078 7079 7080 7081 7082 typedef union tagMiepVcCap3 7083 { 7084 7085 struct 7086 { 7087 UINT32 loadvcarbitrationtable : 1 ; 7088 UINT32 vcarbitrationselect : 3 ; 7089 UINT32 Reserved_84 : 12 ; 7090 UINT32 arbitrationtablestatus : 1 ; 7091 UINT32 Reserved_83 : 15 ; 7092 } Bits; 7093 7094 7095 UINT32 UInt32; 7096 7097 } PCIE_MIEP_VC_CAP3_U; 7098 7099 7100 7101 7102 typedef union tagMiepVcCap4 7103 { 7104 7105 struct 7106 { 7107 UINT32 portarbitrationcapability : 8 ; 7108 UINT32 Reserved_87 : 6 ; 7109 UINT32 Reserved_86 : 1 ; 7110 UINT32 rejectsnooptransactions : 1 ; 7111 UINT32 maximumtimeslots : 7 ; 7112 UINT32 Reserved_85 : 1 ; 7113 UINT32 vc_res_cap : 8 ; 7114 } Bits; 7115 7116 7117 UINT32 UInt32; 7118 7119 } PCIE_MIEP_VC_CAP4_U; 7120 7121 7122 7123 7124 typedef union tagMiepVcCap5 7125 { 7126 7127 struct 7128 { 7129 UINT32 tc_vcmap : 8 ; 7130 UINT32 Reserved_90 : 8 ; 7131 UINT32 loadportarbitrationtable : 1 ; 7132 UINT32 portarbitrationselec : 3 ; 7133 UINT32 Reserved_89 : 4 ; 7134 UINT32 vcid : 3 ; 7135 UINT32 Reserved_88 : 4 ; 7136 UINT32 vc_res_ctrl : 1 ; 7137 } Bits; 7138 7139 7140 UINT32 UInt32; 7141 7142 } PCIE_MIEP_VC_CAP5_U; 7143 7144 7145 7146 7147 typedef union tagMiepVcCap6 7148 { 7149 7150 struct 7151 { 7152 UINT32 Reserved_91 : 16 ; 7153 UINT32 portarbitrationtablestatus : 1 ; 7154 UINT32 vcnegotiationpending : 1 ; 7155 UINT32 vc_res_status : 14 ; 7156 } Bits; 7157 7158 7159 UINT32 UInt32; 7160 7161 } PCIE_MIEP_VC_CAP6_U; 7162 7163 7164 7165 7166 typedef union tagMiepVcCap7 7167 { 7168 7169 struct 7170 { 7171 UINT32 portarbitrationcapability : 8 ; 7172 UINT32 Reserved_94 : 6 ; 7173 UINT32 Reserved_93 : 1 ; 7174 UINT32 rejectsnooptransactions : 1 ; 7175 UINT32 maximumtimeslots : 7 ; 7176 UINT32 Reserved_92 : 1 ; 7177 UINT32 vc_res_cap0 : 8 ; 7178 } Bits; 7179 7180 7181 UINT32 UInt32; 7182 7183 } PCIE_MIEP_VC_CAP7_U; 7184 7185 7186 7187 7188 typedef union tagMiepVcCap8 7189 { 7190 7191 struct 7192 { 7193 UINT32 tc_vcmap : 8 ; 7194 UINT32 Reserved_97 : 8 ; 7195 UINT32 loadportarbitrationtable : 1 ; 7196 UINT32 portarbitrationselect : 3 ; 7197 UINT32 Reserved_96 : 4 ; 7198 UINT32 vcid : 3 ; 7199 UINT32 Reserved_95 : 4 ; 7200 UINT32 vc_res_ctrl0 : 1 ; 7201 } Bits; 7202 7203 7204 UINT32 UInt32; 7205 7206 } PCIE_MIEP_VC_CAP8_U; 7207 7208 7209 7210 7211 typedef union tagMiepVcCap9 7212 { 7213 7214 struct 7215 { 7216 UINT32 Reserved_98 : 16 ; 7217 UINT32 arbitrationtablestatus : 1 ; 7218 UINT32 vcnegotiationpending : 1 ; 7219 UINT32 vc_res_status0 : 14 ; 7220 } Bits; 7221 7222 7223 UINT32 UInt32; 7224 7225 } PCIE_MIEP_VC_CAP9_U; 7226 7227 7228 7229 7230 typedef union tagMiepPortLogic0 7231 { 7232 7233 struct 7234 { 7235 UINT32 ack_lat_timer : 16 ; 7236 UINT32 replay_timer : 16 ; 7237 } Bits; 7238 7239 7240 UINT32 UInt32; 7241 7242 } PCIE_MIEP_PORT_LOGIC0_U; 7243 7244 7245 7246 7247 typedef union tagMiepPortLogic2 7248 { 7249 7250 struct 7251 { 7252 UINT32 linknumber : 8 ; 7253 UINT32 Reserved_101 : 7 ; 7254 UINT32 forcelink : 1 ; 7255 UINT32 linkstate : 6 ; 7256 UINT32 Reserved_100 : 2 ; 7257 UINT32 port_force_link : 8 ; 7258 } Bits; 7259 7260 7261 UINT32 UInt32; 7262 7263 } PCIE_MIEP_PORT_LOGIC2_U; 7264 7265 7266 7267 7268 typedef union tagMiepPortLogic3 7269 { 7270 7271 struct 7272 { 7273 UINT32 ackfrequency : 8 ; 7274 UINT32 n_fts : 8 ; 7275 UINT32 commonclockn_fts : 8 ; 7276 UINT32 l0sentrancelatency : 3 ; 7277 UINT32 l1entrancelatency : 3 ; 7278 UINT32 enteraspml1withoutreceiveinl0s : 1 ; 7279 UINT32 ack_aspm : 1 ; 7280 } Bits; 7281 7282 7283 UINT32 UInt32; 7284 7285 } PCIE_MIEP_PORT_LOGIC3_U; 7286 7287 7288 7289 7290 typedef union tagMiepPortLogic4 7291 { 7292 7293 struct 7294 { 7295 UINT32 vendorspecificdllprequest : 1 ; 7296 UINT32 scrambledisable : 1 ; 7297 UINT32 loopbackenable : 1 ; 7298 UINT32 resetassert : 1 ; 7299 UINT32 Reserved_104 : 1 ; 7300 UINT32 dlllinkenable : 1 ; 7301 UINT32 Reserved_103 : 1 ; 7302 UINT32 fastlinkmode : 1 ; 7303 UINT32 Reserved_102 : 8 ; 7304 UINT32 linkmodeenable : 6 ; 7305 UINT32 crosslinkenable : 1 ; 7306 UINT32 crosslinkactive : 1 ; 7307 UINT32 port_link_ctrl : 8 ; 7308 } Bits; 7309 7310 7311 UINT32 UInt32; 7312 7313 } PCIE_MIEP_PORT_LOGIC4_U; 7314 7315 7316 7317 7318 typedef union tagMiepPortLogic5 7319 { 7320 7321 struct 7322 { 7323 UINT32 insertlaneskewfortransmit : 24 ; 7324 UINT32 flowcontroldisable : 1 ; 7325 UINT32 ack_nakdisable : 1 ; 7326 UINT32 Reserved_105 : 5 ; 7327 UINT32 lane_skew : 1 ; 7328 } Bits; 7329 7330 7331 UINT32 UInt32; 7332 7333 } PCIE_MIEP_PORT_LOGIC5_U; 7334 7335 7336 7337 7338 typedef union tagMiepPortLogic6 7339 { 7340 7341 struct 7342 { 7343 UINT32 numberoftssymbols : 4 ; 7344 UINT32 Reserved_107 : 4 ; 7345 UINT32 numberofskpsymbols : 3 ; 7346 UINT32 Reserved_106 : 3 ; 7347 UINT32 timermodifierforreplaytimer : 5 ; 7348 UINT32 timermodifierforack_naklatencytimer : 5 ; 7349 UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ; 7350 UINT32 sym_num : 3 ; 7351 } Bits; 7352 7353 7354 UINT32 UInt32; 7355 7356 } PCIE_MIEP_PORT_LOGIC6_U; 7357 7358 7359 7360 7361 typedef union tagMiepPortLogic7 7362 { 7363 7364 struct 7365 { 7366 UINT32 vc0posteddataqueuedepth : 11 ; 7367 UINT32 Reserved_108 : 4 ; 7368 UINT32 sym_timer : 1 ; 7369 UINT32 maskfunctionmismatchfilteringfo : 1 ; 7370 UINT32 maskpoisonedtlpfiltering : 1 ; 7371 UINT32 maskbarmatchfiltering : 1 ; 7372 UINT32 masktype1configurationrequestfiltering : 1 ; 7373 UINT32 masklockedrequestfiltering : 1 ; 7374 UINT32 masktagerrorrulesforreceivedcompletions : 1 ; 7375 UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ; 7376 UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ; 7377 UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ; 7378 UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ; 7379 UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ; 7380 UINT32 maske_crcerror_filtering : 1 ; 7381 UINT32 maske_crcerror_filtering_forcompletions : 1 ; 7382 UINT32 message_control : 1 ; 7383 UINT32 maskfilteringofreceived : 1 ; 7384 UINT32 flt_mask1 : 1 ; 7385 } Bits; 7386 7387 7388 UINT32 UInt32; 7389 7390 } PCIE_MIEP_PORT_LOGIC7_U; 7391 7392 7393 7394 7395 typedef union tagMiepPortLogic8 7396 { 7397 7398 struct 7399 { 7400 UINT32 cx_flt_mask_venmsg0_drop : 1 ; 7401 UINT32 cx_flt_mask_venmsg1_drop : 1 ; 7402 UINT32 cx_flt_mask_dabort_4ucpl : 1 ; 7403 UINT32 cx_flt_mask_handle_flush : 1 ; 7404 UINT32 flt_mask2 : 28 ; 7405 } Bits; 7406 7407 7408 UINT32 UInt32; 7409 7410 } PCIE_MIEP_PORT_LOGIC8_U; 7411 7412 7413 7414 7415 typedef union tagMiepPortLogic9 7416 { 7417 7418 struct 7419 { 7420 UINT32 amba_multi_outbound_decomp_np : 1 ; 7421 UINT32 amba_obnp_ctrl : 31 ; 7422 } Bits; 7423 7424 7425 UINT32 UInt32; 7426 7427 } PCIE_MIEP_PORT_LOGIC9_U; 7428 7429 7430 7431 7432 typedef union tagMiepPortLogic12 7433 { 7434 7435 struct 7436 { 7437 UINT32 transmitposteddatafccredits : 12 ; 7438 UINT32 transmitpostedheaderfccredits : 8 ; 7439 UINT32 tx_pfc_status : 12 ; 7440 } Bits; 7441 7442 7443 UINT32 UInt32; 7444 7445 } PCIE_MIEP_PORT_LOGIC12_U; 7446 7447 7448 7449 7450 typedef union tagMiepPortLogic13 7451 { 7452 7453 struct 7454 { 7455 UINT32 transmitnon_posteddatafccredits : 12 ; 7456 UINT32 transmitnon_postedheaderfccredits : 8 ; 7457 UINT32 tx_npfc_status : 12 ; 7458 } Bits; 7459 7460 7461 UINT32 UInt32; 7462 7463 } PCIE_MIEP_PORT_LOGIC13_U; 7464 7465 7466 7467 7468 typedef union tagMiepPortLogic14 7469 { 7470 7471 struct 7472 { 7473 UINT32 transmitcompletiondatafccredits : 12 ; 7474 UINT32 transmitcompletionheaderfccredits : 8 ; 7475 UINT32 tx_cplfc_status : 12 ; 7476 } Bits; 7477 7478 7479 UINT32 UInt32; 7480 7481 } PCIE_MIEP_PORT_LOGIC14_U; 7482 7483 7484 7485 7486 typedef union tagMiepPortLogic15 7487 { 7488 7489 struct 7490 { 7491 UINT32 rx_tlp_fc_credit_not_retured : 1 ; 7492 UINT32 tx_retry_buf_not_empty : 1 ; 7493 UINT32 rx_queue_not_empty : 1 ; 7494 UINT32 Reserved_110 : 13 ; 7495 UINT32 fc_latency_timer_override_value : 13 ; 7496 UINT32 Reserved_109 : 2 ; 7497 UINT32 fc_latency_timer_override_en : 1 ; 7498 } Bits; 7499 7500 7501 UINT32 UInt32; 7502 7503 } PCIE_MIEP_PORT_LOGIC15_U; 7504 7505 7506 7507 7508 typedef union tagMiepPortLogic16 7509 { 7510 7511 struct 7512 { 7513 UINT32 vc0posteddatacredits : 12 ; 7514 UINT32 vc0postedheadercredits : 8 ; 7515 UINT32 Reserved_112 : 1 ; 7516 UINT32 vc0_postedtlpqueuemode : 1 ; 7517 UINT32 vc0postedtlpqueuemode : 1 ; 7518 UINT32 vc0postedtlpqueuemo : 1 ; 7519 UINT32 Reserved_111 : 6 ; 7520 UINT32 tlptypeorderingforvc0 : 1 ; 7521 UINT32 rx_pque_ctrl : 1 ; 7522 } Bits; 7523 7524 7525 UINT32 UInt32; 7526 7527 } PCIE_MIEP_PORT_LOGIC16_U; 7528 7529 7530 7531 7532 typedef union tagMiepPortLogic17 7533 { 7534 7535 struct 7536 { 7537 UINT32 vc0non_posteddatacredits : 12 ; 7538 UINT32 vc0non_postedheadercredits : 8 ; 7539 UINT32 rx_npque_ctrl : 12 ; 7540 } Bits; 7541 7542 7543 UINT32 UInt32; 7544 7545 } PCIE_MIEP_PORT_LOGIC17_U; 7546 7547 7548 7549 7550 typedef union tagMiepPortLogic18 7551 { 7552 7553 struct 7554 { 7555 UINT32 vco_comp_data_credits : 12 ; 7556 UINT32 vc0_cpl_header_credt : 8 ; 7557 UINT32 Reserved_114 : 12 ; 7558 } Bits; 7559 7560 7561 UINT32 UInt32; 7562 7563 } PCIE_MIEP_PORT_LOGIC18_U; 7564 7565 7566 7567 7568 typedef union tagMiepPortLogic19 7569 { 7570 7571 struct 7572 { 7573 UINT32 vco_posted_data_que_path : 14 ; 7574 UINT32 Reserved_115 : 2 ; 7575 UINT32 vco_posted_head_queue_depth : 10 ; 7576 UINT32 vc_pbuf_ctrl : 6 ; 7577 } Bits; 7578 7579 7580 UINT32 UInt32; 7581 7582 } PCIE_MIEP_PORT_LOGIC19_U; 7583 7584 7585 7586 7587 typedef union tagMiepPortLogic20 7588 { 7589 7590 struct 7591 { 7592 UINT32 vco_np_data_que_depth : 14 ; 7593 UINT32 Reserved_117 : 2 ; 7594 UINT32 vco_np_header_que_depth : 10 ; 7595 UINT32 vc_npbuf_ctrl : 6 ; 7596 } Bits; 7597 7598 7599 UINT32 UInt32; 7600 7601 } PCIE_MIEP_PORT_LOGIC20_U; 7602 7603 7604 7605 7606 typedef union tagMiepPortLogic21 7607 { 7608 7609 struct 7610 { 7611 UINT32 vco_comp_data_queue_depth : 14 ; 7612 UINT32 Reserved_119 : 2 ; 7613 UINT32 vco_posted_head_queue_depth : 10 ; 7614 UINT32 Reserved_118 : 6 ; 7615 } Bits; 7616 7617 7618 UINT32 UInt32; 7619 7620 } PCIE_MIEP_PORT_LOGIC21_U; 7621 7622 7623 7624 7625 typedef union tagMiepPortLogic22 7626 { 7627 7628 struct 7629 { 7630 UINT32 n_fts : 8 ; 7631 UINT32 pre_determ_num_of_lane : 9 ; 7632 UINT32 det_sp_change : 1 ; 7633 UINT32 config_phy_tx_sw : 1 ; 7634 UINT32 config_tx_comp_rcv_bit : 1 ; 7635 UINT32 set_emp_level : 1 ; 7636 UINT32 Reserved_120 : 11 ; 7637 } Bits; 7638 7639 7640 UINT32 UInt32; 7641 7642 } PCIE_MIEP_PORT_LOGIC22_U; 7643 7644 7645 7646 7647 typedef union tagMiepPortlogic25 7648 { 7649 7650 struct 7651 { 7652 UINT32 remote_rd_req_size : 3 ; 7653 UINT32 Reserved_123 : 5 ; 7654 UINT32 remote_max_brd_tag : 8 ; 7655 UINT32 Reserved_122 : 16 ; 7656 } Bits; 7657 7658 7659 UINT32 UInt32; 7660 7661 } PCIE_MIEP_PORTLOGIC25_U; 7662 7663 7664 7665 7666 typedef union tagMiepPortlogic26 7667 { 7668 7669 struct 7670 { 7671 UINT32 resize_master_resp_compser : 1 ; 7672 UINT32 axi_ctrl1 : 31 ; 7673 } Bits; 7674 7675 7676 UINT32 UInt32; 7677 7678 } PCIE_MIEP_PORTLOGIC26_U; 7679 7680 7681 7682 7683 typedef union tagMiepPortlogic54 7684 { 7685 7686 struct 7687 { 7688 UINT32 region_index : 4 ; 7689 UINT32 Reserved_124 : 27 ; 7690 UINT32 iatu_view : 1 ; 7691 } Bits; 7692 7693 7694 UINT32 UInt32; 7695 7696 } PCIE_MIEP_PORTLOGIC54_U; 7697 7698 7699 7700 7701 typedef union tagMiepPortlogic55 7702 { 7703 7704 struct 7705 { 7706 UINT32 iatu1_type : 5 ; 7707 UINT32 iatu1_tc : 3 ; 7708 UINT32 iatu1_td : 1 ; 7709 UINT32 iatu1_attr : 2 ; 7710 UINT32 Reserved_128 : 5 ; 7711 UINT32 iatu1_at : 2 ; 7712 UINT32 Reserved_127 : 2 ; 7713 UINT32 iatu1_id : 3 ; 7714 UINT32 Reserved_126 : 9 ; 7715 } Bits; 7716 7717 7718 UINT32 UInt32; 7719 7720 } PCIE_MIEP_PORTLOGIC55_U; 7721 7722 7723 7724 7725 typedef union tagMiepPortlogic56 7726 { 7727 7728 struct 7729 { 7730 UINT32 iatu2_type : 8 ; 7731 UINT32 iatu2_bar_num : 3 ; 7732 UINT32 Reserved_132 : 3 ; 7733 UINT32 iatu2_tc_match_en : 1 ; 7734 UINT32 iatu2_td_match_en : 1 ; 7735 UINT32 iatu2_attr_match_en : 1 ; 7736 UINT32 Reserved_131 : 1 ; 7737 UINT32 iatu2_at_match_en : 1 ; 7738 UINT32 iatu2_func_num_match_en : 1 ; 7739 UINT32 iatu2_virtual_func_num_match_en : 1 ; 7740 UINT32 message_code_match_en : 1 ; 7741 UINT32 Reserved_130 : 2 ; 7742 UINT32 iatu2_response_code : 2 ; 7743 UINT32 Reserved_129 : 1 ; 7744 UINT32 iatu2_fuzzy_type_match_mode : 1 ; 7745 UINT32 iatu2_cfg_shift_mode : 1 ; 7746 UINT32 iatu2_ivert_mode : 1 ; 7747 UINT32 iatu2_match_mode : 1 ; 7748 UINT32 iatu2_region_en : 1 ; 7749 } Bits; 7750 7751 7752 UINT32 UInt32; 7753 7754 } PCIE_MIEP_PORTLOGIC56_U; 7755 7756 7757 7758 7759 typedef union tagMiepPortlogic57 7760 { 7761 7762 struct 7763 { 7764 UINT32 iatu_start_low : 12 ; 7765 UINT32 iatu_start_high : 20 ; 7766 } Bits; 7767 7768 7769 UINT32 UInt32; 7770 7771 } PCIE_MIEP_PORTLOGIC57_U; 7772 7773 7774 7775 7776 typedef union tagMiepPortlogic59 7777 { 7778 7779 struct 7780 { 7781 UINT32 iatu_limit_low : 12 ; 7782 UINT32 iatu_limit_high : 20 ; 7783 } Bits; 7784 7785 7786 UINT32 UInt32; 7787 7788 } PCIE_MIEP_PORTLOGIC59_U; 7789 7790 7791 7792 7793 typedef union tagMiepPortlogic60 7794 { 7795 7796 struct 7797 { 7798 UINT32 xlated_addr_high : 12 ; 7799 UINT32 xlated_addr_low : 20 ; 7800 } Bits; 7801 7802 7803 UINT32 UInt32; 7804 7805 } PCIE_MIEP_PORTLOGIC60_U; 7806 7807 7808 7809 7810 typedef union tagMiepPortlogic62 7811 { 7812 7813 struct 7814 { 7815 UINT32 dma_wr_eng_en : 1 ; 7816 UINT32 dma_wr_ena : 31 ; 7817 } Bits; 7818 7819 7820 UINT32 UInt32; 7821 7822 } PCIE_MIEP_PORTLOGIC62_U; 7823 7824 7825 7826 7827 typedef union tagMiepPortlogic63 7828 { 7829 7830 struct 7831 { 7832 UINT32 wr_doorbell_num : 3 ; 7833 UINT32 Reserved_134 : 28 ; 7834 UINT32 dma_wr_dbell_stop : 1 ; 7835 } Bits; 7836 7837 7838 UINT32 UInt32; 7839 7840 } PCIE_MIEP_PORTLOGIC63_U; 7841 7842 7843 7844 7845 typedef union tagMiepPortlogic64 7846 { 7847 7848 struct 7849 { 7850 UINT32 dma_read_eng_en : 1 ; 7851 UINT32 Reserved_135 : 31 ; 7852 } Bits; 7853 7854 7855 UINT32 UInt32; 7856 7857 } PCIE_MIEP_PORTLOGIC64_U; 7858 7859 7860 7861 7862 typedef union tagMiepPortlogic65 7863 { 7864 7865 struct 7866 { 7867 UINT32 rd_doorbell_num : 3 ; 7868 UINT32 Reserved_137 : 28 ; 7869 UINT32 dma_rd_dbell_stop : 1 ; 7870 } Bits; 7871 7872 7873 UINT32 UInt32; 7874 7875 } PCIE_MIEP_PORTLOGIC65_U; 7876 7877 7878 7879 7880 typedef union tagMiepPortlogic66 7881 { 7882 7883 struct 7884 { 7885 UINT32 done_int_status : 8 ; 7886 UINT32 Reserved_139 : 8 ; 7887 UINT32 abort_int_status : 8 ; 7888 UINT32 Reserved_138 : 8 ; 7889 } Bits; 7890 7891 7892 UINT32 UInt32; 7893 7894 } PCIE_MIEP_PORTLOGIC66_U; 7895 7896 7897 7898 7899 typedef union tagMiepPortlogic67 7900 { 7901 7902 struct 7903 { 7904 UINT32 done_int_mask : 8 ; 7905 UINT32 Reserved_142 : 8 ; 7906 UINT32 abort_int_mask : 8 ; 7907 UINT32 Reserved_141 : 8 ; 7908 } Bits; 7909 7910 7911 UINT32 UInt32; 7912 7913 } PCIE_MIEP_PORTLOGIC67_U; 7914 7915 7916 7917 7918 typedef union tagMiepPortlogic68 7919 { 7920 7921 struct 7922 { 7923 UINT32 done_int_clr : 8 ; 7924 UINT32 Reserved_145 : 8 ; 7925 UINT32 abort_int_clr : 8 ; 7926 UINT32 Reserved_144 : 8 ; 7927 } Bits; 7928 7929 7930 UINT32 UInt32; 7931 7932 } PCIE_MIEP_PORTLOGIC68_U; 7933 7934 7935 7936 7937 typedef union tagMiepPortlogic69 7938 { 7939 7940 struct 7941 { 7942 UINT32 app_rd_err_det : 8 ; 7943 UINT32 Reserved_147 : 8 ; 7944 UINT32 ll_element_fetch_err_det : 8 ; 7945 UINT32 Reserved_146 : 8 ; 7946 } Bits; 7947 7948 7949 UINT32 UInt32; 7950 7951 } PCIE_MIEP_PORTLOGIC69_U; 7952 7953 7954 7955 7956 typedef union tagMiepPortlogic74 7957 { 7958 7959 struct 7960 { 7961 UINT32 dma_wr_c0_imwr_data : 16 ; 7962 UINT32 dma_wr_c1_imwr_data : 16 ; 7963 } Bits; 7964 7965 7966 UINT32 UInt32; 7967 7968 } PCIE_MIEP_PORTLOGIC74_U; 7969 7970 7971 7972 7973 typedef union tagMiepPortlogic75 7974 { 7975 7976 struct 7977 { 7978 UINT32 wr_ch_ll_remote_abort_int_en : 8 ; 7979 UINT32 Reserved_149 : 8 ; 7980 UINT32 wr_ch_ll_local_abort_int_en : 8 ; 7981 UINT32 Reserved_148 : 8 ; 7982 } Bits; 7983 7984 7985 UINT32 UInt32; 7986 7987 } PCIE_MIEP_PORTLOGIC75_U; 7988 7989 7990 7991 7992 typedef union tagMiepPortlogic76 7993 { 7994 7995 struct 7996 { 7997 UINT32 done_int_status : 8 ; 7998 UINT32 Reserved_152 : 8 ; 7999 UINT32 abort_int_status : 8 ; 8000 UINT32 Reserved_151 : 8 ; 8001 } Bits; 8002 8003 8004 UINT32 UInt32; 8005 8006 } PCIE_MIEP_PORTLOGIC76_U; 8007 8008 8009 8010 8011 typedef union tagMiepPortlogic77 8012 { 8013 8014 struct 8015 { 8016 UINT32 done_int_mask : 8 ; 8017 UINT32 Reserved_154 : 8 ; 8018 UINT32 abort_int_mask : 8 ; 8019 UINT32 dma_rd_int_mask : 8 ; 8020 } Bits; 8021 8022 8023 UINT32 UInt32; 8024 8025 } PCIE_MIEP_PORTLOGIC77_U; 8026 8027 8028 8029 8030 typedef union tagMiepPortlogic78 8031 { 8032 8033 struct 8034 { 8035 UINT32 done_int_clr : 8 ; 8036 UINT32 Reserved_156 : 8 ; 8037 UINT32 abort_int_clr : 8 ; 8038 UINT32 dma_rd_int_clr : 8 ; 8039 } Bits; 8040 8041 8042 UINT32 UInt32; 8043 8044 } PCIE_MIEP_PORTLOGIC78_U; 8045 8046 8047 8048 8049 typedef union tagMiepPortlogic79 8050 { 8051 8052 struct 8053 { 8054 UINT32 app_wr_err_det : 8 ; 8055 UINT32 Reserved_157 : 8 ; 8056 UINT32 link_list_fetch_err_det : 8 ; 8057 UINT32 dma_rd_err_low : 8 ; 8058 } Bits; 8059 8060 8061 UINT32 UInt32; 8062 8063 } PCIE_MIEP_PORTLOGIC79_U; 8064 8065 8066 8067 8068 typedef union tagMiepPortlogic80 8069 { 8070 8071 struct 8072 { 8073 UINT32 unspt_request : 8 ; 8074 UINT32 completer_abort : 8 ; 8075 UINT32 cpl_time_out : 8 ; 8076 UINT32 dma_rd_err_high : 8 ; 8077 } Bits; 8078 8079 8080 UINT32 UInt32; 8081 8082 } PCIE_MIEP_PORTLOGIC80_U; 8083 8084 8085 8086 8087 typedef union tagMiepPortlogic81 8088 { 8089 8090 struct 8091 { 8092 UINT32 remote_abort_int_en : 8 ; 8093 UINT32 Reserved_159 : 8 ; 8094 UINT32 local_abort_int_en : 8 ; 8095 UINT32 dma_rd_ll_err_ena : 8 ; 8096 } Bits; 8097 8098 8099 UINT32 UInt32; 8100 8101 } PCIE_MIEP_PORTLOGIC81_U; 8102 8103 8104 8105 8106 typedef union tagMiepPortlogic86 8107 { 8108 8109 struct 8110 { 8111 UINT32 channel_dir : 3 ; 8112 UINT32 Reserved_162 : 28 ; 8113 UINT32 dma_ch_con_idx : 1 ; 8114 } Bits; 8115 8116 8117 UINT32 UInt32; 8118 8119 } PCIE_MIEP_PORTLOGIC86_U; 8120 8121 8122 8123 8124 typedef union tagMiepPortlogic87 8125 { 8126 8127 struct 8128 { 8129 UINT32 cycle_bit : 1 ; 8130 UINT32 toggle_cycle_bit : 1 ; 8131 UINT32 load_link_pointer : 1 ; 8132 UINT32 local_int_en : 1 ; 8133 UINT32 remote_int_en : 1 ; 8134 UINT32 channel_status : 2 ; 8135 UINT32 Reserved_166 : 1 ; 8136 UINT32 consumer_cycle_state : 1 ; 8137 UINT32 linked_list_en : 1 ; 8138 UINT32 Reserved_165 : 2 ; 8139 UINT32 func_num_dma : 5 ; 8140 UINT32 Reserved_164 : 7 ; 8141 UINT32 no_snoop : 1 ; 8142 UINT32 ro : 1 ; 8143 UINT32 td : 1 ; 8144 UINT32 tc : 3 ; 8145 UINT32 dma_ch_ctrl : 2 ; 8146 } Bits; 8147 8148 8149 UINT32 UInt32; 8150 8151 } PCIE_MIEP_PORTLOGIC87_U; 8152 8153 8154 8155 8156 typedef union tagMiepPortlogic93 8157 { 8158 8159 struct 8160 { 8161 UINT32 Reserved_168 : 2 ; 8162 UINT32 dma_ll_ptr_low : 30 ; 8163 } Bits; 8164 8165 8166 UINT32 UInt32; 8167 8168 } PCIE_MIEP_PORTLOGIC93_U; 8169 8170 8171 8172 #define PCIE_IEP_BASE (0x00000000) 8173 8174 8175 8176 8177 #define PCIE_IEP_DEVICE_VENDOR_ID_REG (PCIE_IEP_BASE + 0x0) 8178 #define PCIE_IEP_PCISTS_PCICMD_REG (PCIE_IEP_BASE + 0x4) 8179 #define PCIE_IEP_CCR_RID_REG (PCIE_IEP_BASE + 0x8) 8180 #define PCIE_IEP_PBAR01_BASE_LOWER_REG (PCIE_IEP_BASE + 0x10) 8181 #define PCIE_IEP_PBAR01_BASE_UPPER_REG (PCIE_IEP_BASE + 0x14) 8182 #define PCIE_IEP_PBAR23_BASE_LOWER_REG (PCIE_IEP_BASE + 0x18) 8183 #define PCIE_IEP_PBAR23_BASE_UPPER_REG (PCIE_IEP_BASE + 0x1C) 8184 #define PCIE_IEP_PBAR45_BASE_LOWER_REG (PCIE_IEP_BASE + 0x20) 8185 #define PCIE_IEP_PBAR45_BASE_UPPER_REG (PCIE_IEP_BASE + 0x24) 8186 #define PCIE_IEP_CARDBUSCISPTR_REG (PCIE_IEP_BASE + 0x28) 8187 #define PCIE_IEP_SUBSYSTEMID_REG (PCIE_IEP_BASE + 0x2C) 8188 #define PCIE_IEP_EXPANSIONROM_BASE_ADDR_REG (PCIE_IEP_BASE + 0x30) 8189 #define PCIE_IEP_CAPPTR_REG (PCIE_IEP_BASE + 0x34) 8190 #define PCIE_IEP_INTERRUPT_REG (PCIE_IEP_BASE + 0x3C) 8191 #define PCIE_IEP_MSI_CAPABILITY_REGISTER_REG (PCIE_IEP_BASE + 0x50) 8192 #define PCIE_IEP_MSI_LOWER32_BITADDRESS_REG (PCIE_IEP_BASE + 0x54) 8193 #define PCIE_IEP_MSI_UPPER32_BIT_ADDRESS_REG (PCIE_IEP_BASE + 0x58) 8194 #define PCIE_IEP_MSI_DATA_REG (PCIE_IEP_BASE + 0x5C) 8195 #define PCIE_IEP_MSI_MASK_REG (PCIE_IEP_BASE + 0x60) 8196 #define PCIE_IEP_MSI_PENDING_REG (PCIE_IEP_BASE + 0x64) 8197 #define PCIE_IEP_PCIE_CAPABILITY_REGISTER_REG (PCIE_IEP_BASE + 0x70) 8198 #define PCIE_IEP_DEVICE_CAPABILITIES_REGISTER_REG (PCIE_IEP_BASE + 0x74) 8199 #define PCIE_IEP_DEVICE_STATUS_REGISTER_REG (PCIE_IEP_BASE + 0x78) 8200 #define PCIE_IEP_LINK_CAPABILITY_REG (PCIE_IEP_BASE + 0x7C) 8201 #define PCIE_IEP_LINK_CONTROL_STATUS_REG (PCIE_IEP_BASE + 0x80) 8202 #define PCIE_IEP_AER_CAP_HEADER_REG (PCIE_IEP_BASE + 0x100) 8203 #define PCIE_IEP_UC_ERROR_STATUS_REG (PCIE_IEP_BASE + 0x104) 8204 #define PCIE_IEP_UC_ERROR_MASK_REG (PCIE_IEP_BASE + 0x108) 8205 #define PCIE_IEP_UC_ERROR_SEVERITY_REG (PCIE_IEP_BASE + 0x10C) 8206 #define PCIE_IEP_C_ERROR_STATUS_REG (PCIE_IEP_BASE + 0x110) 8207 #define PCIE_IEP_C_ERROR_MASK_REG (PCIE_IEP_BASE + 0x114) 8208 #define PCIE_IEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG (PCIE_IEP_BASE + 0x118) 8209 #define PCIE_IEP_HEADER_LOG_REGISTERS_1_REG (PCIE_IEP_BASE + 0x11C) 8210 #define PCIE_IEP_HEADER_LOG_REGISTERS_2_REG (PCIE_IEP_BASE + 0x120) 8211 #define PCIE_IEP_HEADER_LOG_REGISTERS_3_REG (PCIE_IEP_BASE + 0x124) 8212 #define PCIE_IEP_HEADER_LOG_REGISTERS_4_REG (PCIE_IEP_BASE + 0x128) 8213 #define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_1_REG (PCIE_IEP_BASE + 0x130) 8214 #define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_2_REG (PCIE_IEP_BASE + 0x134) 8215 #define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_3_REG (PCIE_IEP_BASE + 0x138) 8216 #define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_4_REG (PCIE_IEP_BASE + 0x13C) 8217 #define PCIE_IEP_NTB_IEP_CFG_SPACE_LOWER_REG (PCIE_IEP_BASE + 0x700) 8218 #define PCIE_IEP_NTB_IEP_CFG_SPACE_UPPER_REG (PCIE_IEP_BASE + 0x704) 8219 #define PCIE_IEP_NTB_IEP_BAR01_CTRL_REG (PCIE_IEP_BASE + 0x708) 8220 #define PCIE_IEP_NTB_IEP_BAR23_CTRL_REG (PCIE_IEP_BASE + 0x70C) 8221 #define PCIE_IEP_NTB_IEP_BAR45_CTRL_REG (PCIE_IEP_BASE + 0x710) 8222 #define PCIE_IEP_MSI_CTRL_ADDRESS_LOWER_REG (PCIE_IEP_BASE + 0x714) 8223 #define PCIE_IEP_MSI_CTRL_ADDRESS_UPPER_REG (PCIE_IEP_BASE + 0x718) 8224 #define PCIE_IEP_MSI_CTRL_INT_EN_REG (PCIE_IEP_BASE + 0x71C) 8225 #define PCIE_IEP_MSI_CTRL_INT0_MASK_REG (PCIE_IEP_BASE + 0x720) 8226 #define PCIE_IEP_MSI_CTRL_INT_STATUS_REG (PCIE_IEP_BASE + 0x724) 8227 8228 8229 8230 typedef union tagIepDeviceVendorId 8231 { 8232 8233 struct 8234 { 8235 UINT32 Vendor_ID : 16 ; 8236 UINT32 Device_ID : 16 ; 8237 } Bits; 8238 8239 8240 UINT32 UInt32; 8241 8242 } PCIE_IEP_DEVICE_VENDOR_ID_U; 8243 8244 8245 8246 8247 typedef union tagIepPcistsPcicmd 8248 { 8249 8250 struct 8251 { 8252 UINT32 IO_Space_Enable : 1 ; 8253 UINT32 Memory_Space_Enable : 1 ; 8254 UINT32 Bus_Master_Enable : 1 ; 8255 UINT32 SpecialCycleEnable : 1 ; 8256 UINT32 Memory_Write_and_Invalidate : 1 ; 8257 UINT32 VGA_palette_snoop_Enable : 1 ; 8258 UINT32 Parity_Error_Response : 1 ; 8259 UINT32 IDSEL_Stepping_WaitCycle_Control : 1 ; 8260 UINT32 SERR_Enable : 1 ; 8261 UINT32 FastBack_to_BackEnable : 1 ; 8262 UINT32 Interrupt_Disable : 1 ; 8263 UINT32 Reserved_2 : 5 ; 8264 UINT32 Reserved_1 : 3 ; 8265 UINT32 INTx_Status : 1 ; 8266 UINT32 CapabilitiesList : 1 ; 8267 UINT32 pcibus66MHzcapable : 1 ; 8268 UINT32 Reserved_0 : 1 ; 8269 UINT32 FastBack_to_Back : 1 ; 8270 UINT32 MasterDataParityError : 1 ; 8271 UINT32 DEVSEL_Timing : 2 ; 8272 UINT32 Signaled_Target_Abort : 1 ; 8273 UINT32 Received_Target_Abort : 1 ; 8274 UINT32 Received_Master_Abort : 1 ; 8275 UINT32 Signaled_System_Error : 1 ; 8276 UINT32 Detected_Parity_Error : 1 ; 8277 } Bits; 8278 8279 8280 UINT32 UInt32; 8281 8282 } PCIE_IEP_PCISTS_PCICMD_U; 8283 8284 8285 8286 8287 typedef union tagIepCcrRid 8288 { 8289 8290 struct 8291 { 8292 UINT32 Revision_Identification : 8 ; 8293 UINT32 Reserved_3 : 8 ; 8294 UINT32 Sub_Class : 8 ; 8295 UINT32 BaseClass : 8 ; 8296 } Bits; 8297 8298 8299 UINT32 UInt32; 8300 8301 } PCIE_IEP_CCR_RID_U; 8302 8303 8304 8305 8306 typedef union tagIepPbar01BaseLower 8307 { 8308 8309 struct 8310 { 8311 UINT32 BAR01_Space_Inicator : 1 ; 8312 UINT32 BAR01_Type : 2 ; 8313 UINT32 BAR01_Prefetchable : 1 ; 8314 UINT32 Reserved_4 : 12 ; 8315 UINT32 pbar01_lower : 16 ; 8316 } Bits; 8317 8318 8319 UINT32 UInt32; 8320 8321 } PCIE_IEP_PBAR01_BASE_LOWER_U; 8322 8323 8324 8325 8326 typedef union tagIepPbar23BaseLower 8327 { 8328 8329 struct 8330 { 8331 UINT32 pbar23_space_inicator : 1 ; 8332 UINT32 pbar23_type : 2 ; 8333 UINT32 pbar23_prefetchable : 1 ; 8334 UINT32 Reserved_6 : 8 ; 8335 UINT32 pbar23_lower : 20 ; 8336 } Bits; 8337 8338 8339 UINT32 UInt32; 8340 8341 } PCIE_IEP_PBAR23_BASE_LOWER_U; 8342 8343 8344 8345 8346 typedef union tagIepPbar45BaseLower 8347 { 8348 8349 struct 8350 { 8351 UINT32 pbar45_space_inicator : 1 ; 8352 UINT32 pbar45_type : 2 ; 8353 UINT32 pbar45_prefetchable : 1 ; 8354 UINT32 Reserved_7 : 8 ; 8355 UINT32 pbar45_lower : 20 ; 8356 } Bits; 8357 8358 8359 UINT32 UInt32; 8360 8361 } PCIE_IEP_PBAR45_BASE_LOWER_U; 8362 8363 8364 8365 8366 typedef union tagIepSubsystemid 8367 { 8368 8369 struct 8370 { 8371 UINT32 SubsystemID : 16 ; 8372 UINT32 SubsystemVendorID : 16 ; 8373 } Bits; 8374 8375 8376 UINT32 UInt32; 8377 8378 } PCIE_IEP_SubSystemId_U; 8379 8380 8381 8382 8383 typedef union tagIepCapptr 8384 { 8385 8386 struct 8387 { 8388 UINT32 CapPtr : 8 ; 8389 UINT32 Reserved_10 : 24 ; 8390 } Bits; 8391 8392 8393 UINT32 UInt32; 8394 8395 } PCIE_IEP_CapPtr_U; 8396 8397 8398 8399 8400 typedef union tagIepInterrupt 8401 { 8402 8403 struct 8404 { 8405 UINT32 Interrupt_Line : 8 ; 8406 UINT32 Interrupt_Pin : 8 ; 8407 UINT32 Min_Grant : 8 ; 8408 UINT32 Max_Latency : 8 ; 8409 } Bits; 8410 8411 8412 UINT32 UInt32; 8413 8414 } PCIE_IEP_Interrupt_U; 8415 8416 8417 8418 8419 typedef union tagIepMsiCapabilityRegister 8420 { 8421 8422 struct 8423 { 8424 UINT32 CapabilityID : 8 ; 8425 UINT32 Next_Capability_Pointer : 8 ; 8426 UINT32 MSI_Enabled : 1 ; 8427 UINT32 Multiple_Message_Capable : 3 ; 8428 UINT32 Multiple_Message_Enabled : 3 ; 8429 UINT32 MSI_64_EN : 1 ; 8430 UINT32 PVM_EN : 1 ; 8431 UINT32 Message_Control_Register : 7 ; 8432 } Bits; 8433 8434 8435 UINT32 UInt32; 8436 8437 } PCIE_IEP_MSI_Capability_Register_U; 8438 8439 8440 8441 8442 typedef union tagIepMsiLower32Bitaddress 8443 { 8444 8445 struct 8446 { 8447 UINT32 Reserved_13 : 2 ; 8448 UINT32 Lower32_bitAddress : 30 ; 8449 } Bits; 8450 8451 8452 UINT32 UInt32; 8453 8454 } PCIE_IEP_MSI_Lower32_bitAddress_U; 8455 8456 8457 8458 8459 typedef union tagIepMsiData 8460 { 8461 8462 struct 8463 { 8464 UINT32 MSI_Data : 16 ; 8465 UINT32 Reserved_14 : 16 ; 8466 } Bits; 8467 8468 8469 UINT32 UInt32; 8470 8471 } PCIE_IEP_MSI_Data_U; 8472 8473 8474 8475 8476 typedef union tagIepMsiMask 8477 { 8478 8479 struct 8480 { 8481 UINT32 MsiMask : 1 ; 8482 UINT32 Reserved_15 : 31 ; 8483 } Bits; 8484 8485 8486 UINT32 UInt32; 8487 8488 } PCIE_IEP_MSI_MASK_U; 8489 8490 8491 8492 8493 typedef union tagIepMsiPending 8494 { 8495 8496 struct 8497 { 8498 UINT32 MsiPending : 1 ; 8499 UINT32 Reserved_16 : 31 ; 8500 } Bits; 8501 8502 8503 UINT32 UInt32; 8504 8505 } PCIE_IEP_MSI_Pending_U; 8506 8507 8508 8509 8510 typedef union tagIepPcieCapabilityRegister 8511 { 8512 8513 struct 8514 { 8515 UINT32 Capability_ID : 8 ; 8516 UINT32 Next_Capability_Pointer : 8 ; 8517 UINT32 PCIE_Capability_Version : 4 ; 8518 UINT32 Device_Port_Type : 4 ; 8519 UINT32 Slot_Implemented : 1 ; 8520 UINT32 Interrupt_Message_Number : 5 ; 8521 UINT32 Reserved_17 : 2 ; 8522 } Bits; 8523 8524 8525 UINT32 UInt32; 8526 8527 } PCIE_IEP_PCIE_Capability_Register_U; 8528 8529 8530 8531 8532 typedef union tagIepDeviceCapabilitiesRegister 8533 { 8534 8535 struct 8536 { 8537 UINT32 Max_Payload_Size_Supported : 3 ; 8538 UINT32 Phantom_Function_Supported : 2 ; 8539 UINT32 Extended_TagField_Supported : 1 ; 8540 UINT32 Endpoint_L0sAcceptable_Latency : 3 ; 8541 UINT32 Endpoint_L1Acceptable_Latency : 3 ; 8542 UINT32 Undefined : 3 ; 8543 UINT32 Reserved_20 : 3 ; 8544 UINT32 Captured_Slot_Power_Limit_Value : 8 ; 8545 UINT32 Captured_Slot_Power_Limit_Scale : 2 ; 8546 UINT32 Function_Level_Reset : 1 ; 8547 UINT32 Reserved_19 : 3 ; 8548 } Bits; 8549 8550 8551 UINT32 UInt32; 8552 8553 } PCIE_IEP_Device_Capabilities_Register_U; 8554 8555 8556 8557 8558 typedef union tagIepDeviceStatusRegister 8559 { 8560 8561 struct 8562 { 8563 UINT32 Correctable_Error_Reporting_Enable : 1 ; 8564 UINT32 Non_Fatal_Error_Reporting_Enable : 1 ; 8565 UINT32 Fatal_Error_Reporting_Enable : 1 ; 8566 UINT32 UREnable : 1 ; 8567 UINT32 Enable_Relaxed_Ordering : 1 ; 8568 UINT32 Max_Payload_Size : 3 ; 8569 UINT32 Extended_TagFieldEnable : 1 ; 8570 UINT32 Phantom_Function_Enable : 1 ; 8571 UINT32 AUXPowerPMEnable : 1 ; 8572 UINT32 EnableNoSnoop : 1 ; 8573 UINT32 Max_Read_Request_Size : 3 ; 8574 UINT32 Reserved_22 : 1 ; 8575 UINT32 CorrectableErrorDetected : 1 ; 8576 UINT32 Non_FatalErrordetected : 1 ; 8577 UINT32 FatalErrorDetected : 1 ; 8578 UINT32 UnsupportedRequestDetected : 1 ; 8579 UINT32 AuxPowerDetected : 1 ; 8580 UINT32 TransactionPending : 1 ; 8581 UINT32 Reserved_21 : 10 ; 8582 } Bits; 8583 8584 8585 UINT32 UInt32; 8586 8587 } PCIE_IEP_Device_Status_Register_U; 8588 8589 8590 8591 8592 typedef union tagIepLinkCapability 8593 { 8594 8595 struct 8596 { 8597 UINT32 Max_Link_Speed : 4 ; 8598 UINT32 Max_Link_Width : 6 ; 8599 UINT32 Active_State_Power_Management : 2 ; 8600 UINT32 L0s_ExitLatency : 3 ; 8601 UINT32 L1_Exit_Latency : 3 ; 8602 UINT32 Clock_Power_Management : 1 ; 8603 UINT32 Surprise_Down_Error_Report_Cap : 1 ; 8604 UINT32 Data_Link_Layer_Active_Report_Cap : 1 ; 8605 UINT32 Link_Bandwidth_Noti_Cap : 1 ; 8606 UINT32 ASPM_Option_Compliance : 1 ; 8607 UINT32 Reserved_23 : 1 ; 8608 UINT32 Port_Number : 8 ; 8609 } Bits; 8610 8611 8612 UINT32 UInt32; 8613 8614 } PCIE_IEP_Link_Capability_U; 8615 8616 8617 8618 8619 typedef union tagIepLinkControlStatus 8620 { 8621 8622 struct 8623 { 8624 UINT32 Active_State_Power_Management : 2 ; 8625 UINT32 Reserved_26 : 1 ; 8626 UINT32 RCB : 1 ; 8627 UINT32 Link_Disable : 1 ; 8628 UINT32 Retrain_Link : 1 ; 8629 UINT32 Common_Clock_Config : 1 ; 8630 UINT32 Extended_Sync : 1 ; 8631 UINT32 Enable_Clock_Pwr_Management : 1 ; 8632 UINT32 Hw_Auto_Width_Disable : 1 ; 8633 UINT32 Link_Bandwidth_Management_Int_En : 1 ; 8634 UINT32 Link_Auto_Bandwidth_Int_En : 1 ; 8635 UINT32 Reserved_25 : 4 ; 8636 UINT32 current_link_speed : 4 ; 8637 UINT32 negotiated_link_width : 6 ; 8638 UINT32 Reserved_24 : 1 ; 8639 UINT32 link_training : 1 ; 8640 UINT32 slot_clock_config : 1 ; 8641 UINT32 data_link_layer_active : 1 ; 8642 UINT32 link_bandwidth_management_status : 1 ; 8643 UINT32 link_auto_bandwidth_status : 1 ; 8644 } Bits; 8645 8646 8647 UINT32 UInt32; 8648 8649 } PCIE_IEP_Link_Control_Status_U; 8650 8651 8652 8653 8654 typedef union tagIepAerCapHeader 8655 { 8656 8657 struct 8658 { 8659 UINT32 PCIE_Extended_Capability_ID : 16 ; 8660 UINT32 Capability_Version : 4 ; 8661 UINT32 Next_Capability_Offset : 12 ; 8662 } Bits; 8663 8664 8665 UINT32 UInt32; 8666 8667 } PCIE_IEP_AER_Cap_header_U; 8668 8669 8670 8671 8672 typedef union tagIepUcErrorStatus 8673 { 8674 8675 struct 8676 { 8677 UINT32 Reserved_31 : 1 ; 8678 UINT32 Reserved_30 : 3 ; 8679 UINT32 DataLinkProtocolErrorStatus : 1 ; 8680 UINT32 SurpriseDownErrorStatus : 1 ; 8681 UINT32 Reserved_29 : 6 ; 8682 UINT32 PoisonedTLPStatus : 1 ; 8683 UINT32 FlowControlProtocolErrorStatus : 1 ; 8684 UINT32 CompletionTimeoutStatus : 1 ; 8685 UINT32 CompleterAbortStatus : 1 ; 8686 UINT32 UnexpectedCompletionStatus : 1 ; 8687 UINT32 ReceiverOverflowStatus : 1 ; 8688 UINT32 MalformedTLPStatus : 1 ; 8689 UINT32 ECRCErrorStatus : 1 ; 8690 UINT32 UnsupportedRequestErrorStatus : 1 ; 8691 UINT32 Reserved_28 : 11 ; 8692 } Bits; 8693 8694 8695 UINT32 UInt32; 8696 8697 } PCIE_IEP_UC_Error_Status_U; 8698 8699 8700 8701 8702 typedef union tagIepUcErrorMask 8703 { 8704 8705 struct 8706 { 8707 UINT32 Reserved_35 : 1 ; 8708 UINT32 Reserved_34 : 3 ; 8709 UINT32 DataLinkProtocolErrorMask : 1 ; 8710 UINT32 SurpriseDownErrorMask : 1 ; 8711 UINT32 Reserved_33 : 6 ; 8712 UINT32 PoisonedTLPMask : 1 ; 8713 UINT32 FlowControlProtocolErrorMask : 1 ; 8714 UINT32 CompletionTimeoutMask : 1 ; 8715 UINT32 CompleterAbortMask : 1 ; 8716 UINT32 UnexpectedCompletionMask : 1 ; 8717 UINT32 ReceiverOverflowMask : 1 ; 8718 UINT32 MalformedTLPMask : 1 ; 8719 UINT32 ECRCErrorMask : 1 ; 8720 UINT32 UnsupportedRequestErrorMask : 1 ; 8721 UINT32 Reserved_32 : 11 ; 8722 } Bits; 8723 8724 8725 UINT32 UInt32; 8726 8727 } PCIE_IEP_UC_Error_Mask_U; 8728 8729 8730 8731 8732 typedef union tagIepUcErrorSeverity 8733 { 8734 8735 struct 8736 { 8737 UINT32 Reserved_39 : 1 ; 8738 UINT32 Reserved_38 : 3 ; 8739 UINT32 DataLinkProtocolErrorSeverity : 1 ; 8740 UINT32 SurpriseDownErrorSeverity : 1 ; 8741 UINT32 Reserved_37 : 6 ; 8742 UINT32 PoisonedTLPSeverity : 1 ; 8743 UINT32 FlowControlProtocolErrorSeverity : 1 ; 8744 UINT32 CompletionTimeoutSeverity : 1 ; 8745 UINT32 CompleterAbortSeverity : 1 ; 8746 UINT32 UnexpectedCompletionSeverity : 1 ; 8747 UINT32 ReceiverOverflowSeverity : 1 ; 8748 UINT32 MalformedTLPSeverity : 1 ; 8749 UINT32 ECRCErrorSeverity : 1 ; 8750 UINT32 UnsupportedRequestErrorSeverity : 1 ; 8751 UINT32 Reserved_36 : 11 ; 8752 } Bits; 8753 8754 8755 UINT32 UInt32; 8756 8757 } PCIE_IEP_UC_Error_Severity_U; 8758 8759 8760 8761 8762 typedef union tagIepCErrorStatus 8763 { 8764 8765 struct 8766 { 8767 UINT32 Receiver_Error_Status : 1 ; 8768 UINT32 Reserved_42 : 5 ; 8769 UINT32 Bad_TLP_Status : 1 ; 8770 UINT32 Bad_DLLP_Status : 1 ; 8771 UINT32 REPLAY_NUM_Rollover_Status : 1 ; 8772 UINT32 Reserved_41 : 3 ; 8773 UINT32 Replay_Timer_Timeout_Status : 1 ; 8774 UINT32 Advisory_Non_Fatal_Error_Status : 1 ; 8775 UINT32 Reserved_40 : 18 ; 8776 } Bits; 8777 8778 8779 UINT32 UInt32; 8780 8781 } PCIE_IEP_C_Error_Status_U; 8782 8783 8784 8785 8786 typedef union tagIepCErrorMask 8787 { 8788 8789 struct 8790 { 8791 UINT32 Receiver_Error_Mask : 1 ; 8792 UINT32 Reserved_45 : 5 ; 8793 UINT32 Bad_TLP_Mask : 1 ; 8794 UINT32 Bad_DLLP_Mask : 1 ; 8795 UINT32 REPLAY_NUMRollover_Mask : 1 ; 8796 UINT32 Reserved_44 : 3 ; 8797 UINT32 Replay_Timer_Timeout_Mask : 1 ; 8798 UINT32 Advisory_Non_Fatal_Error_Mask : 1 ; 8799 UINT32 Reserved_43 : 18 ; 8800 } Bits; 8801 8802 8803 UINT32 UInt32; 8804 8805 } PCIE_IEP_C_Error_Mask_U; 8806 8807 8808 8809 8810 typedef union tagIepAdvancedErrorCapabilitiesAndControl 8811 { 8812 8813 struct 8814 { 8815 UINT32 First_Error_Pointer : 5 ; 8816 UINT32 ECRC_Generation_Capability : 1 ; 8817 UINT32 ECRC_Generation_Enable : 1 ; 8818 UINT32 ECRC_Check_Capable : 1 ; 8819 UINT32 ECRC_Check_Enable : 1 ; 8820 UINT32 Reserved_47 : 2 ; 8821 UINT32 TLP_Prefix_Log_Present : 1 ; 8822 UINT32 Reserved_46 : 20 ; 8823 } Bits; 8824 8825 8826 UINT32 UInt32; 8827 8828 } PCIE_IEP_Advanced_Error_Capabilities_and_Control_U; 8829 8830 8831 8832 8833 typedef union tagIepNtbIepBar01Ctrl 8834 { 8835 8836 struct 8837 { 8838 UINT32 bar01_type : 5 ; 8839 UINT32 bar01_tc : 3 ; 8840 UINT32 bar01_td : 1 ; 8841 UINT32 bar01_attr : 2 ; 8842 UINT32 Reserved_51 : 5 ; 8843 UINT32 bar01_at : 2 ; 8844 UINT32 bar01_match_en : 1 ; 8845 UINT32 Reserved_50 : 13 ; 8846 } Bits; 8847 8848 8849 UINT32 UInt32; 8850 8851 } PCIE_IEP_NTB_IEP_BAR01_CTRL_U; 8852 8853 8854 8855 8856 typedef union tagIepNtbIepBar23Ctrl 8857 { 8858 8859 struct 8860 { 8861 UINT32 bar23_type : 5 ; 8862 UINT32 bar23_tc : 3 ; 8863 UINT32 bar23_td : 1 ; 8864 UINT32 bar23_attr : 2 ; 8865 UINT32 Reserved_53 : 5 ; 8866 UINT32 bar23_at : 2 ; 8867 UINT32 bar23_match_en : 1 ; 8868 UINT32 Reserved_52 : 13 ; 8869 } Bits; 8870 8871 8872 UINT32 UInt32; 8873 8874 } PCIE_IEP_NTB_IEP_BAR23_CTRL_U; 8875 8876 8877 8878 8879 typedef union tagIepNtbIepBar45Ctrl 8880 { 8881 8882 struct 8883 { 8884 UINT32 bar45_type : 5 ; 8885 UINT32 bar45_tc : 3 ; 8886 UINT32 bar45_td : 1 ; 8887 UINT32 bar45_attr : 2 ; 8888 UINT32 Reserved_55 : 5 ; 8889 UINT32 bar45_at : 2 ; 8890 UINT32 bar45_match_en : 1 ; 8891 UINT32 Reserved_54 : 13 ; 8892 } Bits; 8893 8894 8895 UINT32 UInt32; 8896 8897 } PCIE_IEP_NTB_IEP_BAR45_CTRL_U; 8898 8899 8900 8901 8902 typedef union tagIepMsiCtrlIntEn 8903 { 8904 8905 struct 8906 { 8907 UINT32 msi_int_en : 1 ; 8908 UINT32 Reserved_56 : 31 ; 8909 } Bits; 8910 8911 8912 UINT32 UInt32; 8913 8914 } PCIE_IEP_MSI_CTRL_INT_EN_U; 8915 8916 8917 8918 8919 typedef union tagIepMsiCtrlInt0Mask 8920 { 8921 8922 struct 8923 { 8924 UINT32 msi_int_mask : 1 ; 8925 UINT32 Reserved_57 : 31 ; 8926 } Bits; 8927 8928 8929 UINT32 UInt32; 8930 8931 } PCIE_IEP_MSI_CTRL_INT0_MASK_U; 8932 8933 8934 8935 8936 typedef union tagIepMsiCtrlIntStatus 8937 { 8938 8939 struct 8940 { 8941 UINT32 msi_int : 1 ; 8942 UINT32 Reserved_58 : 31 ; 8943 } Bits; 8944 8945 8946 UINT32 UInt32; 8947 8948 } PCIE_IEP_MSI_CTRL_INT_STATUS_U; 8949 8950 8951 #define PCI_SYS_BASE (0x00000000) 8952 8953 8954 8955 8956 #define PCIE_CTRL_0_REG (PCI_SYS_BASE + 0xF8) 8957 #define PCIE_CTRL_1_REG (PCI_SYS_BASE + 0xFC) 8958 #define PCIE_CTRL_2_REG (PCI_SYS_BASE + 0x100) 8959 #define PCIE_CTRL_3_REG (PCI_SYS_BASE + 0x104) 8960 #define PCIE_CTRL_4_REG (PCI_SYS_BASE + 0x108) 8961 #define PCIE_CTRL_5_REG (PCI_SYS_BASE + 0x10C) 8962 #define PCIE_CTRL_6_REG (PCI_SYS_BASE + 0x110) 8963 #define PCIE_CTRL_7_REG (PCI_SYS_BASE + 0x114) 8964 #define PCIE_CTRL_9_REG (PCI_SYS_BASE + 0x11C) 8965 #define PCIE_CTRL_10_REG (PCI_SYS_BASE + 0x120) 8966 #define PCIE_CTRL_11_REG (PCI_SYS_BASE + 0x124) 8967 #define PCIE_SYS_CTRL12_REG (PCI_SYS_BASE + 0x0) 8968 #define PCIE_SYS_CTRL13_REG (PCI_SYS_BASE + 0x4) 8969 #define PCIE_SYS_CTRL14_REG (PCI_SYS_BASE + 0x8) 8970 #define PCIE_SYS_CTRL15_REG (PCI_SYS_BASE + 0xC) 8971 #define PCIE_SYS_CTRL16_REG (PCI_SYS_BASE + 0x10) 8972 #define PCIE_SYS_CTRL17_REG (PCI_SYS_BASE + 0x14) 8973 #define PCIE_SYS_CTRL18_REG (PCI_SYS_BASE + 0x18) 8974 #define PCIE_SYS_CTRL19_REG (PCI_SYS_BASE + 0x1C) 8975 #define PCIE_SYS_CTRL20_REG (PCI_SYS_BASE + 0x20) 8976 #define PCIE_RD_TAB_SEL BIT31 8977 #define PCIE_RD_TAB_EN BIT30 8978 #define PCIE_SYS_CTRL21_REG (PCI_SYS_BASE + 0x24) 8979 #define PCIE_SYS_CTRL22_REG (PCI_SYS_BASE + 0x28) 8980 #define PCIE_SYS_CTRL23_REG (PCI_SYS_BASE + 0x2C) 8981 #define PCIE_SYS_CTRL24_REG (PCI_SYS_BASE + 0x1b4) 8982 #define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4) 8983 #define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8) 8984 #define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274) 8985 #define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30) 8986 #define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34) 8987 #define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38) 8988 #define PCIE_SYS_STATE8_REG (PCI_SYS_BASE + 0x3C) 8989 #define PCIE_SYS_STATE9_REG (PCI_SYS_BASE + 0x40) 8990 #define PCIE_SYS_STATE10_REG (PCI_SYS_BASE + 0x44) 8991 #define PCIE_SYS_STATE11_REG (PCI_SYS_BASE + 0x48) 8992 #define PCIE_SYS_STATE12_REG (PCI_SYS_BASE + 0x4C) 8993 #define PCIE_SYS_STATE13_REG (PCI_SYS_BASE + 0x50) 8994 #define PCIE_SYS_STATE14_REG (PCI_SYS_BASE + 0x54) 8995 #define PCIE_SYS_STATE15_REG (PCI_SYS_BASE + 0x58) 8996 #define PCIE_SYS_STATE16_REG (PCI_SYS_BASE + 0x5C) 8997 #define PCIE_SYS_STATE17_REG (PCI_SYS_BASE + 0x60) 8998 #define PCIE_SYS_STATE18_REG (PCI_SYS_BASE + 0x64) 8999 #define PCIE_SYS_STATE19_REG (PCI_SYS_BASE + 0x68) 9000 #define PCIE_SYS_STATE20_REG (PCI_SYS_BASE + 0x6C) 9001 #define PCIE_SYS_STATE21_REG (PCI_SYS_BASE + 0x70) 9002 #define PCIE_SYS_STATE22_REG (PCI_SYS_BASE + 0x74) 9003 #define PCIE_SYS_STATE23_REG (PCI_SYS_BASE + 0x78) 9004 #define PCIE_SYS_STATE24_REG (PCI_SYS_BASE + 0x7C) 9005 #define PCIE_SYS_STATE25_REG (PCI_SYS_BASE + 0x80) 9006 #define PCIE_SYS_STATE26_REG (PCI_SYS_BASE + 0x84) 9007 #define PCIE_SYS_STATE27_REG (PCI_SYS_BASE + 0x88) 9008 #define PCIE_SYS_STATE28_REG (PCI_SYS_BASE + 0x8C) 9009 #define PCIE_SYS_STATE29_REG (PCI_SYS_BASE + 0x90) 9010 #define PCIE_SYS_STATE30_REG (PCI_SYS_BASE + 0x94) 9011 #define PCIE_SYS_STATE31_REG (PCI_SYS_BASE + 0x98) 9012 #define PCIE_SYS_STATE32_REG (PCI_SYS_BASE + 0x9C) 9013 #define PCIE_SYS_STATE33_REG (PCI_SYS_BASE + 0xA0) 9014 #define PCIE_SYS_STATE34_REG (PCI_SYS_BASE + 0xA4) 9015 #define PCIE_SYS_STATE35_REG (PCI_SYS_BASE + 0xA8) 9016 #define PCIE_SYS_STATE36_REG (PCI_SYS_BASE + 0xAC) 9017 #define PCIE_SYS_STATE37_REG (PCI_SYS_BASE + 0xB0) 9018 #define PCIE_SYS_STATE38_REG (PCI_SYS_BASE + 0xB4) 9019 #define PCIE_SYS_STATE39_REG (PCI_SYS_BASE + 0xB8) 9020 #define PCIE_SYS_STATE40_REG (PCI_SYS_BASE + 0xBC) 9021 #define PCIE_SYS_STATE41_REG (PCI_SYS_BASE + 0xC0) 9022 #define PCIE_SYS_STATE42_REG (PCI_SYS_BASE + 0xC4) 9023 #define PCIE_SYS_STATE43_REG (PCI_SYS_BASE + 0xC8) 9024 #define PCIE_SYS_STATE44_REG (PCI_SYS_BASE + 0xCC) 9025 #define PCIE_SYS_STATE45_REG (PCI_SYS_BASE + 0xD0) 9026 #define PCIE_SYS_STATE46_REG (PCI_SYS_BASE + 0xD4) 9027 #define PCIE_SYS_STATE47_REG (PCI_SYS_BASE + 0xD8) 9028 #define PCIE_SYS_STATE48_REG (PCI_SYS_BASE + 0xDC) 9029 #define PCIE_SYS_STATE49_REG (PCI_SYS_BASE + 0xE0) 9030 #define PCIE_SYS_STATE50_REG (PCI_SYS_BASE + 0xE4) 9031 #define PCIE_SYS_STATE51_REG (PCI_SYS_BASE + 0xE8) 9032 #define PCIE_SYS_STATE52_REG (PCI_SYS_BASE + 0xEC) 9033 #define PCIE_SYS_STATE53_REG (PCI_SYS_BASE + 0xF0) 9034 #define PCIE_SYS_STATE54_REG (PCI_SYS_BASE + 0xF4) 9035 #define PCIE_STAT_0_REG (PCI_SYS_BASE + 0x0) 9036 #define PCIE_STAT_1_REG (PCI_SYS_BASE + 0x0) 9037 #define PCIE_STAT_2_REG (PCI_SYS_BASE + 0x0) 9038 #define PCIE_STAT_3_REG (PCI_SYS_BASE + 0x0) 9039 #define PCIE_STAT_4_REG (PCI_SYS_BASE + 0x0) 9040 9041 9042 9043 typedef union tagPcieCtrl0 9044 { 9045 9046 struct 9047 { 9048 UINT32 pcie2_slv_awmisc_info : 22 ; 9049 UINT32 pcie2_slv_resp_err_map : 6 ; 9050 UINT32 pcie2_slv_device_type : 4 ; 9051 } Bits; 9052 9053 9054 UINT32 UInt32; 9055 9056 } PCIE_CTRL_0_U; 9057 9058 9059 9060 9061 typedef union tagPcieCtrl1 9062 { 9063 9064 struct 9065 { 9066 UINT32 pcie2_slv_armisc_info : 22 ; 9067 UINT32 pcie2_common_clocks : 1 ; 9068 UINT32 pcie2_app_clk_req_n : 1 ; 9069 UINT32 pcie2_ven_msg_code : 8 ; 9070 } Bits; 9071 9072 9073 UINT32 UInt32; 9074 9075 } PCIE_CTRL_1_U; 9076 9077 9078 9079 9080 typedef union tagPcieCtrl2 9081 { 9082 9083 struct 9084 { 9085 UINT32 pcie2_mstr_bmisc_info : 14 ; 9086 UINT32 pcie2_mstr_rmisc_info : 12 ; 9087 UINT32 pcie2_ven_msi_req : 1 ; 9088 UINT32 pcie2_ven_msi_vector : 5 ; 9089 } Bits; 9090 9091 9092 UINT32 UInt32; 9093 9094 } PCIE_CTRL_2_U; 9095 9096 9097 9098 9099 typedef union tagPcieCtrl3 9100 { 9101 9102 struct 9103 { 9104 UINT32 pcie2_ven_msg_req : 1 ; 9105 UINT32 pcie2_ven_msg_fmt : 2 ; 9106 UINT32 pcie2_ven_msg_type : 5 ; 9107 UINT32 pcie2_ven_msg_td : 1 ; 9108 UINT32 pcie2_ven_msg_ep : 1 ; 9109 UINT32 pcie2_ven_msg_attr : 2 ; 9110 UINT32 pcie2_ven_msg_len : 10 ; 9111 UINT32 pcie2_ven_msg_tag : 8 ; 9112 UINT32 pcie_mstr_rresp_int_enable : 1 ; 9113 UINT32 pcie_mstr_bresp_int_enable : 1 ; 9114 } Bits; 9115 9116 9117 UINT32 UInt32; 9118 9119 } PCIE_CTRL_3_U; 9120 9121 9122 9123 9124 typedef union tagPcieCtrl7 9125 { 9126 9127 struct 9128 { 9129 UINT32 pcie2_app_init_rst : 1 ; 9130 UINT32 pcie2_app_req_entr_l1 : 1 ; 9131 UINT32 pcie2_app_ready_entr_l23 : 1 ; 9132 UINT32 pcie2_app_req_exit_l1 : 1 ; 9133 UINT32 pcie2_app_req_retry_en : 1 ; 9134 UINT32 pcie2_sys_int : 1 ; 9135 UINT32 pcie2_outband_pwrup_cmd : 1 ; 9136 UINT32 pcie2_app_unlock_msg : 1 ; 9137 UINT32 pcie2_apps_pm_xmt_turnoff : 1 ; 9138 UINT32 pcie2_apps_pm_xmt_pme : 1 ; 9139 UINT32 pcie2_sys_aux_pwr_det : 1 ; 9140 UINT32 pcie2_app_ltssm_enable : 1 ; 9141 UINT32 pcie2_cfg_pwr_ctrler_ctrl_pol : 1 ; 9142 UINT32 Reserved_7 : 1 ; 9143 UINT32 pcie2_sys_mrl_sensor_state : 1 ; 9144 UINT32 pcie2_sys_pwr_fault_det : 1 ; 9145 UINT32 pcie2_sys_mrl_sensor_chged : 1 ; 9146 UINT32 Reserved_6 : 1 ; 9147 UINT32 pcie2_sys_cmd_cpled_int : 1 ; 9148 UINT32 pcie2_sys_eml_interlock_engaged : 1 ; 9149 UINT32 pcie2_cfg_l1_clk_removal_en : 1 ; 9150 UINT32 pcie0_int_ctrl : 8 ; 9151 UINT32 pcie_linkdown_auto_rstn_enable : 1 ; 9152 UINT32 pcie_err_bresp_enable : 1 ; 9153 UINT32 pcie_err_rresp_enable : 1 ; 9154 } Bits; 9155 9156 9157 UINT32 UInt32; 9158 9159 } PCIE_CTRL_7_U; 9160 9161 9162 9163 9164 typedef union tagPcieCtrl9 9165 { 9166 9167 struct 9168 { 9169 UINT32 cfg_l1_aux_clk_switch_core_clk_gate_en : 1 ; 9170 UINT32 cfg_l1_mac_powerdown_override_to_p2_en : 1 ; 9171 UINT32 Reserved_9 : 30 ; 9172 } Bits; 9173 9174 9175 UINT32 UInt32; 9176 9177 } PCIE_CTRL_9_U; 9178 9179 9180 9181 9182 typedef union tagPcieCtrl10 9183 { 9184 9185 struct 9186 { 9187 UINT32 cfg_aer_rc_err_msi_mask : 1 ; 9188 UINT32 cfg_sys_err_rc_mask : 1 ; 9189 UINT32 radm_correctable_err_mask : 1 ; 9190 UINT32 radm_nonfatal_err_mask : 1 ; 9191 UINT32 radm_fatal_err_mask : 1 ; 9192 UINT32 radm_pm_pme_mask : 1 ; 9193 UINT32 radm_pm_to_ack_mask : 1 ; 9194 UINT32 ven_msi_int_mask : 1 ; 9195 UINT32 radm_cpl_timeout_mask : 1 ; 9196 UINT32 radm_msg_unlock_mask : 1 ; 9197 UINT32 cfg_pme_msi_mask : 1 ; 9198 UINT32 bridge_flush_not_mask : 1 ; 9199 UINT32 link_req_rst_not_mask : 1 ; 9200 UINT32 pcie_p2_exit_int_mask : 1 ; 9201 UINT32 pcie_rx_lane_flip_en_tmp : 1 ; 9202 UINT32 pcie_tx_lane_flip_en_tmp : 1 ; 9203 UINT32 radm_pm_turnoff_mask : 1 ; 9204 UINT32 Reserved_11 : 15 ; 9205 } Bits; 9206 9207 9208 UINT32 UInt32; 9209 9210 } PCIE_CTRL_10_U; 9211 9212 9213 9214 9215 typedef union tagPcieCtrl11 9216 { 9217 9218 struct 9219 { 9220 UINT32 cfg_aer_rc_err_msi_clr : 1 ; 9221 UINT32 cfg_sys_err_rc_clr : 1 ; 9222 UINT32 radm_correctable_err_clr : 1 ; 9223 UINT32 radm_nonfatal_err_clr : 1 ; 9224 UINT32 radm_fatal_err_clr : 1 ; 9225 UINT32 radm_pm_pme_clr : 1 ; 9226 UINT32 radm_pm_to_ack_clr : 1 ; 9227 UINT32 ven_msi_int_clr : 1 ; 9228 UINT32 radm_cpl_timeout_clr : 1 ; 9229 UINT32 radm_msg_unlock_clr : 1 ; 9230 UINT32 cfg_pme_msi_clr : 1 ; 9231 UINT32 bridge_flush_not_clr : 1 ; 9232 UINT32 link_req_rst_not_clr : 1 ; 9233 UINT32 pcie_p2_exit_int_clr : 1 ; 9234 UINT32 pcie_slv_err_int_clr : 1 ; 9235 UINT32 pcie_mstr_err_int_clr : 1 ; 9236 UINT32 radm_pm_turnoff_clr : 1 ; 9237 UINT32 cfg_ntb_mode : 1 ; 9238 UINT32 Reserved_13 : 14 ; 9239 } Bits; 9240 9241 9242 UINT32 UInt32; 9243 9244 } PCIE_CTRL_11_U; 9245 9246 9247 9248 9249 typedef union tagPcieSysCtrl12 9250 { 9251 9252 struct 9253 { 9254 UINT32 slv_awmisc_info_func_num : 1 ; 9255 UINT32 slv_awmisc_info_vfunc_active : 1 ; 9256 UINT32 slv_awmisc_info_vfunc_num : 1 ; 9257 UINT32 Reserved_17 : 1 ; 9258 UINT32 slv_armisc_info_func_num : 1 ; 9259 UINT32 slv_armisc_info_vfunc_active : 1 ; 9260 UINT32 slv_armisc_info_vfunc_num : 1 ; 9261 UINT32 Reserved_16 : 1 ; 9262 UINT32 slv_awmisc_info_nw : 1 ; 9263 UINT32 slv_awmisc_info_ats : 2 ; 9264 UINT32 slv_armisc_info_nw : 1 ; 9265 UINT32 slv_armisc_info_ats : 2 ; 9266 UINT32 mstr_bmisc_info_ats : 2 ; 9267 UINT32 mstr_rmisc_info_ats : 2 ; 9268 UINT32 pcie_rfs_ctrl : 6 ; 9269 UINT32 pcie_rft_ctrl : 7 ; 9270 UINT32 Reserved_15 : 1 ; 9271 } Bits; 9272 9273 9274 UINT32 UInt32; 9275 9276 } PCIE_SYS_CTRL12_U; 9277 9278 9279 9280 9281 typedef union tagPcieSysCtrl16 9282 { 9283 9284 struct 9285 { 9286 UINT32 app_flr_pf_done : 1 ; 9287 UINT32 app_flr_vf_done : 2 ; 9288 UINT32 Reserved_23 : 5 ; 9289 UINT32 ven_msi_vfunc_active : 1 ; 9290 UINT32 ven_msi_vfunc_num : 1 ; 9291 UINT32 ven_msg_vfunc_active : 1 ; 9292 UINT32 ven_msg_vfunc_num : 1 ; 9293 UINT32 Reserved_22 : 20 ; 9294 } Bits; 9295 9296 9297 UINT32 UInt32; 9298 9299 } PCIE_SYS_CTRL16_U; 9300 9301 9302 9303 9304 typedef union tagPcieSysCtrl20 9305 { 9306 9307 struct 9308 { 9309 UINT32 ro_sel : 1 ; 9310 UINT32 dbi_func_num : 1 ; 9311 UINT32 dbi_vfunc_num : 1 ; 9312 UINT32 dbi_vfunc_active : 1 ; 9313 UINT32 dbi_addr_h20 : 20 ; 9314 UINT32 dbi_bar_num : 3 ; 9315 UINT32 dbi_rom_access : 1 ; 9316 UINT32 dbi_io_access : 1 ; 9317 UINT32 memicg_bypass : 1 ; 9318 UINT32 Reserved_28 : 2 ; 9319 } Bits; 9320 9321 9322 UINT32 UInt32; 9323 9324 } PCIE_SYS_CTRL20_U; 9325 9326 9327 9328 9329 typedef union tagPcieSysCtrl21 9330 { 9331 9332 struct 9333 { 9334 UINT32 pcie_sys_pre_det_state : 1 ; 9335 UINT32 pcie_sys_atten_button_pressed : 1 ; 9336 UINT32 Reserved_30 : 30 ; 9337 } Bits; 9338 9339 9340 UINT32 UInt32; 9341 9342 } PCIE_SYS_CTRL21_U; 9343 9344 9345 9346 9347 typedef union tagPcieSysCtrl23 9348 { 9349 9350 struct 9351 { 9352 UINT32 Reserved_35 : 2 ; 9353 UINT32 Reserved_34 : 30 ; 9354 } Bits; 9355 9356 9357 UINT32 UInt32; 9358 9359 } PCIE_SYS_CTRL23_U; 9360 9361 9362 9363 9364 typedef union tagPcieSysState5 9365 { 9366 9367 struct 9368 { 9369 UINT32 mstr_awmisc_info_func_num : 1 ; 9370 UINT32 mstr_awmisc_info_vfunc_active : 1 ; 9371 UINT32 mstr_awmisc_info_vfunc_num : 1 ; 9372 UINT32 Reserved_39 : 1 ; 9373 UINT32 mstr_armisc_info_func_num : 1 ; 9374 UINT32 mstr_armisc_info_vfunc_active : 1 ; 9375 UINT32 mstr_armisc_info_vfunc_num : 1 ; 9376 UINT32 Reserved_38 : 1 ; 9377 UINT32 mstr_awmisc_info_nw : 1 ; 9378 UINT32 mstr_awmisc_info_ats : 2 ; 9379 UINT32 mstr_armisc_info_nw : 1 ; 9380 UINT32 mstr_armisc_info_ats : 2 ; 9381 UINT32 slv_bmisc_info_ats : 2 ; 9382 UINT32 slv_rmisc_info_ats : 2 ; 9383 UINT32 Reserved_37 : 14 ; 9384 } Bits; 9385 9386 9387 UINT32 UInt32; 9388 9389 } PCIE_SYS_STATE5_U; 9390 9391 9392 9393 9394 typedef union tagPcieSysState6 9395 { 9396 9397 struct 9398 { 9399 UINT32 cfg_flr_pf_active : 1 ; 9400 UINT32 cfg_flr_vf_active : 2 ; 9401 UINT32 Reserved_41 : 29 ; 9402 } Bits; 9403 9404 9405 UINT32 UInt32; 9406 9407 } PCIE_SYS_STATE6_U; 9408 9409 9410 9411 9412 typedef union tagPcieSysState7 9413 { 9414 9415 struct 9416 { 9417 UINT32 radm_timeout_vfunc_active : 1 ; 9418 UINT32 radm_timeout_vfunc_num : 1 ; 9419 UINT32 trgt_timeout_cpl_vfunc_active : 1 ; 9420 UINT32 trgt_timeout_cpl_vfunc_num : 1 ; 9421 UINT32 Reserved_43 : 28 ; 9422 } Bits; 9423 9424 9425 UINT32 UInt32; 9426 9427 } PCIE_SYS_STATE7_U; 9428 9429 9430 9431 9432 typedef union tagPcieSysState11 9433 { 9434 9435 struct 9436 { 9437 UINT32 cfg_msi_64 : 1 ; 9438 UINT32 cfg_vf_msi_en : 2 ; 9439 UINT32 cfg_vf_msi_64 : 2 ; 9440 UINT32 cfg_multi_msi_en : 3 ; 9441 UINT32 cfg_vf_multi_msi_en : 6 ; 9442 UINT32 Reserved_48 : 2 ; 9443 UINT32 cfg_msi_data : 16 ; 9444 } Bits; 9445 9446 9447 UINT32 UInt32; 9448 9449 } PCIE_SYS_STATE11_U; 9450 9451 9452 9453 9454 typedef union tagPcieSysState12 9455 { 9456 9457 struct 9458 { 9459 UINT32 cfg_vf_en : 1 ; 9460 UINT32 cfg_ari_fwd_en : 1 ; 9461 UINT32 cfg_vf_bme : 2 ; 9462 UINT32 Reserved_51 : 4 ; 9463 UINT32 cfg_num_vf : 16 ; 9464 UINT32 Reserved_50 : 8 ; 9465 } Bits; 9466 9467 9468 UINT32 UInt32; 9469 9470 } PCIE_SYS_STATE12_U; 9471 9472 9473 9474 9475 typedef union tagPcieSysState20 9476 { 9477 9478 struct 9479 { 9480 UINT32 slv_bmisc_info : 11 ; 9481 UINT32 slv_rmisc_info : 11 ; 9482 UINT32 rtlh_rfc_upd : 1 ; 9483 UINT32 Reserved_60 : 9 ; 9484 } Bits; 9485 9486 9487 UINT32 UInt32; 9488 9489 } PCIE_SYS_STATE20_U; 9490 9491 9492 9493 9494 typedef union tagPcieSysState21 9495 { 9496 9497 struct 9498 { 9499 UINT32 cfg_msix_en : 1 ; 9500 UINT32 cfg_msix_func_mask : 1 ; 9501 UINT32 cfg_vf_msix_func_mask : 2 ; 9502 UINT32 cfg_vf_msix_en : 2 ; 9503 UINT32 Reserved_62 : 26 ; 9504 } Bits; 9505 9506 9507 UINT32 UInt32; 9508 9509 } PCIE_SYS_STATE21_U; 9510 9511 9512 9513 9514 typedef union tagPcieSysState22 9515 { 9516 9517 struct 9518 { 9519 UINT32 lbc_ext_vfunc_active : 1 ; 9520 UINT32 lbc_ext_vfunc_num : 1 ; 9521 UINT32 lbc_dbi_ack : 1 ; 9522 UINT32 pcie_mstr_awmisc_info : 24 ; 9523 UINT32 Reserved_64 : 5 ; 9524 } Bits; 9525 9526 9527 UINT32 UInt32; 9528 9529 } PCIE_SYS_STATE22_U; 9530 9531 9532 9533 9534 typedef union tagPcieSysState27 9535 { 9536 9537 struct 9538 { 9539 UINT32 trgt_cpl_timeout : 1 ; 9540 UINT32 trgt_timeout_cpl_func_num : 1 ; 9541 UINT32 trgt_timeout_cpl_tc : 3 ; 9542 UINT32 trgt_timeout_cpl_attr : 2 ; 9543 UINT32 trgt_timeout_cpl_len : 12 ; 9544 UINT32 trgt_lookup_empty : 1 ; 9545 UINT32 Reserved_70 : 12 ; 9546 } Bits; 9547 9548 9549 UINT32 UInt32; 9550 9551 } PCIE_SYS_STATE27_U; 9552 9553 9554 9555 9556 typedef union tagPcieSysState28 9557 { 9558 9559 struct 9560 { 9561 UINT32 trgt_timeout_lookup_id : 8 ; 9562 UINT32 trgt_lookup_id : 8 ; 9563 UINT32 radm_timeout_cpl_tag : 8 ; 9564 UINT32 Reserved_72 : 8 ; 9565 } Bits; 9566 9567 9568 UINT32 UInt32; 9569 9570 } PCIE_SYS_STATE28_U; 9571 9572 9573 9574 9575 typedef union tagPcieSysState29 9576 { 9577 9578 struct 9579 { 9580 UINT32 trgt_cpl_timeout : 1 ; 9581 UINT32 radm_timeout_func_num : 1 ; 9582 UINT32 radm_timeout_cpl_tc : 3 ; 9583 UINT32 radm_timeout_cpl_attr : 2 ; 9584 UINT32 radm_timeout_cpl_len : 12 ; 9585 UINT32 radm_pm_turnoff : 1 ; 9586 UINT32 Reserved_74 : 12 ; 9587 } Bits; 9588 9589 9590 UINT32 UInt32; 9591 9592 } PCIE_SYS_STATE29_U; 9593 9594 9595 9596 9597 typedef union tagPcieSysState30 9598 { 9599 9600 struct 9601 { 9602 UINT32 cfg_pbus_num : 8 ; 9603 UINT32 cfg_pbus_dev_num : 5 ; 9604 UINT32 cfg_link_auto_bw_int : 1 ; 9605 UINT32 cfg_bw_mgt_int : 1 ; 9606 UINT32 Reserved_76 : 17 ; 9607 } Bits; 9608 9609 9610 UINT32 UInt32; 9611 9612 } PCIE_SYS_STATE30_U; 9613 9614 9615 9616 9617 typedef union tagPcieSysState32 9618 { 9619 9620 struct 9621 { 9622 UINT32 mstr_awmisc_info_dma : 6 ; 9623 UINT32 mstr_armisc_info_dma : 6 ; 9624 UINT32 cfg_hw_auto_sp_dis : 1 ; 9625 UINT32 link_timeout_flush_not : 1 ; 9626 UINT32 mac_phy_clk_req_n : 1 ; 9627 UINT32 wake_ref_rst_n : 1 ; 9628 UINT32 pcie_wake : 1 ; 9629 UINT32 Reserved_79 : 15 ; 9630 } Bits; 9631 9632 9633 UINT32 UInt32; 9634 9635 } PCIE_SYS_STATE32_U; 9636 9637 9638 9639 9640 typedef union tagPcieSysState39 9641 { 9642 9643 struct 9644 { 9645 UINT32 radm_msg_unlock_reqid : 16 ; 9646 UINT32 radm_nonfatal_err_reqid : 16 ; 9647 } Bits; 9648 9649 9650 UINT32 UInt32; 9651 9652 } PCIE_SYS_STATE39_U; 9653 9654 9655 9656 9657 typedef union tagPcieSysState44 9658 { 9659 9660 struct 9661 { 9662 UINT32 radm_unlock_reqid : 16 ; 9663 UINT32 radm_nonfatal_err_reqid : 16 ; 9664 } Bits; 9665 9666 9667 UINT32 UInt32; 9668 9669 } PCIE_SYS_STATE44_U; 9670 9671 9672 9673 9674 typedef union tagPcieSysState49 9675 { 9676 9677 struct 9678 { 9679 UINT32 radm_pm_pme_reqid : 16 ; 9680 UINT32 radm_pm_ack_to_reqid : 16 ; 9681 } Bits; 9682 9683 9684 UINT32 UInt32; 9685 9686 } PCIE_SYS_STATE49_U; 9687 9688 9689 9690 9691 typedef union tagPcieStat0 9692 { 9693 9694 struct 9695 { 9696 UINT32 pcie2_gm_cmposer_lookup_err : 1 ; 9697 UINT32 pcie2_radmx_cmposer_lookup_err : 1 ; 9698 UINT32 pcie2_cfg_pwr_ind : 2 ; 9699 UINT32 pcie2_cfg_atten_ind : 2 ; 9700 UINT32 pcie2_cfg_pwr_ctrler_ctrl : 1 ; 9701 UINT32 pcie2_pm_xtlh_block_tlp : 1 ; 9702 UINT32 pcie2_cfg_mem_space_en : 1 ; 9703 UINT32 pcie2_cfg_rcb : 1 ; 9704 UINT32 pcie2_rdlh_link_up : 1 ; 9705 UINT32 pcie2_pm_curnt_state : 3 ; 9706 UINT32 pcie2_cfg_aer_rc_err_int : 1 ; 9707 UINT32 Reserved_106 : 1 ; 9708 UINT32 pcie2_cfg_aer_int_msg_num : 5 ; 9709 UINT32 Reserved_105 : 1 ; 9710 UINT32 pcie2_xmlh_link_up : 1 ; 9711 UINT32 pcie2_wake : 1 ; 9712 UINT32 pcie2_cfg_eml_control : 1 ; 9713 UINT32 pcie2_hp_pme : 1 ; 9714 UINT32 pcie2_hp_int : 1 ; 9715 UINT32 pcie2_hp_msi : 1 ; 9716 UINT32 pcie2_pm_status : 1 ; 9717 UINT32 pcie2_ref_clk_req_n : 1 ; 9718 UINT32 Reserved_104 : 2 ; 9719 } Bits; 9720 9721 9722 UINT32 UInt32; 9723 9724 } PCIE_STAT_0_U; 9725 9726 9727 9728 9729 typedef union tagPcieStat1 9730 { 9731 9732 struct 9733 { 9734 UINT32 axi_parity_errs_reg : 4 ; 9735 UINT32 app_parity_errs_reg : 3 ; 9736 UINT32 pm_linkst_in_l1 : 1 ; 9737 UINT32 pm_linkst_in_l2 : 1 ; 9738 UINT32 pm_linkst_l2_exit : 1 ; 9739 UINT32 mac_phy_power_down : 2 ; 9740 UINT32 radm_correctabl_err_reg : 1 ; 9741 UINT32 radm_nonfatal_err_reg : 1 ; 9742 UINT32 radm_fatal_err_reg : 1 ; 9743 UINT32 radm_pm_to_pme_reg : 1 ; 9744 UINT32 radm_pm_to_ack_reg : 1 ; 9745 UINT32 radm_cpl_timeout_reg : 1 ; 9746 UINT32 radm_msg_unlock_reg : 1 ; 9747 UINT32 cfg_pme_msi_reg : 1 ; 9748 UINT32 bridge_flush_not_reg : 1 ; 9749 UINT32 link_req_rst_not_reg : 1 ; 9750 UINT32 pcie2_cfg_aer_rc_err_msi : 1 ; 9751 UINT32 pcie2_cfg_sys_err_rc : 1 ; 9752 UINT32 Reserved_107 : 8 ; 9753 } Bits; 9754 9755 9756 UINT32 UInt32; 9757 9758 } PCIE_STAT_1_U; 9759 9760 9761 9762 9763 typedef union tagPcieStat3 9764 { 9765 9766 struct 9767 { 9768 UINT32 radm_msg_req_id : 16 ; 9769 UINT32 Reserved_108 : 16 ; 9770 } Bits; 9771 9772 9773 UINT32 UInt32; 9774 9775 } PCIE_STAT_3_U; 9776 9777 9778 9779 9780 typedef union tagPcieStat4 9781 { 9782 9783 struct 9784 { 9785 UINT32 ltssm_state : 6 ; 9786 UINT32 mac_phy_rate : 2 ; 9787 UINT32 pcie_slv_err_int_state : 1 ; 9788 UINT32 retry_sram_addr : 10 ; 9789 UINT32 pcie_mstr_rresp_int_state : 1 ; 9790 UINT32 pcie_mstr_bresp_int_state : 1 ; 9791 UINT32 pcie_radm_inta_int_state : 1 ; 9792 UINT32 pcie_radm_intb_int_state : 1 ; 9793 UINT32 pcie_radm_intc_int_state : 1 ; 9794 UINT32 pcie_radm_intd_int_state : 1 ; 9795 UINT32 pme_int_state : 1 ; 9796 UINT32 radm_vendr_msg_int_state : 1 ; 9797 UINT32 Reserved_109 : 5 ; 9798 } Bits; 9799 9800 9801 UINT32 UInt32; 9802 9803 } PCIE_STAT_4_U; 9804 9805 9806 #define PCIE_MUL_BASE (0x1000) 9807 9808 9809 9810 9811 #define PCIE_MUL_MC_CTRL_REG (PCIE_MUL_BASE + 0x0) 9812 #define PCIE_MUL_CFG_WIN0_BAR_LOWER_REG (PCIE_MUL_BASE + 0x4) 9813 #define PCIE_MUL_CFG_WIN0_BAR_UPPER_REG (PCIE_MUL_BASE + 0x8) 9814 #define PCIE_MUL_CFG_WIN1_BAR_LOWER_REG (PCIE_MUL_BASE + 0xC) 9815 #define PCIE_MUL_CFG_WIN1_BAR_UPPER_REG (PCIE_MUL_BASE + 0x10) 9816 #define PCIE_MUL_CFG_WIN2_BAR_LOWER_REG (PCIE_MUL_BASE + 0x14) 9817 #define PCIE_MUL_CFG_WIN2_BAR_UPPER_REG (PCIE_MUL_BASE + 0x18) 9818 #define PCIE_MUL_CFG_WIN3_BAR_LOWER_REG (PCIE_MUL_BASE + 0x1C) 9819 #define PCIE_MUL_CFG_WIN3_BAR_UPPER_REG (PCIE_MUL_BASE + 0x20) 9820 #define PCIE_MUL_CFG_WIN4_BAR_LOWER_REG (PCIE_MUL_BASE + 0x24) 9821 #define PCIE_MUL_CFG_WIN4_BAR_UPPER_REG (PCIE_MUL_BASE + 0x28) 9822 #define PCIE_MUL_CFG_WIN5_BAR_LOWER_REG (PCIE_MUL_BASE + 0x2C) 9823 #define PCIE_MUL_CFG_WIN5_BAR_UPPER_REG (PCIE_MUL_BASE + 0x30) 9824 #define PCIE_MUL_CFG_WIN6_BAR_LOWER_REG (PCIE_MUL_BASE + 0x34) 9825 #define PCIE_MUL_CFG_WIN6_BAR_UPPER_REG (PCIE_MUL_BASE + 0x38) 9826 #define PCIE_MUL_CFG_WIN7_BAR_LOWER_REG (PCIE_MUL_BASE + 0x3C) 9827 #define PCIE_MUL_CFG_WIN7_BAR_UPPER_REG (PCIE_MUL_BASE + 0x40) 9828 #define PCIE_MUL_CFG_WIN8_BAR_LOWER_REG (PCIE_MUL_BASE + 0x44) 9829 #define PCIE_MUL_CFG_WIN8_BAR_UPPER_REG (PCIE_MUL_BASE + 0x48) 9830 #define PCIE_MUL_CFG_WIN9_BAR_LOWER_REG (PCIE_MUL_BASE + 0x4C) 9831 #define PCIE_MUL_CFG_WIN9_BAR_UPPER_REG (PCIE_MUL_BASE + 0x50) 9832 #define PCIE_MUL_CFG_WIN10_BAR_LOWER_REG (PCIE_MUL_BASE + 0x54) 9833 #define PCIE_MUL_CFG_WIN10_BAR_UPPER_REG (PCIE_MUL_BASE + 0x58) 9834 #define PCIE_MUL_CFG_WIN11_BAR_LOWER_REG (PCIE_MUL_BASE + 0x5C) 9835 #define PCIE_MUL_CFG_WIN11_BAR_UPPER_REG (PCIE_MUL_BASE + 0x60) 9836 #define PCIE_MUL_CFG_WIN12_BAR_LOWER_REG (PCIE_MUL_BASE + 0x64) 9837 #define PCIE_MUL_CFG_WIN12_BAR_UPPER_REG (PCIE_MUL_BASE + 0x68) 9838 #define PCIE_MUL_CFG_WIN13_BAR_LOWER_REG (PCIE_MUL_BASE + 0x6C) 9839 #define PCIE_MUL_CFG_WIN13_BAR_UPPER_REG (PCIE_MUL_BASE + 0x70) 9840 #define PCIE_MUL_CFG_WIN14_BAR_LOWER_REG (PCIE_MUL_BASE + 0x74) 9841 #define PCIE_MUL_CFG_WIN14_BAR_UPPER_REG (PCIE_MUL_BASE + 0x78) 9842 #define PCIE_MUL_CFG_WIN15_BAR_LOWER_REG (PCIE_MUL_BASE + 0x7C) 9843 #define PCIE_MUL_CFG_WIN15_BAR_UPPER_REG (PCIE_MUL_BASE + 0x80) 9844 #define PCIE_MUL_CFG_WIN0_SIZE_REG (PCIE_MUL_BASE + 0x84) 9845 #define PCIE_MUL_CFG_WIN1_SIZE_REG (PCIE_MUL_BASE + 0x88) 9846 #define PCIE_MUL_CFG_WIN2_SIZE_REG (PCIE_MUL_BASE + 0x8C) 9847 #define PCIE_MUL_CFG_WIN3_SIZE_REG (PCIE_MUL_BASE + 0x90) 9848 #define PCIE_MUL_CFG_WIN4_SIZE_REG (PCIE_MUL_BASE + 0x94) 9849 #define PCIE_MUL_CFG_WIN5_SIZE_REG (PCIE_MUL_BASE + 0x98) 9850 #define PCIE_MUL_CFG_WIN6_SIZE_REG (PCIE_MUL_BASE + 0x9C) 9851 #define PCIE_MUL_CFG_WIN7_SIZE_REG (PCIE_MUL_BASE + 0xA0) 9852 #define PCIE_MUL_CFG_WIN8_SIZE_REG (PCIE_MUL_BASE + 0xA4) 9853 #define PCIE_MUL_CFG_WIN9_SIZE_REG (PCIE_MUL_BASE + 0xA8) 9854 #define PCIE_MUL_CFG_WIN10_SIZE_REG (PCIE_MUL_BASE + 0xAC) 9855 #define PCIE_MUL_CFG_WIN11_SIZE_REG (PCIE_MUL_BASE + 0xB0) 9856 #define PCIE_MUL_CFG_WIN12_SIZE_REG (PCIE_MUL_BASE + 0xB4) 9857 #define PCIE_MUL_CFG_WIN13_SIZE_REG (PCIE_MUL_BASE + 0xB8) 9858 #define PCIE_MUL_CFG_WIN14_SIZE_REG (PCIE_MUL_BASE + 0xBC) 9859 #define PCIE_MUL_CFG_WIN15_SIZE_REG (PCIE_MUL_BASE + 0xC0) 9860 #define PCIE_MUL_CFG_WIN0_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xC4) 9861 #define PCIE_MUL_CFG_WIN0_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xC8) 9862 #define PCIE_MUL_CFG_WIN1_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xCC) 9863 #define PCIE_MUL_CFG_WIN1_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xD0) 9864 #define PCIE_MUL_CFG_WIN2_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xD4) 9865 #define PCIE_MUL_CFG_WIN2_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xD8) 9866 #define PCIE_MUL_CFG_WIN3_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xDC) 9867 #define PCIE_MUL_CFG_WIN3_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xE0) 9868 #define PCIE_MUL_CFG_WIN4_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xE4) 9869 #define PCIE_MUL_CFG_WIN4_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xE8) 9870 #define PCIE_MUL_CFG_WIN5_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xEC) 9871 #define PCIE_MUL_CFG_WIN5_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xF0) 9872 #define PCIE_MUL_CFG_WIN6_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xF4) 9873 #define PCIE_MUL_CFG_WIN6_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xF8) 9874 #define PCIE_MUL_CFG_WIN7_XLAT_LOWER_REG (PCIE_MUL_BASE + 0xFC) 9875 #define PCIE_MUL_CFG_WIN7_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x100) 9876 #define PCIE_MUL_CFG_WIN8_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x104) 9877 #define PCIE_MUL_CFG_WIN8_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x108) 9878 #define PCIE_MUL_CFG_WIN9_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x10C) 9879 #define PCIE_MUL_CFG_WIN9_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x110) 9880 #define PCIE_MUL_CFG_WIN10_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x114) 9881 #define PCIE_MUL_CFG_WIN10_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x118) 9882 #define PCIE_MUL_CFG_WIN11_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x11C) 9883 #define PCIE_MUL_CFG_WIN11_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x120) 9884 #define PCIE_MUL_CFG_WIN12_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x124) 9885 #define PCIE_MUL_CFG_WIN12_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x128) 9886 #define PCIE_MUL_CFG_WIN13_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x12C) 9887 #define PCIE_MUL_CFG_WIN13_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x130) 9888 #define PCIE_MUL_CFG_WIN14_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x134) 9889 #define PCIE_MUL_CFG_WIN14_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x138) 9890 #define PCIE_MUL_CFG_WIN15_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x13C) 9891 #define PCIE_MUL_CFG_WIN15_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x140) 9892 #define PCIE_MUL_CFG_WIN_XLAT_EN_REG (PCIE_MUL_BASE + 0x144) 9893 #define PCIE_MUL_CFG_MCAST_CMD_TIMEOUT_REG (PCIE_MUL_BASE + 0x148) 9894 #define PCIE_MUL_CFG_INT_STATUS_REG (PCIE_MUL_BASE + 0x14C) 9895 #define PCIE_MUL_CFG_INJECT_ECC_ERR_REG (PCIE_MUL_BASE + 0x150) 9896 9897 9898 9899 9900 typedef union tagMcCtrl 9901 { 9902 9903 struct 9904 { 9905 UINT32 cfg_mcast_en : 1 ; 9906 UINT32 cfg_win0_mcast_en : 1 ; 9907 UINT32 cfg_win1_mcast_en : 1 ; 9908 UINT32 cfg_win2_mcast_en : 1 ; 9909 UINT32 cfg_win3_mcast_en : 1 ; 9910 UINT32 cfg_win4_mcast_en : 1 ; 9911 UINT32 cfg_win5_mcast_en : 1 ; 9912 UINT32 cfg_win6_mcast_en : 1 ; 9913 UINT32 cfg_win7_mcast_en : 1 ; 9914 UINT32 cfg_win8_mcast_en : 1 ; 9915 UINT32 cfg_win9_mcast_en : 1 ; 9916 UINT32 cfg_win10_mcast_en : 1 ; 9917 UINT32 cfg_win11_mcast_en : 1 ; 9918 UINT32 cfg_win12_mcast_en : 1 ; 9919 UINT32 cfg_win13_mcast_en : 1 ; 9920 UINT32 cfg_win14_mcast_en : 1 ; 9921 UINT32 cfg_win15_mcast_en : 1 ; 9922 UINT32 Reserved_0 : 15 ; 9923 } Bits; 9924 9925 9926 UINT32 UInt32; 9927 9928 } pcie_mul_mc_ctrl_u; 9929 9930 9931 9932 9933 typedef union tagCfgWin0Size 9934 { 9935 9936 struct 9937 { 9938 UINT32 cfg_win0_size : 6 ; 9939 UINT32 Reserved_1 : 26 ; 9940 } Bits; 9941 9942 9943 UINT32 UInt32; 9944 9945 } pcie_mul_cfg_win0_size_u; 9946 9947 9948 9949 9950 typedef union tagCfgWin1Size 9951 { 9952 9953 struct 9954 { 9955 UINT32 cfg_win1_size : 6 ; 9956 UINT32 Reserved_2 : 26 ; 9957 } Bits; 9958 9959 9960 UINT32 UInt32; 9961 9962 } pcie_mul_cfg_win1_size_u; 9963 9964 9965 9966 9967 typedef union tagCfgWin2Size 9968 { 9969 9970 struct 9971 { 9972 UINT32 cfg_win2_size : 6 ; 9973 UINT32 Reserved_3 : 26 ; 9974 } Bits; 9975 9976 9977 UINT32 UInt32; 9978 9979 } pcie_mul_cfg_win2_size_u; 9980 9981 9982 9983 9984 typedef union tagCfgWin3Size 9985 { 9986 9987 struct 9988 { 9989 UINT32 cfg_win3_size : 6 ; 9990 UINT32 Reserved_4 : 26 ; 9991 } Bits; 9992 9993 9994 UINT32 UInt32; 9995 9996 } pcie_mul_cfg_win3_size_u; 9997 9998 9999 10000 10001 typedef union tagCfgWin4Size 10002 { 10003 10004 struct 10005 { 10006 UINT32 cfg_win4_size : 6 ; 10007 UINT32 Reserved_5 : 26 ; 10008 } Bits; 10009 10010 10011 UINT32 UInt32; 10012 10013 } pcie_mul_cfg_win4_size_u; 10014 10015 10016 10017 10018 typedef union tagCfgWin5Size 10019 { 10020 10021 struct 10022 { 10023 UINT32 cfg_win5_size : 6 ; 10024 UINT32 Reserved_6 : 26 ; 10025 } Bits; 10026 10027 10028 UINT32 UInt32; 10029 10030 } pcie_mul_cfg_win5_size_u; 10031 10032 10033 10034 10035 typedef union tagCfgWin6Size 10036 { 10037 10038 struct 10039 { 10040 UINT32 cfg_win6_size : 6 ; 10041 UINT32 Reserved_7 : 26 ; 10042 } Bits; 10043 10044 10045 UINT32 UInt32; 10046 10047 } pcie_mul_cfg_win6_size_u; 10048 10049 10050 10051 10052 typedef union tagCfgWin7Size 10053 { 10054 10055 struct 10056 { 10057 UINT32 cfg_win7_size : 6 ; 10058 UINT32 Reserved_8 : 26 ; 10059 } Bits; 10060 10061 10062 UINT32 UInt32; 10063 10064 } pcie_mul_cfg_win7_size_u; 10065 10066 10067 10068 10069 typedef union tagCfgWin8Size 10070 { 10071 10072 struct 10073 { 10074 UINT32 cfg_win8_size : 6 ; 10075 UINT32 Reserved_9 : 26 ; 10076 } Bits; 10077 10078 10079 UINT32 UInt32; 10080 10081 } pcie_mul_cfg_win8_size_u; 10082 10083 10084 10085 10086 typedef union tagCfgWin9Size 10087 { 10088 10089 struct 10090 { 10091 UINT32 cfg_win9_size : 6 ; 10092 UINT32 Reserved_10 : 26 ; 10093 } Bits; 10094 10095 10096 UINT32 UInt32; 10097 10098 } pcie_mul_cfg_win9_size_u; 10099 10100 10101 10102 10103 typedef union tagCfgWin10Size 10104 { 10105 10106 struct 10107 { 10108 UINT32 cfg_win10_size : 6 ; 10109 UINT32 Reserved_11 : 26 ; 10110 } Bits; 10111 10112 10113 UINT32 UInt32; 10114 10115 } pcie_mul_cfg_win10_size_u; 10116 10117 10118 10119 10120 typedef union tagCfgWin11Size 10121 { 10122 10123 struct 10124 { 10125 UINT32 cfg_win11_size : 6 ; 10126 UINT32 Reserved_12 : 26 ; 10127 } Bits; 10128 10129 10130 UINT32 UInt32; 10131 10132 } pcie_mul_cfg_win11_size_u; 10133 10134 10135 10136 10137 typedef union tagCfgWin12Size 10138 { 10139 10140 struct 10141 { 10142 UINT32 cfg_win12_size : 6 ; 10143 UINT32 Reserved_13 : 26 ; 10144 } Bits; 10145 10146 10147 UINT32 UInt32; 10148 10149 } pcie_mul_cfg_win12_size_u; 10150 10151 10152 10153 10154 typedef union tagCfgWin13Size 10155 { 10156 10157 struct 10158 { 10159 UINT32 cfg_win13_size : 6 ; 10160 UINT32 Reserved_14 : 26 ; 10161 } Bits; 10162 10163 10164 UINT32 UInt32; 10165 10166 } pcie_mul_cfg_win13_size_u; 10167 10168 10169 10170 10171 typedef union tagCfgWin14Size 10172 { 10173 10174 struct 10175 { 10176 UINT32 cfg_win14_size : 6 ; 10177 UINT32 Reserved_15 : 26 ; 10178 } Bits; 10179 10180 10181 UINT32 UInt32; 10182 10183 } pcie_mul_cfg_win14_size_u; 10184 10185 10186 10187 10188 typedef union tagCfgWin15Size 10189 { 10190 10191 struct 10192 { 10193 UINT32 cfg_win15_size : 6 ; 10194 UINT32 Reserved_16 : 26 ; 10195 } Bits; 10196 10197 10198 UINT32 UInt32; 10199 10200 } pcie_mul_cfg_win15_size_u; 10201 10202 10203 10204 10205 typedef union tagCfgWinXlatEn 10206 { 10207 10208 struct 10209 { 10210 UINT32 cfg_win0_xlat_en : 1 ; 10211 UINT32 cfg_win1_xlat_en : 1 ; 10212 UINT32 cfg_win2_xlat_en : 1 ; 10213 UINT32 cfg_win3_xlat_en : 1 ; 10214 UINT32 cfg_win4_xlat_en : 1 ; 10215 UINT32 cfg_win5_xlat_en : 1 ; 10216 UINT32 cfg_win6_xlat_en : 1 ; 10217 UINT32 cfg_win7_xlat_en : 1 ; 10218 UINT32 cfg_win8_xlat_en : 1 ; 10219 UINT32 cfg_win9_xlat_en : 1 ; 10220 UINT32 cfg_win10_xlat_en : 1 ; 10221 UINT32 cfg_win11_xlat_en : 1 ; 10222 UINT32 cfg_win12_xlat_en : 1 ; 10223 UINT32 cfg_win13_xlat_en : 1 ; 10224 UINT32 cfg_win14_xlat_en : 1 ; 10225 UINT32 cfg_win15_xlat_en : 1 ; 10226 UINT32 Reserved_17 : 16 ; 10227 } Bits; 10228 10229 10230 UINT32 UInt32; 10231 10232 } pcie_mul_cfg_win_xlat_en_u; 10233 10234 10235 10236 10237 typedef union tagCfgMcastCmdTimeout 10238 { 10239 10240 struct 10241 { 10242 UINT32 cfg_mcast_cmd_timeout : 10 ; 10243 UINT32 Reserved_18 : 22 ; 10244 } Bits; 10245 10246 10247 UINT32 UInt32; 10248 10249 } pcie_mul_cfg_mcast_cmd_timeout_u; 10250 10251 10252 10253 10254 typedef union tagCfgIntStatus 10255 { 10256 10257 struct 10258 { 10259 UINT32 timeout_int : 1 ; 10260 UINT32 ecc_err1_int : 1 ; 10261 UINT32 ecc_err2_int : 1 ; 10262 UINT32 Reserved_19 : 29 ; 10263 } Bits; 10264 10265 10266 UINT32 UInt32; 10267 10268 } pcie_mul_cfg_int_status_u; 10269 10270 10271 10272 10273 typedef union tagCfgInjectEccErr 10274 { 10275 10276 struct 10277 { 10278 UINT32 ecc_err_inject_en : 1 ; 10279 UINT32 Reserved_20 : 31 ; 10280 } Bits; 10281 10282 10283 UINT32 UInt32; 10284 10285 } pcie_mul_cfg_inject_ecc_err_u; 10286 10287 10288 #define PCIE_EP_BASE (0x00000000) 10289 10290 10291 10292 10293 #define PCIE_EP_PCI_CFG_HDR0_REG (PCIE_EP_BASE + 0x0) 10294 #define PCIE_EP_PCI_CFG_HDR1_REG (PCIE_EP_BASE + 0x4) 10295 #define PCIE_EP_PCI_CFG_HDR2_REG (PCIE_EP_BASE + 0x8) 10296 #define PCIE_EP_PCI_CFG_HDR3_REG (PCIE_EP_BASE + 0xC) 10297 #define PCIE_EP_PCI_CFG_HDR4_REG (PCIE_EP_BASE + 0x10) 10298 #define PCIE_EP_PCI_CFG_HDR5_REG (PCIE_EP_BASE + 0x14) 10299 #define PCIE_EP_PCI_CFG_HDR6_REG (PCIE_EP_BASE + 0x18) 10300 #define PCIE_EP_PCI_CFG_HDR7_REG (PCIE_EP_BASE + 0x1C) 10301 #define PCIE_EP_PCI_CFG_HDR8_REG (PCIE_EP_BASE + 0x20) 10302 #define PCIE_EP_PCI_CFG_HDR9_REG (PCIE_EP_BASE + 0x24) 10303 #define PCIE_EP_PCI_CFG_HDR10_REG (PCIE_EP_BASE + 0x28) 10304 #define PCIE_EP_PCI_CFG_HDR11_REG (PCIE_EP_BASE + 0x2C) 10305 #define PCIE_EP_PCI_CFG_HDR12_REG (PCIE_EP_BASE + 0x30) 10306 #define PCIE_EP_PCI_CFG_HDR13_REG (PCIE_EP_BASE + 0x34) 10307 #define PCIE_EP_PCI_CFG_HDR14_REG (PCIE_EP_BASE + 0x38) 10308 #define PCIE_EP_PCI_CFG_HDR15_REG (PCIE_EP_BASE + 0x3C) 10309 #define PCIE_EP_PCI_PM_CAP0_REG (PCIE_EP_BASE + 0x40) 10310 #define PCIE_EP_PCI_PM_CAP1_REG (PCIE_EP_BASE + 0x44) 10311 #define PCIE_EP_PCI_MSI_CAP0_REG (PCIE_EP_BASE + 0x50) 10312 #define PCIE_EP_PCI_MSI_CAP1_REG (PCIE_EP_BASE + 0x54) 10313 #define PCIE_EP_PCI_MSI_CAP2_REG (PCIE_EP_BASE + 0x58) 10314 #define PCIE_EP_PCI_MSI_CAP3_REG (PCIE_EP_BASE + 0x5C) 10315 #define PCIE_EP_PCIE_CAP0_REG (PCIE_EP_BASE + 0x70) 10316 #define PCIE_EP_PCIE_CAP1_REG (PCIE_EP_BASE + 0x74) 10317 #define PCIE_EP_PCIE_CAP2_REG (PCIE_EP_BASE + 0x78) 10318 #define PCIE_EP_PCIE_CAP3_REG (PCIE_EP_BASE + 0x7C) 10319 #define PCIE_EP_PCIE_CAP4_REG (PCIE_EP_BASE + 0x80) 10320 #define PCIE_EP_PCIE_CAP5_REG (PCIE_EP_BASE + 0x84) 10321 #define PCIE_EP_PCIE_CAP6_REG (PCIE_EP_BASE + 0x88) 10322 #define PCIE_EP_PCIE_CAP7_REG (PCIE_EP_BASE + 0x8C) 10323 #define PCIE_EP_PCIE_CAP8_REG (PCIE_EP_BASE + 0x90) 10324 #define PCIE_EP_PCIE_CAP9_REG (PCIE_EP_BASE + 0x94) 10325 #define PCIE_EP_PCIE_CAP10_REG (PCIE_EP_BASE + 0x98) 10326 #define PCIE_EP_PCIE_CAP11_REG (PCIE_EP_BASE + 0x9C) 10327 #define PCIE_EP_PCIE_CAP12_REG (PCIE_EP_BASE + 0xA0) 10328 #define PCIE_EP_SLOT_CAP_REG (PCIE_EP_BASE + 0xC0) 10329 #define PCIE_EP_AER_CAP0_REG (PCIE_EP_BASE + 0x100) 10330 #define PCIE_EP_AER_CAP1_REG (PCIE_EP_BASE + 0x104) 10331 #define PCIE_EP_AER_CAP2_REG (PCIE_EP_BASE + 0x108) 10332 #define PCIE_EP_AER_CAP3_REG (PCIE_EP_BASE + 0x10C) 10333 #define PCIE_EP_AER_CAP4_REG (PCIE_EP_BASE + 0x110) 10334 #define PCIE_EP_AER_CAP5_REG (PCIE_EP_BASE + 0x114) 10335 #define PCIE_EP_AER_CAP6_REG (PCIE_EP_BASE + 0x118) 10336 #define PCIE_EP_AER_CAP7_REG (PCIE_EP_BASE + 0x11C) 10337 #define PCIE_EP_AER_CAP8_REG (PCIE_EP_BASE + 0x120) 10338 #define PCIE_EP_AER_CAP9_REG (PCIE_EP_BASE + 0x124) 10339 #define PCIE_EP_AER_CAP10_REG (PCIE_EP_BASE + 0x128) 10340 #define PCIE_EP_AER_CAP11_REG (PCIE_EP_BASE + 0x12C) 10341 #define PCIE_EP_AER_CAP12_REG (PCIE_EP_BASE + 0x130) 10342 #define PCIE_EP_AER_CAP13_REG (PCIE_EP_BASE + 0x134) 10343 #define PCIE_EP_VC_CAP0_REG (PCIE_EP_BASE + 0x140) 10344 #define PCIE_EP_VC_CAP1_REG (PCIE_EP_BASE + 0x144) 10345 #define PCIE_EP_VC_CAP2_REG (PCIE_EP_BASE + 0x148) 10346 #define PCIE_EP_VC_CAP3_REG (PCIE_EP_BASE + 0x14C) 10347 #define PCIE_EP_VC_CAP4_REG (PCIE_EP_BASE + 0x150) 10348 #define PCIE_EP_VC_CAP5_REG (PCIE_EP_BASE + 0x154) 10349 #define PCIE_EP_VC_CAP6_REG (PCIE_EP_BASE + 0x158) 10350 #define PCIE_EP_VC_CAP7_REG (PCIE_EP_BASE + 0x15C) 10351 #define PCIE_EP_VC_CAP8_REG (PCIE_EP_BASE + 0x160) 10352 #define PCIE_EP_VC_CAP9_REG (PCIE_EP_BASE + 0x164) 10353 #define PCIE_EP_PORT_LOGIC0_REG (PCIE_EP_BASE + 0x700) 10354 #define PCIE_EP_PORT_LOGIC1_REG (PCIE_EP_BASE + 0x704) 10355 #define PCIE_EP_PORT_LOGIC2_REG (PCIE_EP_BASE + 0x708) 10356 #define PCIE_EP_PORT_LOGIC3_REG (PCIE_EP_BASE + 0x0) 10357 #define PCIE_EP_PORT_LOGIC4_REG (PCIE_EP_BASE + 0x710) 10358 #define PCIE_EP_PORT_LOGIC5_REG (PCIE_EP_BASE + 0x714) 10359 #define PCIE_EP_PORT_LOGIC6_REG (PCIE_EP_BASE + 0x718) 10360 #define PCIE_EP_PORT_LOGIC7_REG (PCIE_EP_BASE + 0x71C) 10361 #define PCIE_EP_PORT_LOGIC8_REG (PCIE_EP_BASE + 0x720) 10362 #define PCIE_EP_PORT_LOGIC9_REG (PCIE_EP_BASE + 0x724) 10363 #define PCIE_EP_PORT_LOGIC10_REG (PCIE_EP_BASE + 0x728) 10364 #define PCIE_EP_PORT_LOGIC11_REG (PCIE_EP_BASE + 0x72C) 10365 #define PCIE_EP_PORT_LOGIC12_REG (PCIE_EP_BASE + 0x730) 10366 #define PCIE_EP_PORT_LOGIC13_REG (PCIE_EP_BASE + 0x734) 10367 #define PCIE_EP_PORT_LOGIC14_REG (PCIE_EP_BASE + 0x738) 10368 #define PCIE_EP_PORT_LOGIC15_REG (PCIE_EP_BASE + 0x73C) 10369 #define PCIE_EP_PORT_LOGIC16_REG (PCIE_EP_BASE + 0x748) 10370 #define PCIE_EP_PORT_LOGIC17_REG (PCIE_EP_BASE + 0x74C) 10371 #define PCIE_EP_PORT_LOGIC18_REG (PCIE_EP_BASE + 0x750) 10372 #define PCIE_EP_PORT_LOGIC19_REG (PCIE_EP_BASE + 0x7A8) 10373 #define PCIE_EP_PORT_LOGIC20_REG (PCIE_EP_BASE + 0x7AC) 10374 #define PCIE_EP_PORT_LOGIC21_REG (PCIE_EP_BASE + 0x7B0) 10375 #define PCIE_EP_PORT_LOGIC22_REG (PCIE_EP_BASE + 0x80C) 10376 #define PCIE_EP_PORTLOGIC23_REG (PCIE_EP_BASE + 0x810) 10377 #define PCIE_EP_PORTLOGIC24_REG (PCIE_EP_BASE + 0x814) 10378 #define PCIE_EP_PORTLOGIC25_REG (PCIE_EP_BASE + 0x818) 10379 #define PCIE_EP_PORTLOGIC26_REG (PCIE_EP_BASE + 0x81C) 10380 #define PCIE_EP_PORTLOGIC27_REG (PCIE_EP_BASE + 0x820) 10381 #define PCIE_EP_PORTLOGIC28_REG (PCIE_EP_BASE + 0x824) 10382 #define PCIE_EP_PORTLOGIC29_REG (PCIE_EP_BASE + 0x828) 10383 #define PCIE_EP_PORTLOGIC30_REG (PCIE_EP_BASE + 0x82C) 10384 #define PCIE_EP_PORTLOGIC31_REG (PCIE_EP_BASE + 0x830) 10385 #define PCIE_EP_PORTLOGIC32_REG (PCIE_EP_BASE + 0x834) 10386 #define PCIE_EP_PORTLOGIC33_REG (PCIE_EP_BASE + 0x838) 10387 #define PCIE_EP_PORTLOGIC34_REG (PCIE_EP_BASE + 0x83C) 10388 #define PCIE_EP_PORTLOGIC35_REG (PCIE_EP_BASE + 0x840) 10389 #define PCIE_EP_PORTLOGIC36_REG (PCIE_EP_BASE + 0x844) 10390 #define PCIE_EP_PORTLOGIC37_REG (PCIE_EP_BASE + 0x848) 10391 #define PCIE_EP_PORTLOGIC38_REG (PCIE_EP_BASE + 0x84C) 10392 #define PCIE_EP_PORTLOGIC39_REG (PCIE_EP_BASE + 0x850) 10393 #define PCIE_EP_PORTLOGIC40_REG (PCIE_EP_BASE + 0x854) 10394 #define PCIE_EP_PORTLOGIC41_REG (PCIE_EP_BASE + 0x858) 10395 #define PCIE_EP_PORTLOGIC42_REG (PCIE_EP_BASE + 0x85C) 10396 #define PCIE_EP_PORTLOGIC43_REG (PCIE_EP_BASE + 0x860) 10397 #define PCIE_EP_PORTLOGIC44_REG (PCIE_EP_BASE + 0x864) 10398 #define PCIE_EP_PORTLOGIC45_REG (PCIE_EP_BASE + 0x868) 10399 #define PCIE_EP_PORTLOGIC46_REG (PCIE_EP_BASE + 0x86C) 10400 #define PCIE_EP_PORTLOGIC47_REG (PCIE_EP_BASE + 0x870) 10401 #define PCIE_EP_PORTLOGIC48_REG (PCIE_EP_BASE + 0x874) 10402 #define PCIE_EP_PORTLOGIC49_REG (PCIE_EP_BASE + 0x878) 10403 #define PCIE_EP_PORTLOGIC50_REG (PCIE_EP_BASE + 0x87C) 10404 #define PCIE_EP_PORTLOGIC51_REG (PCIE_EP_BASE + 0x880) 10405 #define PCIE_EP_PORTLOGIC52_REG (PCIE_EP_BASE + 0x884) 10406 #define PCIE_EP_PORTLOGIC53_REG (PCIE_EP_BASE + 0x888) 10407 #define PCIE_EP_LINK_TIMEOUT_OFF_REG (PCIE_EP_BASE + 0x8d4) 10408 #define PCIE_EP_PORTLOGIC54_REG (PCIE_EP_BASE + 0x900) 10409 #define PCIE_EP_PORTLOGIC55_REG (PCIE_EP_BASE + 0x904) 10410 #define PCIE_EP_PORTLOGIC56_REG (PCIE_EP_BASE + 0x908) 10411 #define PCIE_EP_PORTLOGIC57_REG (PCIE_EP_BASE + 0x90C) 10412 #define PCIE_EP_PORTLOGIC58_REG (PCIE_EP_BASE + 0x910) 10413 #define PCIE_EP_PORTLOGIC59_REG (PCIE_EP_BASE + 0x914) 10414 #define PCIE_EP_PORTLOGIC60_REG (PCIE_EP_BASE + 0x918) 10415 #define PCIE_EP_PORTLOGIC61_REG (PCIE_EP_BASE + 0x91C) 10416 #define PCIE_EP_PORTLOGIC62_REG (PCIE_EP_BASE + 0x97C) 10417 #define PCIE_EP_PORTLOGIC63_REG (PCIE_EP_BASE + 0x980) 10418 #define PCIE_EP_PORTLOGIC64_REG (PCIE_EP_BASE + 0x99C) 10419 #define PCIE_EP_PORTLOGIC65_REG (PCIE_EP_BASE + 0x9A0) 10420 #define PCIE_EP_PORTLOGIC66_REG (PCIE_EP_BASE + 0x9BC) 10421 #define PCIE_EP_PORTLOGIC67_REG (PCIE_EP_BASE + 0x9C4) 10422 #define PCIE_EP_PORTLOGIC68_REG (PCIE_EP_BASE + 0x9C8) 10423 #define PCIE_EP_PORTLOGIC69_REG (PCIE_EP_BASE + 0x9CC) 10424 #define PCIE_EP_PORTLOGIC70_REG (PCIE_EP_BASE + 0x9D0) 10425 #define PCIE_EP_PORTLOGIC71_REG (PCIE_EP_BASE + 0x9D4) 10426 #define PCIE_EP_PORTLOGIC72_REG (PCIE_EP_BASE + 0x9D8) 10427 #define PCIE_EP_PORTLOGIC73_REG (PCIE_EP_BASE + 0x9DC) 10428 #define PCIE_EP_PORTLOGIC74_REG (PCIE_EP_BASE + 0x9E0) 10429 #define PCIE_EP_PORTLOGIC75_REG (PCIE_EP_BASE + 0xA00) 10430 #define PCIE_EP_PORTLOGIC76_REG (PCIE_EP_BASE + 0xA10) 10431 #define PCIE_EP_PORTLOGIC77_REG (PCIE_EP_BASE + 0xA18) 10432 #define PCIE_EP_PORTLOGIC78_REG (PCIE_EP_BASE + 0xA1C) 10433 #define PCIE_EP_PORTLOGIC79_REG (PCIE_EP_BASE + 0xA24) 10434 #define PCIE_EP_PORTLOGIC80_REG (PCIE_EP_BASE + 0xA28) 10435 #define PCIE_EP_PORTLOGIC81_REG (PCIE_EP_BASE + 0xA34) 10436 #define PCIE_EP_PORTLOGIC82_REG (PCIE_EP_BASE + 0xA3C) 10437 #define PCIE_EP_PORTLOGIC83_REG (PCIE_EP_BASE + 0xA40) 10438 #define PCIE_EP_PORTLOGIC84_REG (PCIE_EP_BASE + 0xA44) 10439 #define PCIE_EP_PORTLOGIC85_REG (PCIE_EP_BASE + 0xA48) 10440 #define PCIE_EP_PORTLOGIC86_REG (PCIE_EP_BASE + 0xA6C) 10441 #define PCIE_EP_PORTLOGIC87_REG (PCIE_EP_BASE + 0xA70) 10442 #define PCIE_EP_PORTLOGIC88_REG (PCIE_EP_BASE + 0xA78) 10443 #define PCIE_EP_PORTLOGIC89_REG (PCIE_EP_BASE + 0xA7C) 10444 #define PCIE_EP_PORTLOGIC90_REG (PCIE_EP_BASE + 0xA80) 10445 #define PCIE_EP_PORTLOGIC91_REG (PCIE_EP_BASE + 0xA84) 10446 #define PCIE_EP_PORTLOGIC92_REG (PCIE_EP_BASE + 0xA88) 10447 #define PCIE_EP_PORTLOGIC93_REG (PCIE_EP_BASE + 0xA8C) 10448 #define PCIE_EP_PORTLOGIC94_REG (PCIE_EP_BASE + 0xA90) 10449 10450 10451 10452 typedef union tagPciCfgHdr0 10453 { 10454 10455 struct 10456 { 10457 UINT32 vendor_id : 16 ; 10458 UINT32 device_id : 16 ; 10459 } Bits; 10460 10461 10462 UINT32 UInt32; 10463 10464 } PCIE_EP_PCI_CFG_HDR0_U; 10465 10466 10467 10468 10469 typedef union tagPciCfgHdr1 10470 { 10471 10472 struct 10473 { 10474 UINT32 io_space_enable : 1 ; 10475 UINT32 memory_space_enable : 1 ; 10476 UINT32 bus_master_enable : 1 ; 10477 UINT32 specialcycleenable : 1 ; 10478 UINT32 memory_write_and_invalidate : 1 ; 10479 UINT32 vga_palette_snoop_enable : 1 ; 10480 UINT32 parity_error_response : 1 ; 10481 UINT32 idsel_stepping_waitcycle_control : 1 ; 10482 UINT32 serr_enable : 1 ; 10483 UINT32 fastback_to_backenable : 1 ; 10484 UINT32 interrupt_disable : 1 ; 10485 UINT32 Reserved_2 : 5 ; 10486 UINT32 Reserved_1 : 3 ; 10487 UINT32 intx_status : 1 ; 10488 UINT32 capabilitieslist : 1 ; 10489 UINT32 pcibus66mhzcapable : 1 ; 10490 UINT32 Reserved_0 : 1 ; 10491 UINT32 fastback_to_back : 1 ; 10492 UINT32 masterdataparityerror : 1 ; 10493 UINT32 devsel_timing : 2 ; 10494 UINT32 signaled_target_abort : 1 ; 10495 UINT32 received_target_abort : 1 ; 10496 UINT32 received_master_abort : 1 ; 10497 UINT32 signaled_system_error : 1 ; 10498 UINT32 detected_parity_error : 1 ; 10499 } Bits; 10500 10501 10502 UINT32 UInt32; 10503 10504 } PCIE_EP_PCI_CFG_HDR1_U; 10505 10506 10507 10508 10509 typedef union tagPciCfgHdr2 10510 { 10511 10512 struct 10513 { 10514 UINT32 revision_identification : 8 ; 10515 UINT32 Reserved_3 : 8 ; 10516 UINT32 sub_class : 8 ; 10517 UINT32 baseclass : 8 ; 10518 } Bits; 10519 10520 10521 UINT32 UInt32; 10522 10523 } PCIE_EP_PCI_CFG_HDR2_U; 10524 10525 10526 10527 10528 typedef union tagPciCfgHdr3 10529 { 10530 10531 struct 10532 { 10533 UINT32 cache_line_size : 8 ; 10534 UINT32 mstr_lat_tmr : 8 ; 10535 UINT32 multi_function_device : 7 ; 10536 UINT32 hdr_type : 1 ; 10537 UINT32 bist : 8 ; 10538 } Bits; 10539 10540 10541 UINT32 UInt32; 10542 10543 } PCIE_EP_PCI_CFG_HDR3_U; 10544 10545 10546 10547 10548 typedef union tagPciCfgHdr4 10549 { 10550 10551 struct 10552 { 10553 UINT32 sbar01_space_inicator : 1 ; 10554 UINT32 sbar01_type : 2 ; 10555 UINT32 sbar01_prefetchable : 1 ; 10556 UINT32 sbar01_lower : 28 ; 10557 } Bits; 10558 10559 10560 UINT32 UInt32; 10561 10562 } PCIE_EP_PCI_CFG_HDR4_U; 10563 10564 10565 10566 10567 typedef union tagPciCfgHdr6 10568 { 10569 10570 struct 10571 { 10572 UINT32 sbar23_space_inicator : 1 ; 10573 UINT32 sbar23_type : 2 ; 10574 UINT32 sbar23_prefetchable : 1 ; 10575 UINT32 Reserved_4 : 8 ; 10576 UINT32 sbar23_lower : 20 ; 10577 } Bits; 10578 10579 10580 UINT32 UInt32; 10581 10582 } PCIE_EP_PCI_CFG_HDR6_U; 10583 10584 typedef union tagPciLinkTimeOut 10585 { 10586 10587 struct 10588 { 10589 UINT32 link_timeout_prepriod_default : 8 ; 10590 UINT32 link_timeout_enable_default : 1 ; 10591 UINT32 Reserved_4 : 23 ; 10592 } Bits; 10593 10594 10595 UINT32 UInt32; 10596 10597 } PCIE_EP_LINK_TIMEOUT_OFF_U; 10598 10599 10600 10601 10602 10603 typedef union tagPciCfgHdr8 10604 { 10605 10606 struct 10607 { 10608 UINT32 sbar45_space_inicator : 1 ; 10609 UINT32 sbar45_type : 2 ; 10610 UINT32 sbar45_prefetchable : 1 ; 10611 UINT32 Reserved_5 : 8 ; 10612 UINT32 sbar45_lower : 20 ; 10613 } Bits; 10614 10615 10616 UINT32 UInt32; 10617 10618 } PCIE_EP_PCI_CFG_HDR8_U; 10619 10620 10621 10622 10623 typedef union tagPciCfgHdr11 10624 { 10625 10626 struct 10627 { 10628 UINT32 subsystem_vendor_id : 16 ; 10629 UINT32 subsystemid : 16 ; 10630 } Bits; 10631 10632 10633 UINT32 UInt32; 10634 10635 } PCIE_EP_PCI_CFG_HDR11_U; 10636 10637 10638 10639 10640 typedef union tagPciCfgHdr13 10641 { 10642 10643 struct 10644 { 10645 UINT32 capptr : 8 ; 10646 UINT32 Reserved_6 : 24 ; 10647 } Bits; 10648 10649 10650 UINT32 UInt32; 10651 10652 } PCIE_EP_PCI_CFG_HDR13_U; 10653 10654 10655 10656 10657 typedef union tagPciCfgHdr15 10658 { 10659 10660 struct 10661 { 10662 UINT32 int_line : 8 ; 10663 UINT32 int_pin : 8 ; 10664 UINT32 Min_Grant : 8 ; 10665 UINT32 Max_Latency : 8 ; 10666 } Bits; 10667 10668 10669 UINT32 UInt32; 10670 10671 } PCIE_EP_PCI_CFG_HDR15_U; 10672 10673 10674 10675 10676 typedef union tagPciMsiCap0 10677 { 10678 10679 struct 10680 { 10681 UINT32 msi_cap_id : 8 ; 10682 UINT32 next_capability_pointer : 8 ; 10683 UINT32 msi_enabled : 1 ; 10684 UINT32 multiple_message_capable : 3 ; 10685 UINT32 multiple_message_enabled : 3 ; 10686 UINT32 msi_64_en : 1 ; 10687 UINT32 pvm_en : 1 ; 10688 UINT32 message_control_register : 7 ; 10689 } Bits; 10690 10691 10692 UINT32 UInt32; 10693 10694 } PCIE_EP_PCI_MSI_CAP0_U; 10695 10696 10697 10698 10699 typedef union tagPciMsiCap1 10700 { 10701 10702 struct 10703 { 10704 UINT32 Reserved_11 : 2 ; 10705 UINT32 msi_addr_low : 30 ; 10706 } Bits; 10707 10708 10709 UINT32 UInt32; 10710 10711 } PCIE_EP_PCI_MSI_CAP1_U; 10712 10713 10714 10715 10716 typedef union tagPciMsiCap3 10717 { 10718 10719 struct 10720 { 10721 UINT32 msi_data : 16 ; 10722 UINT32 Reserved_12 : 16 ; 10723 } Bits; 10724 10725 10726 UINT32 UInt32; 10727 10728 } PCIE_EP_PCI_MSI_CAP3_U; 10729 10730 10731 10732 10733 typedef union tagPcieCap0 10734 { 10735 10736 struct 10737 { 10738 UINT32 pcie_cap_id : 8 ; 10739 UINT32 pcie_next_ptr : 8 ; 10740 UINT32 pcie_capability_version : 4 ; 10741 UINT32 device_port_type : 4 ; 10742 UINT32 slot_implemented : 1 ; 10743 UINT32 interrupt_message_number : 5 ; 10744 UINT32 Reserved_13 : 2 ; 10745 } Bits; 10746 10747 10748 UINT32 UInt32; 10749 10750 } PCIE_EP_PCIE_CAP0_U; 10751 10752 10753 10754 10755 typedef union tagPcieCap1 10756 { 10757 10758 struct 10759 { 10760 UINT32 max_payload_size_supported : 3 ; 10761 UINT32 phantom_function_supported : 2 ; 10762 UINT32 extended_tagfield_supported : 1 ; 10763 UINT32 endpoint_l0sacceptable_latency : 3 ; 10764 UINT32 endpoint_l1acceptable_latency : 3 ; 10765 UINT32 undefined : 3 ; 10766 UINT32 Reserved_16 : 3 ; 10767 UINT32 captured_slot_power_limit_value : 8 ; 10768 UINT32 captured_slot_power_limit_scale : 2 ; 10769 UINT32 function_level_reset : 1 ; 10770 UINT32 Reserved_15 : 3 ; 10771 } Bits; 10772 10773 10774 UINT32 UInt32; 10775 10776 } PCIE_EP_PCIE_CAP1_U; 10777 10778 10779 10780 10781 typedef union tagPcieCap2 10782 { 10783 10784 struct 10785 { 10786 UINT32 correctable_error_reporting_enable : 1 ; 10787 UINT32 non_fatal_error_reporting_enable : 1 ; 10788 UINT32 fatal_error_reporting_enable : 1 ; 10789 UINT32 urenable : 1 ; 10790 UINT32 enable_relaxed_ordering : 1 ; 10791 UINT32 max_payload_size : 3 ; 10792 UINT32 extended_tagfieldenable : 1 ; 10793 UINT32 phantom_function_enable : 1 ; 10794 UINT32 auxpowerpmenable : 1 ; 10795 UINT32 enablenosnoop : 1 ; 10796 UINT32 max_read_request_size : 3 ; 10797 UINT32 Reserved_18 : 1 ; 10798 UINT32 correctableerrordetected : 1 ; 10799 UINT32 non_fatalerrordetected : 1 ; 10800 UINT32 fatalerrordetected : 1 ; 10801 UINT32 unsupportedrequestdetected : 1 ; 10802 UINT32 auxpowerdetected : 1 ; 10803 UINT32 transactionpending : 1 ; 10804 UINT32 Reserved_17 : 10 ; 10805 } Bits; 10806 10807 10808 UINT32 UInt32; 10809 10810 } PCIE_EP_PCIE_CAP2_U; 10811 10812 10813 10814 10815 typedef union tagPcieCap3 10816 { 10817 10818 struct 10819 { 10820 UINT32 max_link_speed : 4 ; 10821 UINT32 max_link_width : 6 ; 10822 UINT32 active_state_power_management : 2 ; 10823 UINT32 l0s_exitlatency : 3 ; 10824 UINT32 l1_exit_latency : 3 ; 10825 UINT32 clock_power_management : 1 ; 10826 UINT32 surprise_down_error_report_cap : 1 ; 10827 UINT32 data_link_layer_active_report_cap : 1 ; 10828 UINT32 link_bandwidth_noti_cap : 1 ; 10829 UINT32 aspm_option_compliance : 1 ; 10830 UINT32 Reserved_19 : 1 ; 10831 UINT32 port_number : 8 ; 10832 } Bits; 10833 10834 10835 UINT32 UInt32; 10836 10837 } PCIE_EP_PCIE_CAP3_U; 10838 10839 10840 10841 10842 typedef union tagPcieCap4 10843 { 10844 10845 struct 10846 { 10847 UINT32 active_state_power_management : 2 ; 10848 UINT32 Reserved_22 : 1 ; 10849 UINT32 rcb : 1 ; 10850 UINT32 link_disable : 1 ; 10851 UINT32 retrain_link : 1 ; 10852 UINT32 common_clock_config : 1 ; 10853 UINT32 extended_sync : 1 ; 10854 UINT32 enable_clock_pwr_management : 1 ; 10855 UINT32 hw_auto_width_disable : 1 ; 10856 UINT32 link_bandwidth_management_int_en : 1 ; 10857 UINT32 link_auto_bandwidth_int_en : 1 ; 10858 UINT32 Reserved_21 : 4 ; 10859 UINT32 current_link_speed : 4 ; 10860 UINT32 negotiated_link_width : 6 ; 10861 UINT32 Reserved_20 : 1 ; 10862 UINT32 link_training : 1 ; 10863 UINT32 slot_clock_configration : 1 ; 10864 UINT32 data_link_layer_active : 1 ; 10865 UINT32 link_bandwidth_management_status : 1 ; 10866 UINT32 link_auto_bandwidth_status : 1 ; 10867 } Bits; 10868 10869 10870 UINT32 UInt32; 10871 10872 } PCIE_EP_PCIE_CAP4_U; 10873 10874 10875 10876 10877 typedef union tagPcieCap5 10878 { 10879 10880 struct 10881 { 10882 UINT32 attentioonbuttonpresent : 1 ; 10883 UINT32 powercontrollerpresent : 1 ; 10884 UINT32 mrlsensorpresent : 1 ; 10885 UINT32 attentionindicatorpresent : 1 ; 10886 UINT32 powerindicatorpresent : 1 ; 10887 UINT32 hot_plugsurprise : 1 ; 10888 UINT32 hot_plugcapable : 1 ; 10889 UINT32 slotpowerlimitvalue : 8 ; 10890 UINT32 slotpowerlimitscale : 2 ; 10891 UINT32 electromechanicalinterlockpresen : 1 ; 10892 UINT32 no_cmd_complete_support : 1 ; 10893 UINT32 phy_slot_number : 13 ; 10894 } Bits; 10895 10896 10897 UINT32 UInt32; 10898 10899 } PCIE_EP_PCIE_CAP5_U; 10900 10901 10902 10903 10904 10905 typedef union tagPcieCap6 10906 { 10907 10908 struct 10909 { 10910 UINT32 attentionbuttonpressedenable : 1 ; 10911 UINT32 powerfaultdetectedenable : 1 ; 10912 UINT32 mrlsensorchangedenable : 1 ; 10913 UINT32 presencedetectchangedenable : 1 ; 10914 UINT32 commandcompletedinterruptenable : 1 ; 10915 UINT32 hot_pluginterruptenable : 1 ; 10916 UINT32 attentionindicatorcontrol : 2 ; 10917 UINT32 powerindicatorcontrol : 2 ; 10918 UINT32 powercontrollercontrol : 1 ; 10919 UINT32 electromechanicalinterlockcontrol : 1 ; 10920 UINT32 datalinklayerstatechangedenable : 1 ; 10921 UINT32 Reserved_23 : 3 ; 10922 UINT32 attentionbuttonpressed : 1 ; 10923 UINT32 powerfaultdetected : 1 ; 10924 UINT32 mrlsensorchanged : 1 ; 10925 UINT32 presencedetectchanged : 1 ; 10926 UINT32 commandcompleted : 1 ; 10927 UINT32 mrlsensorstate : 1 ; 10928 UINT32 presencedetectstate : 1 ; 10929 UINT32 electromechanicalinterlockstatus : 1 ; 10930 UINT32 datalinklayerstatechanged : 1 ; 10931 UINT32 slot_ctrl_status : 7 ; 10932 } Bits; 10933 10934 10935 UINT32 UInt32; 10936 10937 } PCIE_EP_PCIE_CAP6_U; 10938 10939 10940 10941 10942 typedef union tagPcieCap7 10943 { 10944 10945 struct 10946 { 10947 UINT32 systemerroroncorrectableerrorenable : 1 ; 10948 UINT32 systemerroronnon_fatalerrorenable : 1 ; 10949 UINT32 systemerroronfatalerrorenable : 1 ; 10950 UINT32 pmeinterruptenable : 1 ; 10951 UINT32 crssoftwarevisibilityenable : 1 ; 10952 UINT32 Reserved_24 : 11 ; 10953 UINT32 crssoftwarevisibility : 1 ; 10954 UINT32 root_cap : 15 ; 10955 } Bits; 10956 10957 10958 UINT32 UInt32; 10959 10960 } PCIE_EP_PCIE_CAP7_U; 10961 10962 10963 10964 10965 typedef union tagPcieCap8 10966 { 10967 10968 struct 10969 { 10970 UINT32 pmerequesterid : 16 ; 10971 UINT32 pmestatus : 1 ; 10972 UINT32 pmepending : 1 ; 10973 UINT32 root_status : 14 ; 10974 } Bits; 10975 10976 10977 UINT32 UInt32; 10978 10979 } PCIE_EP_PCIE_CAP8_U; 10980 10981 10982 10983 10984 typedef union tagPcieCap9 10985 { 10986 10987 struct 10988 { 10989 UINT32 completiontimeoutrangessupported : 4 ; 10990 UINT32 completiontimeoutdisablesupported : 1 ; 10991 UINT32 ariforwardingsupported : 1 ; 10992 UINT32 atomicoproutingsupported : 1 ; 10993 UINT32 _2_bitatomicopcompletersupported : 1 ; 10994 UINT32 _4_bitatomicopcompletersupported : 1 ; 10995 UINT32 _28_bitcascompletersupported : 1 ; 10996 UINT32 noro_enabledpr_prpassing : 1 ; 10997 UINT32 Reserved_25 : 1 ; 10998 UINT32 tphcompletersupported : 2 ; 10999 UINT32 dev_cap2 : 18 ; 11000 } Bits; 11001 11002 11003 UINT32 UInt32; 11004 11005 } PCIE_EP_PCIE_CAP9_U; 11006 11007 11008 11009 11010 typedef union tagPcieCap10 11011 { 11012 11013 struct 11014 { 11015 UINT32 completiontimeoutvalue : 4 ; 11016 UINT32 completiontimeoutdisable : 1 ; 11017 UINT32 ariforwardingsupported : 1 ; 11018 UINT32 atomicoprequesterenable : 1 ; 11019 UINT32 atomicopegressblocking : 1 ; 11020 UINT32 idorequestenable : 1 ; 11021 UINT32 idocompletionenable : 1 ; 11022 UINT32 dev_ctrl2 : 22 ; 11023 } Bits; 11024 11025 11026 UINT32 UInt32; 11027 11028 } PCIE_EP_PCIE_CAP10_U; 11029 11030 11031 11032 11033 typedef union tagPcieCap11 11034 { 11035 11036 struct 11037 { 11038 UINT32 Reserved_27 : 1 ; 11039 UINT32 gen1_suport : 1 ; 11040 UINT32 gen2_suport : 1 ; 11041 UINT32 gen3_suport : 1 ; 11042 UINT32 Reserved_26 : 4 ; 11043 UINT32 crosslink_supported : 1 ; 11044 UINT32 link_cap2 : 23 ; 11045 } Bits; 11046 11047 11048 UINT32 UInt32; 11049 11050 } PCIE_EP_PCIE_CAP11_U; 11051 11052 11053 11054 11055 typedef union tagPcieCap12 11056 { 11057 11058 struct 11059 { 11060 UINT32 targetlinkspeed : 4 ; 11061 UINT32 entercompliance : 1 ; 11062 UINT32 hardwareautonomousspeeddisa : 1 ; 11063 UINT32 selectablede_empha : 1 ; 11064 UINT32 transmitmargin : 3 ; 11065 UINT32 _entermodifiedcompliance : 1 ; 11066 UINT32 compliancesos : 1 ; 11067 UINT32 de_emphasislevel : 4 ; 11068 UINT32 currentde_emphasislevel : 1 ; 11069 UINT32 equalizationcomplete : 1 ; 11070 UINT32 equalizationphase1successful : 1 ; 11071 UINT32 equalizationphase2successful : 1 ; 11072 UINT32 equalizationphase3successful : 1 ; 11073 UINT32 linkequalizationrequest : 1 ; 11074 UINT32 link_ctrl2_status2 : 10 ; 11075 } Bits; 11076 11077 11078 UINT32 UInt32; 11079 11080 } PCIE_EP_PCIE_CAP12_U; 11081 11082 11083 11084 11085 typedef union tagSlotCap 11086 { 11087 11088 struct 11089 { 11090 UINT32 slotnumberingcapabilitiesid : 8 ; 11091 UINT32 nextcapabilitypointer : 8 ; 11092 UINT32 add_incardslotsprovided : 5 ; 11093 UINT32 firstinchassis : 1 ; 11094 UINT32 Reserved_28 : 2 ; 11095 UINT32 slot_cap : 8 ; 11096 } Bits; 11097 11098 11099 UINT32 UInt32; 11100 11101 } PCIE_EP_SLOT_CAP_U; 11102 11103 11104 11105 11106 typedef union tagAerCap0 11107 { 11108 11109 struct 11110 { 11111 UINT32 pciexpressextendedcapabilityid : 16 ; 11112 UINT32 capabilityversion : 4 ; 11113 UINT32 aer_cap_hdr : 12 ; 11114 } Bits; 11115 11116 11117 UINT32 UInt32; 11118 11119 } PCIE_EP_AER_CAP0_U; 11120 11121 11122 11123 11124 typedef union tagAerCap1 11125 { 11126 11127 struct 11128 { 11129 UINT32 Reserved_34 : 1 ; 11130 UINT32 Reserved_33 : 3 ; 11131 UINT32 datalinkprotocolerrorsta : 1 ; 11132 UINT32 surprisedownerrorstatus : 1 ; 11133 UINT32 Reserved_32 : 6 ; 11134 UINT32 poisonedtlpstatu : 1 ; 11135 UINT32 flowcontrolprotocolerrorst : 1 ; 11136 UINT32 completiontimeouts : 1 ; 11137 UINT32 completerabortstatus : 1 ; 11138 UINT32 receiveroverflowstatus : 1 ; 11139 UINT32 malformedtlpstatus : 1 ; 11140 UINT32 ecrcerrorstatus : 1 ; 11141 UINT32 ecrcerrorstat : 1 ; 11142 UINT32 unsupportedrequesterrorstatus : 1 ; 11143 UINT32 Reserved_31 : 3 ; 11144 UINT32 atomicopegressblockedstatus : 1 ; 11145 UINT32 uncorr_err_status : 7 ; 11146 } Bits; 11147 11148 11149 UINT32 UInt32; 11150 11151 } PCIE_EP_AER_CAP1_U; 11152 11153 11154 11155 11156 typedef union tagAerCap2 11157 { 11158 11159 struct 11160 { 11161 UINT32 Reserved_38 : 1 ; 11162 UINT32 Reserved_37 : 3 ; 11163 UINT32 datalinkprotocolerrormask : 1 ; 11164 UINT32 surprisedownerrormask : 1 ; 11165 UINT32 Reserved_36 : 6 ; 11166 UINT32 poisonedtlpmask : 1 ; 11167 UINT32 flowcontrolprotocolerrormask : 1 ; 11168 UINT32 completiontimeoutmask : 1 ; 11169 UINT32 completerabortmask : 1 ; 11170 UINT32 unexpectedcompletionmask : 1 ; 11171 UINT32 receiveroverflowmask : 1 ; 11172 UINT32 malformedtlpmask : 1 ; 11173 UINT32 ecrcerrormask : 1 ; 11174 UINT32 unsupportedrequesterrormask : 1 ; 11175 UINT32 Reserved_35 : 3 ; 11176 UINT32 atomicopegressblockedmask : 1 ; 11177 UINT32 uncorr_err_mask : 7 ; 11178 } Bits; 11179 11180 11181 UINT32 UInt32; 11182 11183 } PCIE_EP_AER_CAP2_U; 11184 11185 11186 11187 11188 typedef union tagAerCap3 11189 { 11190 11191 struct 11192 { 11193 UINT32 Reserved_42 : 1 ; 11194 UINT32 Reserved_41 : 3 ; 11195 UINT32 datalinkprotocolerrorsever : 1 ; 11196 UINT32 surprisedownerrorseverity : 1 ; 11197 UINT32 Reserved_40 : 6 ; 11198 UINT32 poisonedtlpseverity : 1 ; 11199 UINT32 flowcontrolprotocolerrorseveri : 1 ; 11200 UINT32 completiontimeoutseverity : 1 ; 11201 UINT32 completerabortseverity : 1 ; 11202 UINT32 unexpectedcompletionseverity : 1 ; 11203 UINT32 receiveroverflowseverity : 1 ; 11204 UINT32 malformedtlpseverity : 1 ; 11205 UINT32 ecrcerrorseverity : 1 ; 11206 UINT32 unsupportedrequesterrorseverity : 1 ; 11207 UINT32 Reserved_39 : 3 ; 11208 UINT32 atomicopegressblockedseverity : 1 ; 11209 UINT32 uncorr_err_ser : 7 ; 11210 } Bits; 11211 11212 11213 UINT32 UInt32; 11214 11215 } PCIE_EP_AER_CAP3_U; 11216 11217 11218 11219 11220 typedef union tagAerCap4 11221 { 11222 11223 struct 11224 { 11225 UINT32 receivererrorstatus : 1 ; 11226 UINT32 Reserved_44 : 5 ; 11227 UINT32 badtlpstatus : 1 ; 11228 UINT32 baddllpstatus : 1 ; 11229 UINT32 replay_numrolloverstatus : 1 ; 11230 UINT32 Reserved_43 : 3 ; 11231 UINT32 replytimertimeoutstatus : 1 ; 11232 UINT32 advisorynon_fatalerrorstatus : 1 ; 11233 UINT32 corr_err_status : 18 ; 11234 } Bits; 11235 11236 11237 UINT32 UInt32; 11238 11239 } PCIE_EP_AER_CAP4_U; 11240 11241 11242 11243 11244 typedef union tagAerCap5 11245 { 11246 11247 struct 11248 { 11249 UINT32 receivererrormask : 1 ; 11250 UINT32 Reserved_46 : 5 ; 11251 UINT32 badtlpmask : 1 ; 11252 UINT32 baddllpmask : 1 ; 11253 UINT32 replay_numrollovermask : 1 ; 11254 UINT32 Reserved_45 : 3 ; 11255 UINT32 replytimertimeoutmask : 1 ; 11256 UINT32 advisorynon_fatalerrormask : 1 ; 11257 UINT32 corr_err_mask : 18 ; 11258 } Bits; 11259 11260 11261 UINT32 UInt32; 11262 11263 } PCIE_EP_AER_CAP5_U; 11264 11265 11266 11267 11268 typedef union tagAerCap6 11269 { 11270 11271 struct 11272 { 11273 UINT32 firsterrorpointer : 5 ; 11274 UINT32 ecrcgenerationcapability : 1 ; 11275 UINT32 ecrcgenerationenable : 1 ; 11276 UINT32 ecrccheckcapable : 1 ; 11277 UINT32 ecrccheckenable : 1 ; 11278 UINT32 adv_cap_ctrl : 23 ; 11279 } Bits; 11280 11281 11282 UINT32 UInt32; 11283 11284 } PCIE_EP_AER_CAP6_U; 11285 11286 11287 11288 11289 typedef union tagAerCap11 11290 { 11291 11292 struct 11293 { 11294 UINT32 correctableerrorreportingenable : 1 ; 11295 UINT32 non_fatalerrorreportingenable : 1 ; 11296 UINT32 fatalerrorreportingenable : 1 ; 11297 UINT32 root_err_cmd : 29 ; 11298 } Bits; 11299 11300 11301 UINT32 UInt32; 11302 11303 } PCIE_EP_AER_CAP11_U; 11304 11305 11306 11307 11308 typedef union tagAerCap12 11309 { 11310 11311 struct 11312 { 11313 UINT32 err_correceived : 1 ; 11314 UINT32 multipleerr_correceived : 1 ; 11315 UINT32 err_fatal_nonfatalreceived : 1 ; 11316 UINT32 multipleerr_fatal_nonfatalreceived : 1 ; 11317 UINT32 firstuncorrectablefatal : 1 ; 11318 UINT32 non_fatalerrormessagesreceived : 1 ; 11319 UINT32 fatalerrormessagesreceived : 1 ; 11320 UINT32 Reserved_47 : 20 ; 11321 UINT32 root_err_status : 5 ; 11322 } Bits; 11323 11324 11325 UINT32 UInt32; 11326 11327 } PCIE_EP_AER_CAP12_U; 11328 11329 11330 11331 11332 typedef union tagAerCap13 11333 { 11334 11335 struct 11336 { 11337 UINT32 err_corsourceidentification : 16 ; 11338 UINT32 err_src_id : 16 ; 11339 } Bits; 11340 11341 11342 UINT32 UInt32; 11343 11344 } PCIE_EP_AER_CAP13_U; 11345 11346 11347 11348 11349 typedef union tagVcCap0 11350 { 11351 11352 struct 11353 { 11354 UINT32 pciexpressextendedcapabilityid : 16 ; 11355 UINT32 capabilityversion : 4 ; 11356 UINT32 vc_cap_hdr : 12 ; 11357 } Bits; 11358 11359 11360 UINT32 UInt32; 11361 11362 } PCIE_EP_VC_CAP0_U; 11363 11364 11365 11366 11367 typedef union tagVcCap1 11368 { 11369 11370 struct 11371 { 11372 UINT32 extendedvccount : 3 ; 11373 UINT32 Reserved_50 : 1 ; 11374 UINT32 lowpriorityextendedvccount : 3 ; 11375 UINT32 Reserved_49 : 1 ; 11376 UINT32 referenceclock : 2 ; 11377 UINT32 portarbitrationtableentrysize : 2 ; 11378 UINT32 vc_cap1 : 20 ; 11379 } Bits; 11380 11381 11382 UINT32 UInt32; 11383 11384 } PCIE_EP_VC_CAP1_U; 11385 11386 11387 11388 11389 typedef union tagVcCap2 11390 { 11391 11392 struct 11393 { 11394 UINT32 vcarbitrationcapability : 8 ; 11395 UINT32 Reserved_51 : 16 ; 11396 UINT32 vc_cap2 : 8 ; 11397 } Bits; 11398 11399 11400 UINT32 UInt32; 11401 11402 } PCIE_EP_VC_CAP2_U; 11403 11404 11405 11406 11407 typedef union tagVcCap3 11408 { 11409 11410 struct 11411 { 11412 UINT32 loadvcarbitrationtable : 1 ; 11413 UINT32 vcarbitrationselect : 3 ; 11414 UINT32 Reserved_53 : 12 ; 11415 UINT32 arbitrationtablestatus : 1 ; 11416 UINT32 Reserved_52 : 15 ; 11417 } Bits; 11418 11419 11420 UINT32 UInt32; 11421 11422 } PCIE_EP_VC_CAP3_U; 11423 11424 11425 11426 11427 typedef union tagVcCap4 11428 { 11429 11430 struct 11431 { 11432 UINT32 portarbitrationcapability : 8 ; 11433 UINT32 Reserved_56 : 6 ; 11434 UINT32 Reserved_55 : 1 ; 11435 UINT32 rejectsnooptransactions : 1 ; 11436 UINT32 maximumtimeslots : 7 ; 11437 UINT32 Reserved_54 : 1 ; 11438 UINT32 vc_res_cap : 8 ; 11439 } Bits; 11440 11441 11442 UINT32 UInt32; 11443 11444 } PCIE_EP_VC_CAP4_U; 11445 11446 11447 11448 11449 typedef union tagVcCap5 11450 { 11451 11452 struct 11453 { 11454 UINT32 tc_vcmap : 8 ; 11455 UINT32 Reserved_59 : 8 ; 11456 UINT32 loadportarbitrationtable : 1 ; 11457 UINT32 portarbitrationselec : 3 ; 11458 UINT32 Reserved_58 : 4 ; 11459 UINT32 vcid : 3 ; 11460 UINT32 Reserved_57 : 4 ; 11461 UINT32 vc_res_ctrl : 1 ; 11462 } Bits; 11463 11464 11465 UINT32 UInt32; 11466 11467 } PCIE_EP_VC_CAP5_U; 11468 11469 11470 11471 11472 typedef union tagVcCap6 11473 { 11474 11475 struct 11476 { 11477 UINT32 Reserved_60 : 16 ; 11478 UINT32 portarbitrationtablestatus : 1 ; 11479 UINT32 vcnegotiationpending : 1 ; 11480 UINT32 vc_res_status : 14 ; 11481 } Bits; 11482 11483 11484 UINT32 UInt32; 11485 11486 } PCIE_EP_VC_CAP6_U; 11487 11488 11489 11490 11491 typedef union tagVcCap7 11492 { 11493 11494 struct 11495 { 11496 UINT32 portarbitrationcapability : 8 ; 11497 UINT32 Reserved_63 : 6 ; 11498 UINT32 Reserved_62 : 1 ; 11499 UINT32 rejectsnooptransactions : 1 ; 11500 UINT32 maximumtimeslots : 7 ; 11501 UINT32 Reserved_61 : 1 ; 11502 UINT32 vc_res_cap0 : 8 ; 11503 } Bits; 11504 11505 11506 UINT32 UInt32; 11507 11508 } PCIE_EP_VC_CAP7_U; 11509 11510 11511 11512 11513 typedef union tagVcCap8 11514 { 11515 11516 struct 11517 { 11518 UINT32 tc_vcmap : 8 ; 11519 UINT32 Reserved_66 : 8 ; 11520 UINT32 loadportarbitrationtable : 1 ; 11521 UINT32 portarbitrationselect : 3 ; 11522 UINT32 Reserved_65 : 4 ; 11523 UINT32 vcid : 3 ; 11524 UINT32 Reserved_64 : 4 ; 11525 UINT32 vc_res_ctrl0 : 1 ; 11526 } Bits; 11527 11528 11529 UINT32 UInt32; 11530 11531 } PCIE_EP_VC_CAP8_U; 11532 11533 11534 11535 11536 typedef union tagVcCap9 11537 { 11538 11539 struct 11540 { 11541 UINT32 Reserved_67 : 16 ; 11542 UINT32 arbitrationtablestatus : 1 ; 11543 UINT32 vcnegotiationpending : 1 ; 11544 UINT32 vc_res_status0 : 14 ; 11545 } Bits; 11546 11547 11548 UINT32 UInt32; 11549 11550 } PCIE_EP_VC_CAP9_U; 11551 11552 11553 11554 11555 typedef union tagPortLogic0 11556 { 11557 11558 struct 11559 { 11560 UINT32 ack_lat_timer : 16 ; 11561 UINT32 replay_timer : 16 ; 11562 } Bits; 11563 11564 11565 UINT32 UInt32; 11566 11567 } PCIE_EP_PORT_LOGIC0_U; 11568 11569 11570 11571 11572 typedef union tagPortLogic2 11573 { 11574 11575 struct 11576 { 11577 UINT32 linknumber : 8 ; 11578 UINT32 Reserved_70 : 7 ; 11579 UINT32 forcelink : 1 ; 11580 UINT32 linkstate : 6 ; 11581 UINT32 Reserved_69 : 2 ; 11582 UINT32 port_force_link : 8 ; 11583 } Bits; 11584 11585 11586 UINT32 UInt32; 11587 11588 } PCIE_EP_PORT_LOGIC2_U; 11589 11590 11591 11592 11593 typedef union tagPortLogic3 11594 { 11595 11596 struct 11597 { 11598 UINT32 ackfrequency : 8 ; 11599 UINT32 n_fts : 8 ; 11600 UINT32 commonclockn_fts : 8 ; 11601 UINT32 l0sentrancelatency : 3 ; 11602 UINT32 l1entrancelatency : 3 ; 11603 UINT32 enteraspml1withoutreceiveinl0s : 1 ; 11604 UINT32 ack_aspm : 1 ; 11605 } Bits; 11606 11607 11608 UINT32 UInt32; 11609 11610 } PCIE_EP_PORT_LOGIC3_U; 11611 11612 11613 11614 11615 typedef union tagPortLogic4 11616 { 11617 11618 struct 11619 { 11620 UINT32 vendorspecificdllprequest : 1 ; 11621 UINT32 scrambledisable : 1 ; 11622 UINT32 loopbackenable : 1 ; 11623 UINT32 resetassert : 1 ; 11624 UINT32 Reserved_73 : 1 ; 11625 UINT32 dlllinkenable : 1 ; 11626 UINT32 Reserved_72 : 1 ; 11627 UINT32 fastlinkmode : 1 ; 11628 UINT32 Reserved_71 : 8 ; 11629 UINT32 linkmodeenable : 6 ; 11630 UINT32 crosslinkenable : 1 ; 11631 UINT32 crosslinkactive : 1 ; 11632 UINT32 port_link_ctrl : 8 ; 11633 } Bits; 11634 11635 11636 UINT32 UInt32; 11637 11638 } PCIE_EP_PORT_LOGIC4_U; 11639 11640 11641 11642 11643 typedef union tagPortLogic5 11644 { 11645 11646 struct 11647 { 11648 UINT32 insertlaneskewfortransmit : 24 ; 11649 UINT32 flowcontroldisable : 1 ; 11650 UINT32 ack_nakdisable : 1 ; 11651 UINT32 Reserved_75 : 5 ; 11652 UINT32 lane_skew : 1 ; 11653 } Bits; 11654 11655 11656 UINT32 UInt32; 11657 11658 } PCIE_EP_PORT_LOGIC5_U; 11659 11660 11661 11662 11663 typedef union tagPortLogic6 11664 { 11665 11666 struct 11667 { 11668 UINT32 numberoftssymbols : 4 ; 11669 UINT32 Reserved_77 : 4 ; 11670 UINT32 numberofskpsymbols : 3 ; 11671 UINT32 Reserved_76 : 3 ; 11672 UINT32 timermodifierforreplaytimer : 5 ; 11673 UINT32 timermodifierforack_naklatencytimer : 5 ; 11674 UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ; 11675 UINT32 sym_num : 3 ; 11676 } Bits; 11677 11678 11679 UINT32 UInt32; 11680 11681 } PCIE_EP_PORT_LOGIC6_U; 11682 11683 11684 11685 11686 typedef union tagPortLogic7 11687 { 11688 11689 struct 11690 { 11691 UINT32 vc0posteddataqueuedepth : 11 ; 11692 UINT32 Reserved_78 : 4 ; 11693 UINT32 sym_timer : 1 ; 11694 UINT32 maskfunctionmismatchfilteringfo : 1 ; 11695 UINT32 maskpoisonedtlpfiltering : 1 ; 11696 UINT32 maskbarmatchfiltering : 1 ; 11697 UINT32 masktype1configurationrequestfiltering : 1 ; 11698 UINT32 masklockedrequestfiltering : 1 ; 11699 UINT32 masktagerrorrulesforreceivedcompletions : 1 ; 11700 UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ; 11701 UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ; 11702 UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ; 11703 UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ; 11704 UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ; 11705 UINT32 maske_crcerror_filtering : 1 ; 11706 UINT32 maske_crcerror_filtering_forcompletions : 1 ; 11707 UINT32 message_control : 1 ; 11708 UINT32 maskfilteringofreceived : 1 ; 11709 UINT32 flt_mask1 : 1 ; 11710 } Bits; 11711 11712 11713 UINT32 UInt32; 11714 11715 } PCIE_EP_PORT_LOGIC7_U; 11716 11717 11718 11719 11720 typedef union tagPortLogic8 11721 { 11722 11723 struct 11724 { 11725 UINT32 cx_flt_mask_venmsg0_drop : 1 ; 11726 UINT32 cx_flt_mask_venmsg1_drop : 1 ; 11727 UINT32 cx_flt_mask_dabort_4ucpl : 1 ; 11728 UINT32 cx_flt_mask_handle_flush : 1 ; 11729 UINT32 flt_mask2 : 28 ; 11730 } Bits; 11731 11732 11733 UINT32 UInt32; 11734 11735 } PCIE_EP_PORT_LOGIC8_U; 11736 11737 11738 11739 11740 typedef union tagPortLogic9 11741 { 11742 11743 struct 11744 { 11745 UINT32 amba_multi_outbound_decomp_np : 1 ; 11746 UINT32 amba_obnp_ctrl : 31 ; 11747 } Bits; 11748 11749 11750 UINT32 UInt32; 11751 11752 } PCIE_EP_PORT_LOGIC9_U; 11753 11754 11755 11756 11757 typedef union tagPortLogic12 11758 { 11759 11760 struct 11761 { 11762 UINT32 transmitposteddatafccredits : 12 ; 11763 UINT32 transmitpostedheaderfccredits : 8 ; 11764 UINT32 tx_pfc_status : 12 ; 11765 } Bits; 11766 11767 11768 UINT32 UInt32; 11769 11770 } PCIE_EP_PORT_LOGIC12_U; 11771 11772 11773 11774 11775 typedef union tagPortLogic13 11776 { 11777 11778 struct 11779 { 11780 UINT32 transmitnon_posteddatafccredits : 12 ; 11781 UINT32 transmitnon_postedheaderfccredits : 8 ; 11782 UINT32 tx_npfc_status : 12 ; 11783 } Bits; 11784 11785 11786 UINT32 UInt32; 11787 11788 } PCIE_EP_PORT_LOGIC13_U; 11789 11790 11791 11792 11793 typedef union tagPortLogic14 11794 { 11795 11796 struct 11797 { 11798 UINT32 transmitcompletiondatafccredits : 12 ; 11799 UINT32 transmitcompletionheaderfccredits : 8 ; 11800 UINT32 tx_cplfc_status : 12 ; 11801 } Bits; 11802 11803 11804 UINT32 UInt32; 11805 11806 } PCIE_EP_PORT_LOGIC14_U; 11807 11808 11809 11810 11811 typedef union tagPortLogic15 11812 { 11813 11814 struct 11815 { 11816 UINT32 rx_tlp_fc_credit_not_retured : 1 ; 11817 UINT32 tx_retry_buf_not_empty : 1 ; 11818 UINT32 rx_queue_not_empty : 1 ; 11819 UINT32 Reserved_80 : 13 ; 11820 UINT32 fc_latency_timer_override_value : 13 ; 11821 UINT32 Reserved_79 : 2 ; 11822 UINT32 fc_latency_timer_override_en : 1 ; 11823 } Bits; 11824 11825 11826 UINT32 UInt32; 11827 11828 } PCIE_EP_PORT_LOGIC15_U; 11829 11830 11831 11832 11833 typedef union tagPortLogic16 11834 { 11835 11836 struct 11837 { 11838 UINT32 vc0posteddatacredits : 12 ; 11839 UINT32 vc0postedheadercredits : 8 ; 11840 UINT32 Reserved_82 : 1 ; 11841 UINT32 vc0_postedtlpqueuemode : 1 ; 11842 UINT32 vc0postedtlpqueuemode : 1 ; 11843 UINT32 vc0postedtlpqueuemo : 1 ; 11844 UINT32 Reserved_81 : 6 ; 11845 UINT32 tlptypeorderingforvc0 : 1 ; 11846 UINT32 rx_pque_ctrl : 1 ; 11847 } Bits; 11848 11849 11850 UINT32 UInt32; 11851 11852 } PCIE_EP_PORT_LOGIC16_U; 11853 11854 11855 11856 11857 typedef union tagPortLogic17 11858 { 11859 11860 struct 11861 { 11862 UINT32 vc0non_posteddatacredits : 12 ; 11863 UINT32 vc0non_postedheadercredits : 8 ; 11864 UINT32 rx_npque_ctrl : 12 ; 11865 } Bits; 11866 11867 11868 UINT32 UInt32; 11869 11870 } PCIE_EP_PORT_LOGIC17_U; 11871 11872 11873 11874 11875 typedef union tagPortLogic18 11876 { 11877 11878 struct 11879 { 11880 UINT32 vco_comp_data_credits : 12 ; 11881 UINT32 vc0_cpl_header_credt : 8 ; 11882 UINT32 Reserved_84 : 12 ; 11883 } Bits; 11884 11885 11886 UINT32 UInt32; 11887 11888 } PCIE_EP_PORT_LOGIC18_U; 11889 11890 11891 11892 11893 typedef union tagPortLogic19 11894 { 11895 11896 struct 11897 { 11898 UINT32 vco_posted_data_que_path : 14 ; 11899 UINT32 Reserved_85 : 2 ; 11900 UINT32 vco_posted_head_queue_depth : 10 ; 11901 UINT32 vc_pbuf_ctrl : 6 ; 11902 } Bits; 11903 11904 11905 UINT32 UInt32; 11906 11907 } PCIE_EP_PORT_LOGIC19_U; 11908 11909 11910 11911 11912 typedef union tagPortLogic20 11913 { 11914 11915 struct 11916 { 11917 UINT32 vco_np_data_que_depth : 14 ; 11918 UINT32 Reserved_87 : 2 ; 11919 UINT32 vco_np_header_que_depth : 10 ; 11920 UINT32 vc_npbuf_ctrl : 6 ; 11921 } Bits; 11922 11923 11924 UINT32 UInt32; 11925 11926 } PCIE_EP_PORT_LOGIC20_U; 11927 11928 11929 11930 11931 typedef union tagPortLogic21 11932 { 11933 11934 struct 11935 { 11936 UINT32 vco_comp_data_queue_depth : 14 ; 11937 UINT32 Reserved_89 : 2 ; 11938 UINT32 vco_posted_head_queue_depth : 10 ; 11939 UINT32 Reserved_88 : 6 ; 11940 } Bits; 11941 11942 11943 UINT32 UInt32; 11944 11945 } PCIE_EP_PORT_LOGIC21_U; 11946 11947 11948 11949 11950 typedef union tagPortLogic22 11951 { 11952 11953 struct 11954 { 11955 UINT32 n_fts : 8 ; 11956 UINT32 pre_determ_num_of_lane : 9 ; 11957 UINT32 det_sp_change : 1 ; 11958 UINT32 config_phy_tx_sw : 1 ; 11959 UINT32 config_tx_comp_rcv_bit : 1 ; 11960 UINT32 set_emp_level : 1 ; 11961 UINT32 Reserved_90 : 11 ; 11962 } Bits; 11963 11964 11965 UINT32 UInt32; 11966 11967 } PCIE_EP_PORT_LOGIC22_U; 11968 11969 11970 11971 11972 typedef union tagPortlogic25 11973 { 11974 11975 struct 11976 { 11977 UINT32 remote_rd_req_size : 3 ; 11978 UINT32 Reserved_93 : 5 ; 11979 UINT32 remote_max_brd_tag : 8 ; 11980 UINT32 Reserved_92 : 16 ; 11981 } Bits; 11982 11983 11984 UINT32 UInt32; 11985 11986 } PCIE_EP_PORTLOGIC25_U; 11987 11988 11989 11990 11991 typedef union tagPortlogic26 11992 { 11993 11994 struct 11995 { 11996 UINT32 resize_master_resp_compser : 1 ; 11997 UINT32 axi_ctrl1 : 31 ; 11998 } Bits; 11999 12000 12001 UINT32 UInt32; 12002 12003 } PCIE_EP_PORTLOGIC26_U; 12004 12005 12006 12007 12008 typedef union tagPortlogic54 12009 { 12010 12011 struct 12012 { 12013 UINT32 region_index : 4 ; 12014 UINT32 Reserved_94 : 27 ; 12015 UINT32 iatu_view : 1 ; 12016 } Bits; 12017 12018 12019 UINT32 UInt32; 12020 12021 } PCIE_EP_PORTLOGIC54_U; 12022 12023 12024 12025 12026 typedef union tagPortlogic55 12027 { 12028 12029 struct 12030 { 12031 UINT32 iatu1_type : 5 ; 12032 UINT32 iatu1_tc : 3 ; 12033 UINT32 iatu1_td : 1 ; 12034 UINT32 iatu1_attr : 2 ; 12035 UINT32 Reserved_98 : 5 ; 12036 UINT32 iatu1_at : 2 ; 12037 UINT32 Reserved_97 : 2 ; 12038 UINT32 iatu1_id : 3 ; 12039 UINT32 Reserved_96 : 9 ; 12040 } Bits; 12041 12042 12043 UINT32 UInt32; 12044 12045 } PCIE_EP_PORTLOGIC55_U; 12046 12047 12048 12049 12050 typedef union tagPortlogic56 12051 { 12052 12053 struct 12054 { 12055 UINT32 iatu2_type : 8 ; 12056 UINT32 iatu2_bar_num : 3 ; 12057 UINT32 Reserved_102 : 3 ; 12058 UINT32 iatu2_tc_match_en : 1 ; 12059 UINT32 iatu2_td_match_en : 1 ; 12060 UINT32 iatu2_attr_match_en : 1 ; 12061 UINT32 Reserved_101 : 1 ; 12062 UINT32 iatu2_at_match_en : 1 ; 12063 UINT32 iatu2_func_num_match_en : 1 ; 12064 UINT32 iatu2_virtual_func_num_match_en : 1 ; 12065 UINT32 message_code_match_en : 1 ; 12066 UINT32 Reserved_100 : 2 ; 12067 UINT32 iatu2_response_code : 2 ; 12068 UINT32 Reserved_99 : 1 ; 12069 UINT32 iatu2_fuzzy_type_match_mode : 1 ; 12070 UINT32 iatu2_cfg_shift_mode : 1 ; 12071 UINT32 iatu2_ivert_mode : 1 ; 12072 UINT32 iatu2_match_mode : 1 ; 12073 UINT32 iatu2_region_en : 1 ; 12074 } Bits; 12075 12076 12077 UINT32 UInt32; 12078 12079 } PCIE_EP_PORTLOGIC56_U; 12080 12081 12082 12083 12084 typedef union tagPortlogic57 12085 { 12086 12087 struct 12088 { 12089 UINT32 iatu_start_low : 12 ; 12090 UINT32 iatu_start_high : 20 ; 12091 } Bits; 12092 12093 12094 UINT32 UInt32; 12095 12096 } PCIE_EP_PORTLOGIC57_U; 12097 12098 12099 12100 12101 typedef union tagPortlogic59 12102 { 12103 12104 struct 12105 { 12106 UINT32 iatu_limit_low : 12 ; 12107 UINT32 iatu_limit_high : 20 ; 12108 } Bits; 12109 12110 12111 UINT32 UInt32; 12112 12113 } PCIE_EP_PORTLOGIC59_U; 12114 12115 12116 12117 12118 typedef union tagPortlogic60 12119 { 12120 12121 struct 12122 { 12123 UINT32 xlated_addr_high : 12 ; 12124 UINT32 xlated_addr_low : 20 ; 12125 } Bits; 12126 12127 12128 UINT32 UInt32; 12129 12130 } PCIE_EP_PORTLOGIC60_U; 12131 12132 12133 12134 12135 typedef union tagPortlogic62 12136 { 12137 12138 struct 12139 { 12140 UINT32 dma_wr_eng_en : 1 ; 12141 UINT32 dma_wr_ena : 31 ; 12142 } Bits; 12143 12144 12145 UINT32 UInt32; 12146 12147 } PCIE_EP_PORTLOGIC62_U; 12148 12149 12150 12151 12152 typedef union tagPortlogic63 12153 { 12154 12155 struct 12156 { 12157 UINT32 wr_doorbell_num : 3 ; 12158 UINT32 Reserved_104 : 28 ; 12159 UINT32 dma_wr_dbell_stop : 1 ; 12160 } Bits; 12161 12162 12163 UINT32 UInt32; 12164 12165 } PCIE_EP_PORTLOGIC63_U; 12166 12167 12168 12169 12170 typedef union tagPortlogic64 12171 { 12172 12173 struct 12174 { 12175 UINT32 dma_read_eng_en : 1 ; 12176 UINT32 Reserved_105 : 31 ; 12177 } Bits; 12178 12179 12180 UINT32 UInt32; 12181 12182 } PCIE_EP_PORTLOGIC64_U; 12183 12184 12185 12186 12187 typedef union tagPortlogic65 12188 { 12189 12190 struct 12191 { 12192 UINT32 rd_doorbell_num : 3 ; 12193 UINT32 Reserved_107 : 28 ; 12194 UINT32 dma_rd_dbell_stop : 1 ; 12195 } Bits; 12196 12197 12198 UINT32 UInt32; 12199 12200 } PCIE_EP_PORTLOGIC65_U; 12201 12202 12203 12204 12205 typedef union tagPortlogic66 12206 { 12207 12208 struct 12209 { 12210 UINT32 done_int_status : 8 ; 12211 UINT32 Reserved_109 : 8 ; 12212 UINT32 abort_int_status : 8 ; 12213 UINT32 Reserved_108 : 8 ; 12214 } Bits; 12215 12216 12217 UINT32 UInt32; 12218 12219 } PCIE_EP_PORTLOGIC66_U; 12220 12221 12222 12223 12224 typedef union tagPortlogic67 12225 { 12226 12227 struct 12228 { 12229 UINT32 done_int_mask : 8 ; 12230 UINT32 Reserved_112 : 8 ; 12231 UINT32 abort_int_mask : 8 ; 12232 UINT32 Reserved_111 : 8 ; 12233 } Bits; 12234 12235 12236 UINT32 UInt32; 12237 12238 } PCIE_EP_PORTLOGIC67_U; 12239 12240 12241 12242 12243 typedef union tagPortlogic68 12244 { 12245 12246 struct 12247 { 12248 UINT32 done_int_clr : 8 ; 12249 UINT32 Reserved_115 : 8 ; 12250 UINT32 abort_int_clr : 8 ; 12251 UINT32 Reserved_114 : 8 ; 12252 } Bits; 12253 12254 12255 UINT32 UInt32; 12256 12257 } PCIE_EP_PORTLOGIC68_U; 12258 12259 12260 12261 12262 typedef union tagPortlogic69 12263 { 12264 12265 struct 12266 { 12267 UINT32 app_rd_err_det : 8 ; 12268 UINT32 Reserved_117 : 8 ; 12269 UINT32 ll_element_fetch_err_det : 8 ; 12270 UINT32 Reserved_116 : 8 ; 12271 } Bits; 12272 12273 12274 UINT32 UInt32; 12275 12276 } PCIE_EP_PORTLOGIC69_U; 12277 12278 12279 12280 12281 typedef union tagPortlogic74 12282 { 12283 12284 struct 12285 { 12286 UINT32 dma_wr_c0_imwr_data : 16 ; 12287 UINT32 dma_wr_c1_imwr_data : 16 ; 12288 } Bits; 12289 12290 12291 UINT32 UInt32; 12292 12293 } PCIE_EP_PORTLOGIC74_U; 12294 12295 12296 12297 12298 typedef union tagPortlogic75 12299 { 12300 12301 struct 12302 { 12303 UINT32 wr_ch_ll_remote_abort_int_en : 8 ; 12304 UINT32 Reserved_119 : 8 ; 12305 UINT32 wr_ch_ll_local_abort_int_en : 8 ; 12306 UINT32 Reserved_118 : 8 ; 12307 } Bits; 12308 12309 12310 UINT32 UInt32; 12311 12312 } PCIE_EP_PORTLOGIC75_U; 12313 12314 12315 12316 12317 typedef union tagPortlogic76 12318 { 12319 12320 struct 12321 { 12322 UINT32 done_int_status : 8 ; 12323 UINT32 Reserved_122 : 8 ; 12324 UINT32 abort_int_status : 8 ; 12325 UINT32 Reserved_121 : 8 ; 12326 } Bits; 12327 12328 12329 UINT32 UInt32; 12330 12331 } PCIE_EP_PORTLOGIC76_U; 12332 12333 12334 12335 12336 typedef union tagPortlogic77 12337 { 12338 12339 struct 12340 { 12341 UINT32 done_int_mask : 8 ; 12342 UINT32 Reserved_124 : 8 ; 12343 UINT32 abort_int_mask : 8 ; 12344 UINT32 dma_rd_int_mask : 8 ; 12345 } Bits; 12346 12347 12348 UINT32 UInt32; 12349 12350 } PCIE_EP_PORTLOGIC77_U; 12351 12352 12353 12354 12355 typedef union tagPortlogic78 12356 { 12357 12358 struct 12359 { 12360 UINT32 done_int_clr : 8 ; 12361 UINT32 Reserved_126 : 8 ; 12362 UINT32 abort_int_clr : 8 ; 12363 UINT32 dma_rd_int_clr : 8 ; 12364 } Bits; 12365 12366 12367 UINT32 UInt32; 12368 12369 } PCIE_EP_PORTLOGIC78_U; 12370 12371 12372 12373 12374 typedef union tagPortlogic79 12375 { 12376 12377 struct 12378 { 12379 UINT32 app_wr_err_det : 8 ; 12380 UINT32 Reserved_127 : 8 ; 12381 UINT32 link_list_fetch_err_det : 8 ; 12382 UINT32 dma_rd_err_low : 8 ; 12383 } Bits; 12384 12385 12386 UINT32 UInt32; 12387 12388 } PCIE_EP_PORTLOGIC79_U; 12389 12390 12391 12392 12393 typedef union tagPortlogic80 12394 { 12395 12396 struct 12397 { 12398 UINT32 unspt_request : 8 ; 12399 UINT32 completer_abort : 8 ; 12400 UINT32 cpl_time_out : 8 ; 12401 UINT32 data_poison : 8 ; 12402 } Bits; 12403 12404 12405 UINT32 UInt32; 12406 12407 } PCIE_EP_PORTLOGIC80_U; 12408 12409 12410 12411 12412 typedef union tagPortlogic81 12413 { 12414 12415 struct 12416 { 12417 UINT32 remote_abort_int_en : 8 ; 12418 UINT32 Reserved_129 : 8 ; 12419 UINT32 local_abort_int_en : 8 ; 12420 UINT32 dma_rd_ll_err_ena : 8 ; 12421 } Bits; 12422 12423 12424 UINT32 UInt32; 12425 12426 } PCIE_EP_PORTLOGIC81_U; 12427 12428 12429 12430 12431 typedef union tagPortlogic86 12432 { 12433 12434 struct 12435 { 12436 UINT32 channel_dir : 3 ; 12437 UINT32 Reserved_132 : 28 ; 12438 UINT32 dma_ch_con_idx : 1 ; 12439 } Bits; 12440 12441 12442 UINT32 UInt32; 12443 12444 } PCIE_EP_PORTLOGIC86_U; 12445 12446 12447 12448 12449 typedef union tagPortlogic87 12450 { 12451 12452 struct 12453 { 12454 UINT32 cycle_bit : 1 ; 12455 UINT32 toggle_cycle_bit : 1 ; 12456 UINT32 load_link_pointer : 1 ; 12457 UINT32 local_int_en : 1 ; 12458 UINT32 remote_int_en : 1 ; 12459 UINT32 channel_status : 2 ; 12460 UINT32 Reserved_136 : 1 ; 12461 UINT32 consumer_cycle_state : 1 ; 12462 UINT32 linked_list_en : 1 ; 12463 UINT32 Reserved_135 : 2 ; 12464 UINT32 func_num_dma : 5 ; 12465 UINT32 Reserved_134 : 7 ; 12466 UINT32 no_snoop : 1 ; 12467 UINT32 ro : 1 ; 12468 UINT32 td : 1 ; 12469 UINT32 tc : 3 ; 12470 UINT32 dma_ch_ctrl : 2 ; 12471 } Bits; 12472 12473 12474 UINT32 UInt32; 12475 12476 } PCIE_EP_PORTLOGIC87_U; 12477 12478 12479 12480 12481 typedef union tagPortlogic93 12482 { 12483 12484 struct 12485 { 12486 UINT32 Reserved_138 : 2 ; 12487 UINT32 dma_ll_ptr_low : 30 ; 12488 } Bits; 12489 12490 12491 UINT32 UInt32; 12492 12493 } PCIE_EP_PORTLOGIC93_U; 12494 12495 12496 #define PCIE_SUBCTRL_BASE (0x0) 12497 12498 12499 12500 12501 12502 #define PCIE_SUBCTRL_SC_PCIE0_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x300) 12503 #define PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(port_id) \ 12504 (PCIE_SUBCTRL_SC_PCIE0_CLK_EN_REG + (port_id << 3)) 12505 #define PCIE_SUBCTRL_SC_PCIE0_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x304) 12506 #define PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(port_id) \ 12507 (PCIE_SUBCTRL_SC_PCIE0_CLK_DIS_REG + (port_id << 3)) 12508 #define PCIE_SUBCTRL_SC_PCIE1_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x308) 12509 #define PCIE_SUBCTRL_SC_PCIE1_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x30C) 12510 #define PCIE_SUBCTRL_SC_PCIE2_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x310) 12511 #define PCIE_SUBCTRL_SC_PCIE2_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x314) 12512 #define PCIE_SUBCTRL_SC_SAS_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x318) 12513 #define PCIE_SUBCTRL_SC_SAS_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x31C) 12514 #define PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x320) 12515 #define PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x324) 12516 #define PCIE_SUBCTRL_SC_ITS_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x328) 12517 #define PCIE_SUBCTRL_SC_ITS_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x32C) 12518 #define PCIE_SUBCTRL_SC_SLLC_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x360) 12519 #define PCIE_SUBCTRL_SC_SLLC_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x364) 12520 #define PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA00) 12521 #define PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA04) 12522 #define PCIE_SUBCTRL_SC_PCIE1_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA08) 12523 #define PCIE_SUBCTRL_SC_PCIE1_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA0C) 12524 #define PCIE_SUBCTRL_SC_PCIE2_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA10) 12525 #define PCIE_SUBCTRL_SC_PCIE2_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA14) 12526 #define PCIE_SUBCTRL_SC_SAS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA18) 12527 #define PCIE_SUBCTRL_SC_SAS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA1C) 12528 #define PCIE_SUBCTRL_SC_MCTP0_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA20) 12529 #define PCIE_SUBCTRL_SC_MCTP0_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA24) 12530 #define PCIE_SUBCTRL_SC_MCTP1_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA28) 12531 #define PCIE_SUBCTRL_SC_MCTP1_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA2C) 12532 #define PCIE_SUBCTRL_SC_MCTP2_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA30) 12533 #define PCIE_SUBCTRL_SC_MCTP2_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA34) 12534 #define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA58) 12535 #define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA5C) 12536 #define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA60) 12537 #define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA64) 12538 #define PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA68) 12539 #define PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA6C) 12540 #define PCIE_SUBCTRL_SC_MCTP3_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA70) 12541 #define PCIE_SUBCTRL_SC_MCTP3_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA74) 12542 #define PCIE_SUBCTRL_SC_ITS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA80) 12543 #define PCIE_SUBCTRL_SC_ITS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA84) 12544 #define PCIE_SUBCTRL_SC_SLLC_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAA0) 12545 #define PCIE_SUBCTRL_SC_SLLC_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xAA4) 12546 #define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAC0) 12547 #define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xAC4) 12548 #define PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAC8) 12549 #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (PCIE_SUBCTRL_BASE + 0x1000) 12550 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY0_REG (PCIE_SUBCTRL_BASE + 0x1004) 12551 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY1_REG (PCIE_SUBCTRL_BASE + 0x1008) 12552 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY2_REG (PCIE_SUBCTRL_BASE + 0x100C) 12553 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (PCIE_SUBCTRL_BASE + 0x1010) 12554 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (PCIE_SUBCTRL_BASE + 0x1014) 12555 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (PCIE_SUBCTRL_BASE + 0x1018) 12556 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (PCIE_SUBCTRL_BASE + 0x101C) 12557 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG (PCIE_SUBCTRL_BASE + 0x1020) 12558 #define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG (PCIE_SUBCTRL_BASE + 0x1030) 12559 #define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG (PCIE_SUBCTRL_BASE + 0x1100) 12560 #define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG (PCIE_SUBCTRL_BASE + 0x1104) 12561 #define PCIE_SUBCTRL_SC_DISPATCH_INTSTAT_REG (PCIE_SUBCTRL_BASE + 0x1108) 12562 #define PCIE_SUBCTRL_SC_DISPATCH_INTCLR_REG (PCIE_SUBCTRL_BASE + 0x110C) 12563 #define PCIE_SUBCTRL_SC_DISPATCH_ERRSTAT_REG (PCIE_SUBCTRL_BASE + 0x1110) 12564 #define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (PCIE_SUBCTRL_BASE + 0x1200) 12565 #define PCIE_SUBCTRL_SC_FTE_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2200) 12566 #define PCIE_SUBCTRL_SC_HILINK0_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2300) 12567 #define PCIE_SUBCTRL_SC_HILINK1_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2304) 12568 #define PCIE_SUBCTRL_SC_HILINK2_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2308) 12569 #define PCIE_SUBCTRL_SC_HILINK5_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2314) 12570 #define PCIE_SUBCTRL_SC_HILINK1_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2324) 12571 #define PCIE_SUBCTRL_SC_HILINK2_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2328) 12572 #define PCIE_SUBCTRL_SC_HILINK5_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2334) 12573 #define PCIE_SUBCTRL_SC_HILINK5_LRSTB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2340) 12574 #define PCIE_SUBCTRL_SC_HILINK6_LRSTB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2344) 12575 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2400) 12576 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2404) 12577 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2408) 12578 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x240C) 12579 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2410) 12580 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2414) 12581 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2418) 12582 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x241C) 12583 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2420) 12584 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2424) 12585 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2500) 12586 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2504) 12587 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2508) 12588 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x250C) 12589 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2510) 12590 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2514) 12591 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2518) 12592 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x251C) 12593 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2520) 12594 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2524) 12595 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2600) 12596 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2604) 12597 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2608) 12598 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x260C) 12599 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2610) 12600 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2614) 12601 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2618) 12602 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x261C) 12603 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2620) 12604 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2624) 12605 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2700) 12606 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2704) 12607 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2708) 12608 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x270C) 12609 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2710) 12610 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2714) 12611 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2718) 12612 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x271C) 12613 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2720) 12614 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2724) 12615 #define PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2800) 12616 #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2880) 12617 #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2890) 12618 #define PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2900) 12619 #define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2980) 12620 #define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2990) 12621 #define PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2A00) 12622 #define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2A80) 12623 #define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2A90) 12624 #define PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2B00) 12625 #define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL0_REG (PCIE_SUBCTRL_BASE + 0x3000) 12626 #define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL1_REG (PCIE_SUBCTRL_BASE + 0x3004) 12627 #define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL2_REG (PCIE_SUBCTRL_BASE + 0x3008) 12628 #define PCIE_SUBCTRL_SC_SLLC0_MEM_CTRL_REG (PCIE_SUBCTRL_BASE + 0x3010) 12629 #define PCIE_SUBCTRL_SC_SAS_MEM_CTRL_REG (PCIE_SUBCTRL_BASE + 0x3030) 12630 #define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL0_REG (PCIE_SUBCTRL_BASE + 0x3040) 12631 #define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL1_REG (PCIE_SUBCTRL_BASE + 0x3044) 12632 #define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL2_REG (PCIE_SUBCTRL_BASE + 0x3048) 12633 #define PCIE_SUBCTRL_SC_SKEW_COMMON_0_REG (PCIE_SUBCTRL_BASE + 0x3400) 12634 #define PCIE_SUBCTRL_SC_SKEW_COMMON_1_REG (PCIE_SUBCTRL_BASE + 0x3404) 12635 #define PCIE_SUBCTRL_SC_SKEW_COMMON_2_REG (PCIE_SUBCTRL_BASE + 0x3408) 12636 #define PCIE_SUBCTRL_SC_SKEW_A_0_REG (PCIE_SUBCTRL_BASE + 0x3500) 12637 #define PCIE_SUBCTRL_SC_SKEW_A_1_REG (PCIE_SUBCTRL_BASE + 0x3504) 12638 #define PCIE_SUBCTRL_SC_SKEW_A_2_REG (PCIE_SUBCTRL_BASE + 0x3508) 12639 #define PCIE_SUBCTRL_SC_SKEW_A_3_REG (PCIE_SUBCTRL_BASE + 0x350C) 12640 #define PCIE_SUBCTRL_SC_SKEW_A_4_REG (PCIE_SUBCTRL_BASE + 0x3510) 12641 #define PCIE_SUBCTRL_SC_SKEW_A_5_REG (PCIE_SUBCTRL_BASE + 0x3514) 12642 #define PCIE_SUBCTRL_SC_SKEW_A_6_REG (PCIE_SUBCTRL_BASE + 0x3518) 12643 #define PCIE_SUBCTRL_SC_SKEW_A_7_REG (PCIE_SUBCTRL_BASE + 0x351C) 12644 #define PCIE_SUBCTRL_SC_SKEW_A_8_REG (PCIE_SUBCTRL_BASE + 0x3520) 12645 #define PCIE_SUBCTRL_SC_SKEW_B_0_REG (PCIE_SUBCTRL_BASE + 0x3600) 12646 #define PCIE_SUBCTRL_SC_SKEW_B_1_REG (PCIE_SUBCTRL_BASE + 0x3604) 12647 #define PCIE_SUBCTRL_SC_SKEW_B_2_REG (PCIE_SUBCTRL_BASE + 0x3608) 12648 #define PCIE_SUBCTRL_SC_SKEW_B_3_REG (PCIE_SUBCTRL_BASE + 0x360C) 12649 #define PCIE_SUBCTRL_SC_SKEW_B_4_REG (PCIE_SUBCTRL_BASE + 0x3610) 12650 #define PCIE_SUBCTRL_SC_SKEW_B_5_REG (PCIE_SUBCTRL_BASE + 0x3614) 12651 #define PCIE_SUBCTRL_SC_SKEW_B_6_REG (PCIE_SUBCTRL_BASE + 0x3618) 12652 #define PCIE_SUBCTRL_SC_SKEW_B_7_REG (PCIE_SUBCTRL_BASE + 0x361C) 12653 #define PCIE_SUBCTRL_SC_SKEW_B_8_REG (PCIE_SUBCTRL_BASE + 0x3620) 12654 #define PCIE_SUBCTRL_SC_PCIE0_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5300) 12655 #define PCIE_SUBCTRL_SC_PCIE0_2_CLK_ST_REG(port_id) \ 12656 (PCIE_SUBCTRL_SC_PCIE0_CLK_ST_REG + (port_id << 2)) 12657 #define PCIE_SUBCTRL_SC_PCIE1_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5304) 12658 #define PCIE_SUBCTRL_SC_PCIE2_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5308) 12659 #define PCIE_SUBCTRL_SC_SAS_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x530C) 12660 #define PCIE_SUBCTRL_SC_PCIE3_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5310) 12661 #define PCIE_SUBCTRL_SC_ITS_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5314) 12662 #define PCIE_SUBCTRL_SC_SLLC_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5330) 12663 #define PCIE_SUBCTRL_SC_PCIE0_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A00) 12664 #define PCIE_SUBCTRL_SC_PCIE1_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A04) 12665 #define PCIE_SUBCTRL_SC_PCIE2_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A08) 12666 #define PCIE_SUBCTRL_SC_SAS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A0C) 12667 #define PCIE_SUBCTRL_SC_MCTP0_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A10) 12668 #define PCIE_SUBCTRL_SC_MCTP1_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A14) 12669 #define PCIE_SUBCTRL_SC_MCTP2_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A18) 12670 #define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A2C) 12671 #define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A30) 12672 #define PCIE_SUBCTRL_SC_PCIE3_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A34) 12673 #define PCIE_SUBCTRL_SC_MCTP3_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A38) 12674 #define PCIE_SUBCTRL_SC_ITS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A40) 12675 #define PCIE_SUBCTRL_SC_SLLC_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A50) 12676 #define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A60) 12677 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6400) 12678 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6404) 12679 #define PCIE_SUBCTRL_SC_HILINK0_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6408) 12680 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6500) 12681 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6504) 12682 #define PCIE_SUBCTRL_SC_HILINK1_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6508) 12683 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6600) 12684 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6604) 12685 #define PCIE_SUBCTRL_SC_HILINK5_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6608) 12686 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6700) 12687 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6704) 12688 #define PCIE_SUBCTRL_SC_HILINK6_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6708) 12689 #define PCIE_SUBCTRL_SC_PCIE0_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6800) 12690 #define PCIE_SUBCTRL_SC_PCIE0_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6804) 12691 #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6808) 12692 #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x680C) 12693 #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6810) 12694 #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6814) 12695 #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6818) 12696 #define PCIE_LTSSM_STATE_MASK (0x3f) 12697 #define PCIE_LTSSM_LINKUP_STATE (0x11) 12698 #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6880) 12699 #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6884) 12700 #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6890) 12701 #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6894) 12702 #define PCIE_SUBCTRL_SC_PCIE0_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x68A0) 12703 #define PCIE_SUBCTRL_SC_PCIE0_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x68C0) 12704 #define PCIE_SUBCTRL_SC_PCIE1_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6900) 12705 #define PCIE_SUBCTRL_SC_PCIE1_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6904) 12706 #define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6908) 12707 #define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x690C) 12708 #define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6910) 12709 #define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6914) 12710 #define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6918) 12711 #define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6980) 12712 #define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6984) 12713 #define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6990) 12714 #define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6994) 12715 #define PCIE_SUBCTRL_SC_PCIE1_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x69A0) 12716 #define PCIE_SUBCTRL_SC_PCIE1_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x69C0) 12717 #define PCIE_SUBCTRL_SC_PCIE2_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6A00) 12718 #define PCIE_SUBCTRL_SC_PCIE2_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6A04) 12719 #define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6A08) 12720 #define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x6A0C) 12721 #define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6A10) 12722 #define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6A14) 12723 #define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6A18) 12724 #define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6A80) 12725 #define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6A84) 12726 #define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6A90) 12727 #define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6A94) 12728 #define PCIE_SUBCTRL_SC_PCIE2_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x6AA0) 12729 #define PCIE_SUBCTRL_SC_PCIE2_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x6AC0) 12730 #define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6B08) 12731 #define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x6B0C) 12732 #define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6B10) 12733 #define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6B14) 12734 #define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6B18) 12735 #define PCIE_SUBCTRL_SC_PCIE3_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x6BC0) 12736 #define PCIE_SUBCTRL_SC_SKEW_ST_0_REG (PCIE_SUBCTRL_BASE + 0x7400) 12737 #define PCIE_SUBCTRL_SC_SKEW_ST_A_0_REG (PCIE_SUBCTRL_BASE + 0x7500) 12738 #define PCIE_SUBCTRL_SC_SKEW_ST_A_1_REG (PCIE_SUBCTRL_BASE + 0x7504) 12739 #define PCIE_SUBCTRL_SC_SKEW_ST_A_2_REG (PCIE_SUBCTRL_BASE + 0x7508) 12740 #define PCIE_SUBCTRL_SC_SKEW_ST_A_3_REG (PCIE_SUBCTRL_BASE + 0x750C) 12741 #define PCIE_SUBCTRL_SC_SKEW_ST_B_0_REG (PCIE_SUBCTRL_BASE + 0x7600) 12742 #define PCIE_SUBCTRL_SC_SKEW_ST_B_1_REG (PCIE_SUBCTRL_BASE + 0x7604) 12743 #define PCIE_SUBCTRL_SC_SKEW_ST_B_2_REG (PCIE_SUBCTRL_BASE + 0x7608) 12744 #define PCIE_SUBCTRL_SC_SKEW_ST_B_3_REG (PCIE_SUBCTRL_BASE + 0x760C) 12745 #define PCIE_SUBCTRL_SC_ECO_RSV0_REG (PCIE_SUBCTRL_BASE + 0x8000) 12746 #define PCIE_SUBCTRL_SC_ECO_RSV1_REG (PCIE_SUBCTRL_BASE + 0x8004) 12747 #define PCIE_SUBCTRL_SC_ECO_RSV2_REG (PCIE_SUBCTRL_BASE + 0x8008) 12748 12749 12750 typedef union 12751 { 12752 12753 struct 12754 { 12755 UINT32 clk_pcie0_enb : 1 ; 12756 UINT32 clk_pcie0_pipe_enb : 1 ; 12757 UINT32 reserved_0 : 30 ; 12758 } Bits; 12759 12760 12761 UINT32 UInt32; 12762 12763 } u_sc_pcie0_clk_en; 12764 12765 12766 typedef union 12767 { 12768 12769 struct 12770 { 12771 UINT32 clk_pcie0_dsb : 1 ; 12772 UINT32 clk_pcie0_pipe_dsb : 1 ; 12773 UINT32 reserved_0 : 30 ; 12774 } Bits; 12775 12776 12777 UINT32 UInt32; 12778 12779 } u_sc_pcie0_clk_dis; 12780 12781 12782 typedef union 12783 { 12784 12785 struct 12786 { 12787 UINT32 clk_pcie1_enb : 1 ; 12788 UINT32 clk_pcie1_pipe_enb : 1 ; 12789 UINT32 reserved_0 : 30 ; 12790 } Bits; 12791 12792 12793 UINT32 UInt32; 12794 12795 } u_sc_pcie1_clk_en; 12796 12797 12798 typedef union 12799 { 12800 12801 struct 12802 { 12803 UINT32 clk_pcie1_dsb : 1 ; 12804 UINT32 clk_pcie1_pipe_dsb : 1 ; 12805 UINT32 reserved_0 : 30 ; 12806 } Bits; 12807 12808 12809 UINT32 UInt32; 12810 12811 } u_sc_pcie1_clk_dis; 12812 12813 12814 typedef union 12815 { 12816 12817 struct 12818 { 12819 UINT32 clk_pcie2_enb : 1 ; 12820 UINT32 clk_pcie2_pipe_enb : 1 ; 12821 UINT32 reserved_0 : 30 ; 12822 } Bits; 12823 12824 12825 UINT32 UInt32; 12826 12827 } u_sc_pcie2_clk_en; 12828 12829 12830 typedef union 12831 { 12832 12833 struct 12834 { 12835 UINT32 clk_pcie2_dsb : 1 ; 12836 UINT32 clk_pcie2_pipe_dsb : 1 ; 12837 UINT32 reserved_0 : 30 ; 12838 } Bits; 12839 12840 12841 UINT32 UInt32; 12842 12843 } u_sc_pcie2_clk_dis; 12844 12845 12846 typedef union 12847 { 12848 12849 struct 12850 { 12851 UINT32 clk_sas_enb : 1 ; 12852 UINT32 clk_sas_mem_enb : 1 ; 12853 UINT32 clk_sas_ahb_enb : 1 ; 12854 UINT32 clk_sas_oob_enb : 1 ; 12855 UINT32 clk_sas_ch0_rx_enb : 1 ; 12856 UINT32 clk_sas_ch1_rx_enb : 1 ; 12857 UINT32 clk_sas_ch2_rx_enb : 1 ; 12858 UINT32 clk_sas_ch3_rx_enb : 1 ; 12859 UINT32 clk_sas_ch4_rx_enb : 1 ; 12860 UINT32 clk_sas_ch5_rx_enb : 1 ; 12861 UINT32 clk_sas_ch6_rx_enb : 1 ; 12862 UINT32 clk_sas_ch7_rx_enb : 1 ; 12863 UINT32 clk_sas_ch0_tx_enb : 1 ; 12864 UINT32 clk_sas_ch1_tx_enb : 1 ; 12865 UINT32 clk_sas_ch2_tx_enb : 1 ; 12866 UINT32 clk_sas_ch3_tx_enb : 1 ; 12867 UINT32 clk_sas_ch4_tx_enb : 1 ; 12868 UINT32 clk_sas_ch5_tx_enb : 1 ; 12869 UINT32 clk_sas_ch6_tx_enb : 1 ; 12870 UINT32 clk_sas_ch7_tx_enb : 1 ; 12871 UINT32 reserved_0 : 12 ; 12872 } Bits; 12873 12874 12875 UINT32 UInt32; 12876 12877 } u_sc_sas_clk_en; 12878 12879 12880 typedef union 12881 { 12882 12883 struct 12884 { 12885 UINT32 clk_sas_dsb : 1 ; 12886 UINT32 clk_sas_mem_dsb : 1 ; 12887 UINT32 clk_sas_ahb_dsb : 1 ; 12888 UINT32 clk_sas_oob_dsb : 1 ; 12889 UINT32 clk_sas_ch0_rx_dsb : 1 ; 12890 UINT32 clk_sas_ch1_rx_dsb : 1 ; 12891 UINT32 clk_sas_ch2_rx_dsb : 1 ; 12892 UINT32 clk_sas_ch3_rx_dsb : 1 ; 12893 UINT32 clk_sas_ch4_rx_dsb : 1 ; 12894 UINT32 clk_sas_ch5_rx_dsb : 1 ; 12895 UINT32 clk_sas_ch6_rx_dsb : 1 ; 12896 UINT32 clk_sas_ch7_rx_dsb : 1 ; 12897 UINT32 clk_sas_ch0_tx_dsb : 1 ; 12898 UINT32 clk_sas_ch1_tx_dsb : 1 ; 12899 UINT32 clk_sas_ch2_tx_dsb : 1 ; 12900 UINT32 clk_sas_ch3_tx_dsb : 1 ; 12901 UINT32 clk_sas_ch4_tx_dsb : 1 ; 12902 UINT32 clk_sas_ch5_tx_dsb : 1 ; 12903 UINT32 clk_sas_ch6_tx_dsb : 1 ; 12904 UINT32 clk_sas_ch7_tx_dsb : 1 ; 12905 UINT32 reserved_0 : 12 ; 12906 } Bits; 12907 12908 12909 UINT32 UInt32; 12910 12911 } u_sc_sas_clk_dis; 12912 12913 12914 typedef union 12915 { 12916 12917 struct 12918 { 12919 UINT32 clk_pcie3_enb : 1 ; 12920 UINT32 clk_pcie3_pipe_enb : 1 ; 12921 UINT32 reserved_0 : 30 ; 12922 } Bits; 12923 12924 12925 UINT32 UInt32; 12926 12927 } u_sc_pcie3_clk_en; 12928 12929 12930 typedef union 12931 { 12932 12933 struct 12934 { 12935 UINT32 clk_pcie3_dsb : 1 ; 12936 UINT32 clk_pcie3_pipe_dsb : 1 ; 12937 UINT32 reserved_0 : 30 ; 12938 } Bits; 12939 12940 12941 UINT32 UInt32; 12942 12943 } u_sc_pcie3_clk_dis; 12944 12945 12946 typedef union 12947 { 12948 12949 struct 12950 { 12951 UINT32 clk_its_enb : 1 ; 12952 UINT32 reserved_0 : 31 ; 12953 } Bits; 12954 12955 12956 UINT32 UInt32; 12957 12958 } u_sc_its_clk_en; 12959 12960 12961 typedef union 12962 { 12963 12964 struct 12965 { 12966 UINT32 clk_its_dsb : 1 ; 12967 UINT32 reserved_0 : 31 ; 12968 } Bits; 12969 12970 12971 UINT32 UInt32; 12972 12973 } u_sc_its_clk_dis; 12974 12975 12976 typedef union 12977 { 12978 12979 struct 12980 { 12981 UINT32 clk_sllc_enb : 1 ; 12982 UINT32 reserved_0 : 31 ; 12983 } Bits; 12984 12985 12986 UINT32 UInt32; 12987 12988 } u_sc_sllc_clk_en; 12989 12990 12991 typedef union 12992 { 12993 12994 struct 12995 { 12996 UINT32 clk_sllc_dsb : 1 ; 12997 UINT32 reserved_0 : 31 ; 12998 } Bits; 12999 13000 13001 UINT32 UInt32; 13002 13003 } u_sc_sllc_clk_dis; 13004 13005 13006 typedef union 13007 { 13008 13009 struct 13010 { 13011 UINT32 pcie0_srst_req : 1 ; 13012 UINT32 reserved_0 : 31 ; 13013 } Bits; 13014 13015 13016 UINT32 UInt32; 13017 13018 } u_sc_pcie0_reset_req; 13019 13020 13021 typedef union 13022 { 13023 13024 struct 13025 { 13026 UINT32 pcie0_srst_dreq : 1 ; 13027 UINT32 reserved_0 : 31 ; 13028 } Bits; 13029 13030 13031 UINT32 UInt32; 13032 13033 } u_sc_pcie0_reset_dreq; 13034 13035 13036 typedef union 13037 { 13038 13039 struct 13040 { 13041 UINT32 pcie1_srst_req : 1 ; 13042 UINT32 reserved_0 : 31 ; 13043 } Bits; 13044 13045 13046 UINT32 UInt32; 13047 13048 } u_sc_pcie1_reset_req; 13049 13050 13051 typedef union 13052 { 13053 13054 struct 13055 { 13056 UINT32 pcie1_srst_dreq : 1 ; 13057 UINT32 reserved_0 : 31 ; 13058 } Bits; 13059 13060 13061 UINT32 UInt32; 13062 13063 } u_sc_pcie1_reset_dreq; 13064 13065 13066 typedef union 13067 { 13068 13069 struct 13070 { 13071 UINT32 pcie2_srst_req : 1 ; 13072 UINT32 reserved_0 : 31 ; 13073 } Bits; 13074 13075 13076 UINT32 UInt32; 13077 13078 } u_sc_pcie2_reset_req; 13079 13080 13081 typedef union 13082 { 13083 13084 struct 13085 { 13086 UINT32 pcie2_srst_dreq : 1 ; 13087 UINT32 reserved_0 : 31 ; 13088 } Bits; 13089 13090 13091 UINT32 UInt32; 13092 13093 } u_sc_pcie2_reset_dreq; 13094 13095 13096 typedef union 13097 { 13098 13099 struct 13100 { 13101 UINT32 sas_srst_req : 1 ; 13102 UINT32 sas_oob_srst_req : 1 ; 13103 UINT32 sas_ahb_srst_req : 1 ; 13104 UINT32 sas_ch0_rx_srst_req : 1 ; 13105 UINT32 sas_ch1_rx_srst_req : 1 ; 13106 UINT32 sas_ch2_rx_srst_req : 1 ; 13107 UINT32 sas_ch3_rx_srst_req : 1 ; 13108 UINT32 sas_ch4_rx_srst_req : 1 ; 13109 UINT32 sas_ch5_rx_srst_req : 1 ; 13110 UINT32 sas_ch6_rx_srst_req : 1 ; 13111 UINT32 sas_ch7_rx_srst_req : 1 ; 13112 UINT32 sas_ch0_tx_srst_req : 1 ; 13113 UINT32 sas_ch1_tx_srst_req : 1 ; 13114 UINT32 sas_ch2_tx_srst_req : 1 ; 13115 UINT32 sas_ch3_tx_srst_req : 1 ; 13116 UINT32 sas_ch4_tx_srst_req : 1 ; 13117 UINT32 sas_ch5_tx_srst_req : 1 ; 13118 UINT32 sas_ch6_tx_srst_req : 1 ; 13119 UINT32 sas_ch7_tx_srst_req : 1 ; 13120 UINT32 reserved_0 : 13 ; 13121 } Bits; 13122 13123 13124 UINT32 UInt32; 13125 13126 } u_sc_sas_reset_req; 13127 13128 13129 typedef union 13130 { 13131 13132 struct 13133 { 13134 UINT32 sas_srst_dreq : 1 ; 13135 UINT32 sas_oob_srst_dreq : 1 ; 13136 UINT32 sas_ahb_srst_dreq : 1 ; 13137 UINT32 sas_ch0_rx_srst_dreq : 1 ; 13138 UINT32 sas_ch1_rx_srst_dreq : 1 ; 13139 UINT32 sas_ch2_rx_srst_dreq : 1 ; 13140 UINT32 sas_ch3_rx_srst_dreq : 1 ; 13141 UINT32 sas_ch4_rx_srst_dreq : 1 ; 13142 UINT32 sas_ch5_rx_srst_dreq : 1 ; 13143 UINT32 sas_ch6_rx_srst_dreq : 1 ; 13144 UINT32 sas_ch7_rx_srst_dreq : 1 ; 13145 UINT32 sas_ch0_tx_srst_dreq : 1 ; 13146 UINT32 sas_ch1_tx_srst_dreq : 1 ; 13147 UINT32 sas_ch2_tx_srst_dreq : 1 ; 13148 UINT32 sas_ch3_tx_srst_dreq : 1 ; 13149 UINT32 sas_ch4_tx_srst_dreq : 1 ; 13150 UINT32 sas_ch5_tx_srst_dreq : 1 ; 13151 UINT32 sas_ch6_tx_srst_dreq : 1 ; 13152 UINT32 sas_ch7_tx_srst_dreq : 1 ; 13153 UINT32 reserved_0 : 13 ; 13154 } Bits; 13155 13156 13157 UINT32 UInt32; 13158 13159 } u_sc_sas_reset_dreq; 13160 13161 13162 typedef union 13163 { 13164 13165 struct 13166 { 13167 UINT32 mctp0_srst_req : 1 ; 13168 UINT32 reserved_0 : 31 ; 13169 } Bits; 13170 13171 13172 UINT32 UInt32; 13173 13174 } u_sc_mctp0_reset_req; 13175 13176 13177 typedef union 13178 { 13179 13180 struct 13181 { 13182 UINT32 mctp0_srst_dreq : 1 ; 13183 UINT32 reserved_0 : 31 ; 13184 } Bits; 13185 13186 13187 UINT32 UInt32; 13188 13189 } u_sc_mctp0_reset_dreq; 13190 13191 13192 typedef union 13193 { 13194 13195 struct 13196 { 13197 UINT32 mctp1_srst_req : 1 ; 13198 UINT32 reserved_0 : 31 ; 13199 } Bits; 13200 13201 13202 UINT32 UInt32; 13203 13204 } u_sc_mctp1_reset_req; 13205 13206 13207 typedef union 13208 { 13209 13210 struct 13211 { 13212 UINT32 mctp1_srst_dreq : 1 ; 13213 UINT32 reserved_0 : 31 ; 13214 } Bits; 13215 13216 13217 UINT32 UInt32; 13218 13219 } u_sc_mctp1_reset_dreq; 13220 13221 13222 typedef union 13223 { 13224 13225 struct 13226 { 13227 UINT32 mctp2_srst_req : 1 ; 13228 UINT32 reserved_0 : 31 ; 13229 } Bits; 13230 13231 13232 UINT32 UInt32; 13233 13234 } u_sc_mctp2_reset_req; 13235 13236 13237 typedef union 13238 { 13239 13240 struct 13241 { 13242 UINT32 mctp2_srst_dreq : 1 ; 13243 UINT32 reserved_0 : 31 ; 13244 } Bits; 13245 13246 13247 UINT32 UInt32; 13248 13249 } u_sc_mctp2_reset_dreq; 13250 13251 13252 typedef union 13253 { 13254 13255 struct 13256 { 13257 UINT32 sllc_tsvrx0_srst_req : 1 ; 13258 UINT32 sllc_tsvrx1_srst_req : 1 ; 13259 UINT32 sllc_tsvrx2_srst_req : 1 ; 13260 UINT32 sllc_tsvrx3_srst_req : 1 ; 13261 UINT32 reserved_0 : 28 ; 13262 } Bits; 13263 13264 13265 UINT32 UInt32; 13266 13267 } u_sc_sllc_tsvrx_reset_req; 13268 13269 13270 typedef union 13271 { 13272 13273 struct 13274 { 13275 UINT32 sllc_tsvrx0_srst_dreq : 1 ; 13276 UINT32 sllc_tsvrx1_srst_dreq : 1 ; 13277 UINT32 sllc_tsvrx2_srst_dreq : 1 ; 13278 UINT32 sllc_tsvrx3_srst_dreq : 1 ; 13279 UINT32 reserved_0 : 28 ; 13280 } Bits; 13281 13282 13283 UINT32 UInt32; 13284 13285 } u_sc_sllc_tsvrx_reset_dreq; 13286 13287 13288 typedef union 13289 { 13290 13291 struct 13292 { 13293 UINT32 pcie0_hilink_pcs_lane0_srst_req : 1 ; 13294 UINT32 pcie0_hilink_pcs_lane1_srst_req : 1 ; 13295 UINT32 pcie0_hilink_pcs_lane2_srst_req : 1 ; 13296 UINT32 pcie0_hilink_pcs_lane3_srst_req : 1 ; 13297 UINT32 pcie0_hilink_pcs_lane4_srst_req : 1 ; 13298 UINT32 pcie0_hilink_pcs_lane5_srst_req : 1 ; 13299 UINT32 pcie0_hilink_pcs_lane6_srst_req : 1 ; 13300 UINT32 pcie0_hilink_pcs_lane7_srst_req : 1 ; 13301 UINT32 pcie1_hilink_pcs_lane0_srst_req : 1 ; 13302 UINT32 pcie1_hilink_pcs_lane1_srst_req : 1 ; 13303 UINT32 pcie1_hilink_pcs_lane2_srst_req : 1 ; 13304 UINT32 pcie1_hilink_pcs_lane3_srst_req : 1 ; 13305 UINT32 pcie1_hilink_pcs_lane4_srst_req : 1 ; 13306 UINT32 pcie1_hilink_pcs_lane5_srst_req : 1 ; 13307 UINT32 pcie1_hilink_pcs_lane6_srst_req : 1 ; 13308 UINT32 pcie1_hilink_pcs_lane7_srst_req : 1 ; 13309 UINT32 pcie2_hilink_pcs_lane0_srst_req : 1 ; 13310 UINT32 pcie2_hilink_pcs_lane1_srst_req : 1 ; 13311 UINT32 pcie2_hilink_pcs_lane2_srst_req : 1 ; 13312 UINT32 pcie2_hilink_pcs_lane3_srst_req : 1 ; 13313 UINT32 pcie2_hilink_pcs_lane4_srst_req : 1 ; 13314 UINT32 pcie2_hilink_pcs_lane5_srst_req : 1 ; 13315 UINT32 pcie2_hilink_pcs_lane6_srst_req : 1 ; 13316 UINT32 pcie2_hilink_pcs_lane7_srst_req : 1 ; 13317 UINT32 pcie3_hilink_pcs_lane0_srst_req : 1 ; 13318 UINT32 pcie3_hilink_pcs_lane1_srst_req : 1 ; 13319 UINT32 pcie3_hilink_pcs_lane2_srst_req : 1 ; 13320 UINT32 pcie3_hilink_pcs_lane3_srst_req : 1 ; 13321 UINT32 pcie3_hilink_pcs_lane4_srst_req : 1 ; 13322 UINT32 pcie3_hilink_pcs_lane5_srst_req : 1 ; 13323 UINT32 pcie3_hilink_pcs_lane6_srst_req : 1 ; 13324 UINT32 pcie3_hilink_pcs_lane7_srst_req : 1 ; 13325 } Bits; 13326 13327 13328 UINT32 UInt32; 13329 13330 } u_sc_pcie_hilink_pcs_reset_req; 13331 13332 13333 typedef union 13334 { 13335 13336 struct 13337 { 13338 UINT32 pcie0_hilink_pcs_lane0_srst_dreq : 1 ; 13339 UINT32 pcie0_hilink_pcs_lane1_srst_dreq : 1 ; 13340 UINT32 pcie0_hilink_pcs_lane2_srst_dreq : 1 ; 13341 UINT32 pcie0_hilink_pcs_lane3_srst_dreq : 1 ; 13342 UINT32 pcie0_hilink_pcs_lane4_srst_dreq : 1 ; 13343 UINT32 pcie0_hilink_pcs_lane5_srst_dreq : 1 ; 13344 UINT32 pcie0_hilink_pcs_lane6_srst_dreq : 1 ; 13345 UINT32 pcie0_hilink_pcs_lane7_srst_dreq : 1 ; 13346 UINT32 pcie1_hilink_pcs_lane0_srst_dreq : 1 ; 13347 UINT32 pcie1_hilink_pcs_lane1_srst_dreq : 1 ; 13348 UINT32 pcie1_hilink_pcs_lane2_srst_dreq : 1 ; 13349 UINT32 pcie1_hilink_pcs_lane3_srst_dreq : 1 ; 13350 UINT32 pcie1_hilink_pcs_lane4_srst_dreq : 1 ; 13351 UINT32 pcie1_hilink_pcs_lane5_srst_dreq : 1 ; 13352 UINT32 pcie1_hilink_pcs_lane6_srst_dreq : 1 ; 13353 UINT32 pcie1_hilink_pcs_lane7_srst_dreq : 1 ; 13354 UINT32 pcie2_hilink_pcs_lane0_srst_dreq : 1 ; 13355 UINT32 pcie2_hilink_pcs_lane1_srst_dreq : 1 ; 13356 UINT32 pcie2_hilink_pcs_lane2_srst_dreq : 1 ; 13357 UINT32 pcie2_hilink_pcs_lane3_srst_dreq : 1 ; 13358 UINT32 pcie2_hilink_pcs_lane4_srst_dreq : 1 ; 13359 UINT32 pcie2_hilink_pcs_lane5_srst_dreq : 1 ; 13360 UINT32 pcie2_hilink_pcs_lane6_srst_dreq : 1 ; 13361 UINT32 pcie2_hilink_pcs_lane7_srst_dreq : 1 ; 13362 UINT32 pcie3_hilink_pcs_lane0_srst_dreq : 1 ; 13363 UINT32 pcie3_hilink_pcs_lane1_srst_dreq : 1 ; 13364 UINT32 pcie3_hilink_pcs_lane2_srst_dreq : 1 ; 13365 UINT32 pcie3_hilink_pcs_lane3_srst_dreq : 1 ; 13366 UINT32 pcie3_hilink_pcs_lane4_srst_dreq : 1 ; 13367 UINT32 pcie3_hilink_pcs_lane5_srst_dreq : 1 ; 13368 UINT32 pcie3_hilink_pcs_lane6_srst_dreq : 1 ; 13369 UINT32 pcie3_hilink_pcs_lane7_srst_dreq : 1 ; 13370 } Bits; 13371 13372 13373 UINT32 UInt32; 13374 13375 } u_sc_pcie_hilink_pcs_reset_dreq; 13376 13377 13378 typedef union 13379 { 13380 13381 struct 13382 { 13383 UINT32 pcie3_srst_req : 1 ; 13384 UINT32 reserved_0 : 31 ; 13385 } Bits; 13386 13387 13388 UINT32 UInt32; 13389 13390 } u_sc_pcie3_reset_req; 13391 13392 13393 typedef union 13394 { 13395 13396 struct 13397 { 13398 UINT32 pcie3_srst_dreq : 1 ; 13399 UINT32 reserved_0 : 31 ; 13400 } Bits; 13401 13402 13403 UINT32 UInt32; 13404 13405 } u_sc_pcie3_reset_dreq; 13406 13407 13408 typedef union 13409 { 13410 13411 struct 13412 { 13413 UINT32 mctp3_srst_req : 1 ; 13414 UINT32 reserved_0 : 31 ; 13415 } Bits; 13416 13417 13418 UINT32 UInt32; 13419 13420 } u_sc_mctp3_reset_req; 13421 13422 13423 typedef union 13424 { 13425 13426 struct 13427 { 13428 UINT32 mctp3_srst_dreq : 1 ; 13429 UINT32 reserved_0 : 31 ; 13430 } Bits; 13431 13432 13433 UINT32 UInt32; 13434 13435 } u_sc_mctp3_reset_dreq; 13436 13437 13438 typedef union 13439 { 13440 13441 struct 13442 { 13443 UINT32 its_srst_req : 1 ; 13444 UINT32 reserved_0 : 31 ; 13445 } Bits; 13446 13447 13448 UINT32 UInt32; 13449 13450 } u_sc_its_reset_req; 13451 13452 13453 typedef union 13454 { 13455 13456 struct 13457 { 13458 UINT32 its_srst_dreq : 1 ; 13459 UINT32 reserved_0 : 31 ; 13460 } Bits; 13461 13462 13463 UINT32 UInt32; 13464 13465 } u_sc_its_reset_dreq; 13466 13467 13468 typedef union 13469 { 13470 13471 struct 13472 { 13473 UINT32 sllc_srst_req : 1 ; 13474 UINT32 reserved_0 : 31 ; 13475 } Bits; 13476 13477 13478 UINT32 UInt32; 13479 13480 } u_sc_sllc_reset_req; 13481 13482 13483 typedef union 13484 { 13485 13486 struct 13487 { 13488 UINT32 sllc_srst_dreq : 1 ; 13489 UINT32 reserved_0 : 31 ; 13490 } Bits; 13491 13492 13493 UINT32 UInt32; 13494 13495 } u_sc_sllc_reset_dreq; 13496 13497 13498 typedef union 13499 { 13500 13501 struct 13502 { 13503 UINT32 pcie0_pcs_local_srst_req : 1 ; 13504 UINT32 pcie1_pcs_local_srst_req : 1 ; 13505 UINT32 pcie2_pcs_local_srst_req : 1 ; 13506 UINT32 pcie3_pcs_local_srst_req : 1 ; 13507 UINT32 reserved_0 : 28 ; 13508 } Bits; 13509 13510 13511 UINT32 UInt32; 13512 13513 } u_sc_pcs_local_reset_req; 13514 13515 13516 typedef union 13517 { 13518 13519 struct 13520 { 13521 UINT32 pcie0_pcs_local_srst_dreq : 1 ; 13522 UINT32 pcie1_pcs_local_srst_dreq : 1 ; 13523 UINT32 pcie2_pcs_local_srst_dreq : 1 ; 13524 UINT32 pcie3_pcs_local_srst_dreq : 1 ; 13525 UINT32 reserved_0 : 28 ; 13526 } Bits; 13527 13528 13529 UINT32 UInt32; 13530 13531 } u_sc_pcs_local_reset_dreq; 13532 13533 13534 typedef union 13535 { 13536 13537 struct 13538 { 13539 UINT32 dispatch_daw_en : 8 ; 13540 UINT32 reserved_0 : 24 ; 13541 } Bits; 13542 13543 13544 UINT32 UInt32; 13545 13546 } u_sc_disp_daw_en; 13547 13548 13549 typedef union 13550 { 13551 13552 struct 13553 { 13554 UINT32 daw_array0_did : 3 ; 13555 UINT32 daw_array0_size : 5 ; 13556 UINT32 daw_array0_sync : 1 ; 13557 UINT32 reserved_0 : 4 ; 13558 UINT32 daw_array0_addr : 19 ; 13559 } Bits; 13560 13561 13562 UINT32 UInt32; 13563 13564 } u_sc_dispatch_daw_array0; 13565 13566 13567 typedef union 13568 { 13569 13570 struct 13571 { 13572 UINT32 daw_array1_did : 3 ; 13573 UINT32 daw_array1_size : 5 ; 13574 UINT32 daw_array1_sync : 1 ; 13575 UINT32 reserved_0 : 4 ; 13576 UINT32 daw_array1_addr : 19 ; 13577 } Bits; 13578 13579 13580 UINT32 UInt32; 13581 13582 } u_sc_dispatch_daw_array1; 13583 13584 13585 typedef union 13586 { 13587 13588 struct 13589 { 13590 UINT32 daw_array2_did : 3 ; 13591 UINT32 daw_array2_size : 5 ; 13592 UINT32 daw_array2_sync : 1 ; 13593 UINT32 reserved_0 : 4 ; 13594 UINT32 daw_array2_addr : 19 ; 13595 } Bits; 13596 13597 13598 UINT32 UInt32; 13599 13600 } u_sc_dispatch_daw_array2; 13601 13602 13603 typedef union 13604 { 13605 13606 struct 13607 { 13608 UINT32 daw_array3_did : 3 ; 13609 UINT32 daw_array3_size : 5 ; 13610 UINT32 daw_array3_sync : 1 ; 13611 UINT32 reserved_0 : 4 ; 13612 UINT32 daw_array3_addr : 19 ; 13613 } Bits; 13614 13615 13616 UINT32 UInt32; 13617 13618 } u_sc_dispatch_daw_array3; 13619 13620 13621 typedef union 13622 { 13623 13624 struct 13625 { 13626 UINT32 daw_array4_did : 3 ; 13627 UINT32 daw_array4_size : 5 ; 13628 UINT32 daw_array4_sync : 1 ; 13629 UINT32 reserved_0 : 4 ; 13630 UINT32 daw_array4_addr : 19 ; 13631 } Bits; 13632 13633 13634 UINT32 UInt32; 13635 13636 } u_sc_dispatch_daw_array4; 13637 13638 13639 typedef union 13640 { 13641 13642 struct 13643 { 13644 UINT32 daw_array5_did : 3 ; 13645 UINT32 daw_array5_size : 5 ; 13646 UINT32 daw_array5_sync : 1 ; 13647 UINT32 reserved_0 : 4 ; 13648 UINT32 daw_array5_addr : 19 ; 13649 } Bits; 13650 13651 13652 UINT32 UInt32; 13653 13654 } u_sc_dispatch_daw_array5; 13655 13656 13657 typedef union 13658 { 13659 13660 struct 13661 { 13662 UINT32 daw_array6_did : 3 ; 13663 UINT32 daw_array6_size : 5 ; 13664 UINT32 daw_array6_sync : 1 ; 13665 UINT32 reserved_0 : 4 ; 13666 UINT32 daw_array6_addr : 19 ; 13667 } Bits; 13668 13669 13670 UINT32 UInt32; 13671 13672 } u_sc_dispatch_daw_array6; 13673 13674 13675 typedef union 13676 { 13677 13678 struct 13679 { 13680 UINT32 daw_array7_did : 3 ; 13681 UINT32 daw_array7_size : 5 ; 13682 UINT32 daw_array7_sync : 1 ; 13683 UINT32 reserved_0 : 4 ; 13684 UINT32 daw_array7_addr : 19 ; 13685 } Bits; 13686 13687 13688 UINT32 UInt32; 13689 13690 } u_sc_dispatch_daw_array7; 13691 13692 13693 typedef union 13694 { 13695 13696 struct 13697 { 13698 UINT32 retry_num_limit : 16 ; 13699 UINT32 retry_en : 1 ; 13700 UINT32 reserved_0 : 15 ; 13701 } Bits; 13702 13703 13704 UINT32 UInt32; 13705 13706 } u_sc_dispatch_retry_control; 13707 13708 13709 typedef union 13710 { 13711 13712 struct 13713 { 13714 UINT32 intmask : 1 ; 13715 UINT32 reserved_0 : 31 ; 13716 } Bits; 13717 13718 13719 UINT32 UInt32; 13720 13721 } u_sc_dispatch_intmask; 13722 13723 13724 typedef union 13725 { 13726 13727 struct 13728 { 13729 UINT32 rawint : 1 ; 13730 UINT32 reserved_0 : 31 ; 13731 } Bits; 13732 13733 13734 UINT32 UInt32; 13735 13736 } u_sc_dispatch_rawint; 13737 13738 13739 typedef union 13740 { 13741 13742 struct 13743 { 13744 UINT32 intsts : 1 ; 13745 UINT32 reserved_0 : 31 ; 13746 } Bits; 13747 13748 13749 UINT32 UInt32; 13750 13751 } u_sc_dispatch_intstat; 13752 13753 13754 typedef union 13755 { 13756 13757 struct 13758 { 13759 UINT32 intclr : 1 ; 13760 UINT32 reserved_0 : 31 ; 13761 } Bits; 13762 13763 13764 UINT32 UInt32; 13765 13766 } u_sc_dispatch_intclr; 13767 13768 13769 typedef union 13770 { 13771 13772 struct 13773 { 13774 UINT32 err_opcode : 5 ; 13775 UINT32 err_addr : 17 ; 13776 UINT32 reserved_0 : 10 ; 13777 } Bits; 13778 13779 13780 UINT32 UInt32; 13781 13782 } u_sc_dispatch_errstat; 13783 13784 13785 typedef union 13786 { 13787 13788 struct 13789 { 13790 UINT32 sys_remap_vld : 1 ; 13791 UINT32 reserved_0 : 31 ; 13792 } Bits; 13793 13794 13795 UINT32 UInt32; 13796 13797 } u_sc_remap_ctrl; 13798 13799 13800 typedef union 13801 { 13802 13803 struct 13804 { 13805 UINT32 mux_sel_fte : 1 ; 13806 UINT32 reserved_0 : 31 ; 13807 } Bits; 13808 13809 13810 UINT32 UInt32; 13811 13812 } u_sc_fte_mux_ctrl; 13813 13814 13815 typedef union 13816 { 13817 13818 struct 13819 { 13820 UINT32 hilink0_mux_sel : 1 ; 13821 UINT32 reserved_0 : 31 ; 13822 } Bits; 13823 13824 13825 UINT32 UInt32; 13826 13827 } u_sc_hilink0_mux_ctrl; 13828 13829 13830 typedef union 13831 { 13832 13833 struct 13834 { 13835 UINT32 hilink1_mux_sel : 1 ; 13836 UINT32 reserved_0 : 31 ; 13837 } Bits; 13838 13839 13840 UINT32 UInt32; 13841 13842 } u_sc_hilink1_mux_ctrl; 13843 13844 13845 typedef union 13846 { 13847 13848 struct 13849 { 13850 UINT32 hilink2_mux_sel : 1 ; 13851 UINT32 reserved_0 : 31 ; 13852 } Bits; 13853 13854 13855 UINT32 UInt32; 13856 13857 } u_sc_hilink2_mux_ctrl; 13858 13859 13860 typedef union 13861 { 13862 13863 struct 13864 { 13865 UINT32 hilink5_mux_sel : 1 ; 13866 UINT32 reserved_0 : 31 ; 13867 } Bits; 13868 13869 13870 UINT32 UInt32; 13871 13872 } u_sc_hilink5_mux_ctrl; 13873 13874 13875 typedef union 13876 { 13877 13878 struct 13879 { 13880 UINT32 hilink1_ahb_mux_sel : 1 ; 13881 UINT32 reserved_0 : 31 ; 13882 } Bits; 13883 13884 13885 UINT32 UInt32; 13886 13887 } u_sc_hilink1_ahb_mux_ctrl; 13888 13889 13890 typedef union 13891 { 13892 13893 struct 13894 { 13895 UINT32 hilink2_ahb_mux_sel : 1 ; 13896 UINT32 reserved_0 : 31 ; 13897 } Bits; 13898 13899 13900 UINT32 UInt32; 13901 13902 } u_sc_hilink2_ahb_mux_ctrl; 13903 13904 13905 typedef union 13906 { 13907 13908 struct 13909 { 13910 UINT32 hilink5_ahb_mux_sel : 1 ; 13911 UINT32 reserved_0 : 31 ; 13912 } Bits; 13913 13914 13915 UINT32 UInt32; 13916 13917 } u_sc_hilink5_ahb_mux_ctrl; 13918 13919 13920 typedef union 13921 { 13922 13923 struct 13924 { 13925 UINT32 hilink5_lrstb_mux_sel : 1 ; 13926 UINT32 reserved_0 : 31 ; 13927 } Bits; 13928 13929 13930 UINT32 UInt32; 13931 13932 } u_sc_hilink5_lrstb_mux_ctrl; 13933 13934 13935 typedef union 13936 { 13937 13938 struct 13939 { 13940 UINT32 hilink6_lrstb_mux_sel : 1 ; 13941 UINT32 reserved_0 : 31 ; 13942 } Bits; 13943 13944 13945 UINT32 UInt32; 13946 13947 } u_sc_hilink6_lrstb_mux_ctrl; 13948 13949 13950 typedef union 13951 { 13952 13953 struct 13954 { 13955 UINT32 hilink0_ss_refclk0_x2s : 2 ; 13956 UINT32 hilink0_ss_refclk0_x2n : 2 ; 13957 UINT32 hilink0_ss_refclk0_x2e : 2 ; 13958 UINT32 hilink0_ss_refclk0_x2w : 2 ; 13959 UINT32 hilink0_ss_refclk1_x2s : 2 ; 13960 UINT32 hilink0_ss_refclk1_x2n : 2 ; 13961 UINT32 hilink0_ss_refclk1_x2e : 2 ; 13962 UINT32 hilink0_ss_refclk1_x2w : 2 ; 13963 UINT32 reserved_0 : 16 ; 13964 } Bits; 13965 13966 13967 UINT32 UInt32; 13968 13969 } u_sc_hilink0_macro_ss_refclk; 13970 13971 13972 typedef union 13973 { 13974 13975 struct 13976 { 13977 UINT32 hilink0_cs_refclk0_dirsel0 : 2 ; 13978 UINT32 hilink0_cs_refclk0_dirsel1 : 2 ; 13979 UINT32 hilink0_cs_refclk0_dirsel2 : 2 ; 13980 UINT32 hilink0_cs_refclk0_dirsel3 : 2 ; 13981 UINT32 hilink0_cs_refclk0_dirsel4 : 2 ; 13982 UINT32 hilink0_cs_refclk1_dirsel0 : 2 ; 13983 UINT32 hilink0_cs_refclk1_dirsel1 : 2 ; 13984 UINT32 hilink0_cs_refclk1_dirsel2 : 2 ; 13985 UINT32 hilink0_cs_refclk1_dirsel3 : 2 ; 13986 UINT32 hilink0_cs_refclk1_dirsel4 : 2 ; 13987 UINT32 reserved_0 : 12 ; 13988 } Bits; 13989 13990 13991 UINT32 UInt32; 13992 13993 } u_sc_hilink0_macro_cs_refclk_dirsel; 13994 13995 13996 typedef union 13997 { 13998 13999 struct 14000 { 14001 UINT32 hilink0_lifeclk2dig_sel : 2 ; 14002 UINT32 reserved_0 : 30 ; 14003 } Bits; 14004 14005 14006 UINT32 UInt32; 14007 14008 } u_sc_hilink0_macro_lifeclk2dig_sel; 14009 14010 14011 typedef union 14012 { 14013 14014 struct 14015 { 14016 UINT32 hilink0_core_clk_selext : 1 ; 14017 UINT32 reserved_0 : 31 ; 14018 } Bits; 14019 14020 14021 UINT32 UInt32; 14022 14023 } u_sc_hilink0_macro_core_clk_selext; 14024 14025 14026 typedef union 14027 { 14028 14029 struct 14030 { 14031 UINT32 hilink0_core_clk_sel : 1 ; 14032 UINT32 reserved_0 : 31 ; 14033 } Bits; 14034 14035 14036 UINT32 UInt32; 14037 14038 } u_sc_hilink0_macro_core_clk_sel; 14039 14040 14041 typedef union 14042 { 14043 14044 struct 14045 { 14046 UINT32 hilink0_ctrl_bus_mode : 2 ; 14047 UINT32 reserved_0 : 30 ; 14048 } Bits; 14049 14050 14051 UINT32 UInt32; 14052 14053 } u_sc_hilink0_macro_ctrl_bus_mode; 14054 14055 14056 typedef union 14057 { 14058 14059 struct 14060 { 14061 UINT32 hilink0_macropwrdb : 1 ; 14062 UINT32 reserved_0 : 31 ; 14063 } Bits; 14064 14065 14066 UINT32 UInt32; 14067 14068 } u_sc_hilink0_macro_macropwrdb; 14069 14070 14071 typedef union 14072 { 14073 14074 struct 14075 { 14076 UINT32 hilink0_grstb : 1 ; 14077 UINT32 reserved_0 : 31 ; 14078 } Bits; 14079 14080 14081 UINT32 UInt32; 14082 14083 } u_sc_hilink0_macro_grstb; 14084 14085 14086 typedef union 14087 { 14088 14089 struct 14090 { 14091 UINT32 hilink0_bit_slip : 8 ; 14092 UINT32 reserved_0 : 24 ; 14093 } Bits; 14094 14095 14096 UINT32 UInt32; 14097 14098 } u_sc_hilink0_macro_bit_slip; 14099 14100 14101 typedef union 14102 { 14103 14104 struct 14105 { 14106 UINT32 hilink0_lrstb : 8 ; 14107 UINT32 reserved_0 : 24 ; 14108 } Bits; 14109 14110 14111 UINT32 UInt32; 14112 14113 } u_sc_hilink0_macro_lrstb; 14114 14115 14116 typedef union 14117 { 14118 14119 struct 14120 { 14121 UINT32 hilink1_ss_refclk0_x2s : 2 ; 14122 UINT32 hilink1_ss_refclk0_x2n : 2 ; 14123 UINT32 hilink1_ss_refclk0_x2e : 2 ; 14124 UINT32 hilink1_ss_refclk0_x2w : 2 ; 14125 UINT32 hilink1_ss_refclk1_x2s : 2 ; 14126 UINT32 hilink1_ss_refclk1_x2n : 2 ; 14127 UINT32 hilink1_ss_refclk1_x2e : 2 ; 14128 UINT32 hilink1_ss_refclk1_x2w : 2 ; 14129 UINT32 reserved_0 : 16 ; 14130 } Bits; 14131 14132 14133 UINT32 UInt32; 14134 14135 } u_sc_hilink1_macro_ss_refclk; 14136 14137 14138 typedef union 14139 { 14140 14141 struct 14142 { 14143 UINT32 hilink1_cs_refclk0_dirsel0 : 2 ; 14144 UINT32 hilink1_cs_refclk0_dirsel1 : 2 ; 14145 UINT32 hilink1_cs_refclk0_dirsel2 : 2 ; 14146 UINT32 hilink1_cs_refclk0_dirsel3 : 2 ; 14147 UINT32 hilink1_cs_refclk0_dirsel4 : 2 ; 14148 UINT32 hilink1_cs_refclk1_dirsel0 : 2 ; 14149 UINT32 hilink1_cs_refclk1_dirsel1 : 2 ; 14150 UINT32 hilink1_cs_refclk1_dirsel2 : 2 ; 14151 UINT32 hilink1_cs_refclk1_dirsel3 : 2 ; 14152 UINT32 hilink1_cs_refclk1_dirsel4 : 2 ; 14153 UINT32 reserved_0 : 12 ; 14154 } Bits; 14155 14156 14157 UINT32 UInt32; 14158 14159 } u_sc_hilink1_macro_cs_refclk_dirsel; 14160 14161 14162 typedef union 14163 { 14164 14165 struct 14166 { 14167 UINT32 hilink1_lifeclk2dig_sel : 2 ; 14168 UINT32 reserved_0 : 30 ; 14169 } Bits; 14170 14171 14172 UINT32 UInt32; 14173 14174 } u_sc_hilink1_macro_lifeclk2dig_sel; 14175 14176 14177 typedef union 14178 { 14179 14180 struct 14181 { 14182 UINT32 hilink1_core_clk_selext : 1 ; 14183 UINT32 reserved_0 : 31 ; 14184 } Bits; 14185 14186 14187 UINT32 UInt32; 14188 14189 } u_sc_hilink1_macro_core_clk_selext; 14190 14191 14192 typedef union 14193 { 14194 14195 struct 14196 { 14197 UINT32 hilink1_core_clk_sel : 1 ; 14198 UINT32 reserved_0 : 31 ; 14199 } Bits; 14200 14201 14202 UINT32 UInt32; 14203 14204 } u_sc_hilink1_macro_core_clk_sel; 14205 14206 14207 typedef union 14208 { 14209 14210 struct 14211 { 14212 UINT32 hilink1_ctrl_bus_mode : 2 ; 14213 UINT32 reserved_0 : 30 ; 14214 } Bits; 14215 14216 14217 UINT32 UInt32; 14218 14219 } u_sc_hilink1_macro_ctrl_bus_mode; 14220 14221 14222 typedef union 14223 { 14224 14225 struct 14226 { 14227 UINT32 hilink1_macropwrdb : 1 ; 14228 UINT32 reserved_0 : 31 ; 14229 } Bits; 14230 14231 14232 UINT32 UInt32; 14233 14234 } u_sc_hilink1_macro_macropwrdb; 14235 14236 14237 typedef union 14238 { 14239 14240 struct 14241 { 14242 UINT32 hilink1_grstb : 1 ; 14243 UINT32 reserved_0 : 31 ; 14244 } Bits; 14245 14246 14247 UINT32 UInt32; 14248 14249 } u_sc_hilink1_macro_grstb; 14250 14251 14252 typedef union 14253 { 14254 14255 struct 14256 { 14257 UINT32 hilink1_bit_slip : 8 ; 14258 UINT32 reserved_0 : 24 ; 14259 } Bits; 14260 14261 14262 UINT32 UInt32; 14263 14264 } u_sc_hilink1_macro_bit_slip; 14265 14266 14267 typedef union 14268 { 14269 14270 struct 14271 { 14272 UINT32 hilink1_lrstb : 8 ; 14273 UINT32 reserved_0 : 24 ; 14274 } Bits; 14275 14276 14277 UINT32 UInt32; 14278 14279 } u_sc_hilink1_macro_lrstb; 14280 14281 14282 typedef union 14283 { 14284 14285 struct 14286 { 14287 UINT32 hilink5_ss_refclk0_x2s : 2 ; 14288 UINT32 hilink5_ss_refclk0_x2n : 2 ; 14289 UINT32 hilink5_ss_refclk0_x2e : 2 ; 14290 UINT32 hilink5_ss_refclk0_x2w : 2 ; 14291 UINT32 hilink5_ss_refclk1_x2s : 2 ; 14292 UINT32 hilink5_ss_refclk1_x2n : 2 ; 14293 UINT32 hilink5_ss_refclk1_x2e : 2 ; 14294 UINT32 hilink5_ss_refclk1_x2w : 2 ; 14295 UINT32 reserved_0 : 16 ; 14296 } Bits; 14297 14298 14299 UINT32 UInt32; 14300 14301 } u_sc_hilink5_macro_ss_refclk; 14302 14303 14304 typedef union 14305 { 14306 14307 struct 14308 { 14309 UINT32 hilink5_cs_refclk0_dirsel0 : 2 ; 14310 UINT32 hilink5_cs_refclk0_dirsel1 : 2 ; 14311 UINT32 hilink5_cs_refclk0_dirsel2 : 2 ; 14312 UINT32 hilink5_cs_refclk0_dirsel3 : 2 ; 14313 UINT32 hilink5_cs_refclk0_dirsel4 : 2 ; 14314 UINT32 hilink5_cs_refclk1_dirsel0 : 2 ; 14315 UINT32 hilink5_cs_refclk1_dirsel1 : 2 ; 14316 UINT32 hilink5_cs_refclk1_dirsel2 : 2 ; 14317 UINT32 hilink5_cs_refclk1_dirsel3 : 2 ; 14318 UINT32 hilink5_cs_refclk1_dirsel4 : 2 ; 14319 UINT32 reserved_0 : 12 ; 14320 } Bits; 14321 14322 14323 UINT32 UInt32; 14324 14325 } u_sc_hilink5_macro_cs_refclk_dirsel; 14326 14327 14328 typedef union 14329 { 14330 14331 struct 14332 { 14333 UINT32 hilink5_lifeclk2dig_sel : 2 ; 14334 UINT32 reserved_0 : 30 ; 14335 } Bits; 14336 14337 14338 UINT32 UInt32; 14339 14340 } u_sc_hilink5_macro_lifeclk2dig_sel; 14341 14342 14343 typedef union 14344 { 14345 14346 struct 14347 { 14348 UINT32 hilink5_core_clk_selext : 1 ; 14349 UINT32 reserved_0 : 31 ; 14350 } Bits; 14351 14352 14353 UINT32 UInt32; 14354 14355 } u_sc_hilink5_macro_core_clk_selext; 14356 14357 14358 typedef union 14359 { 14360 14361 struct 14362 { 14363 UINT32 hilink5_core_clk_sel : 1 ; 14364 UINT32 reserved_0 : 31 ; 14365 } Bits; 14366 14367 14368 UINT32 UInt32; 14369 14370 } u_sc_hilink5_macro_core_clk_sel; 14371 14372 14373 typedef union 14374 { 14375 14376 struct 14377 { 14378 UINT32 hilink5_ctrl_bus_mode : 2 ; 14379 UINT32 reserved_0 : 30 ; 14380 } Bits; 14381 14382 14383 UINT32 UInt32; 14384 14385 } u_sc_hilink5_macro_ctrl_bus_mode; 14386 14387 14388 typedef union 14389 { 14390 14391 struct 14392 { 14393 UINT32 hilink5_macropwrdb : 1 ; 14394 UINT32 reserved_0 : 31 ; 14395 } Bits; 14396 14397 14398 UINT32 UInt32; 14399 14400 } u_sc_hilink5_macro_macropwrdb; 14401 14402 14403 typedef union 14404 { 14405 14406 struct 14407 { 14408 UINT32 hilink5_grstb : 1 ; 14409 UINT32 reserved_0 : 31 ; 14410 } Bits; 14411 14412 14413 UINT32 UInt32; 14414 14415 } u_sc_hilink5_macro_grstb; 14416 14417 14418 typedef union 14419 { 14420 14421 struct 14422 { 14423 UINT32 hilink5_bit_slip : 4 ; 14424 UINT32 reserved_0 : 28 ; 14425 } Bits; 14426 14427 14428 UINT32 UInt32; 14429 14430 } u_sc_hilink5_macro_bit_slip; 14431 14432 14433 typedef union 14434 { 14435 14436 struct 14437 { 14438 UINT32 hilink5_lrstb : 4 ; 14439 UINT32 reserved_0 : 28 ; 14440 } Bits; 14441 14442 14443 UINT32 UInt32; 14444 14445 } u_sc_hilink5_macro_lrstb; 14446 14447 14448 typedef union 14449 { 14450 14451 struct 14452 { 14453 UINT32 hilink6_ss_refclk0_x2s : 2 ; 14454 UINT32 hilink6_ss_refclk0_x2n : 2 ; 14455 UINT32 hilink6_ss_refclk0_x2e : 2 ; 14456 UINT32 hilink6_ss_refclk0_x2w : 2 ; 14457 UINT32 hilink6_ss_refclk1_x2s : 2 ; 14458 UINT32 hilink6_ss_refclk1_x2n : 2 ; 14459 UINT32 hilink6_ss_refclk1_x2e : 2 ; 14460 UINT32 hilink6_ss_refclk1_x2w : 2 ; 14461 UINT32 reserved_0 : 16 ; 14462 } Bits; 14463 14464 14465 UINT32 UInt32; 14466 14467 } u_sc_hilink6_macro_ss_refclk; 14468 14469 14470 typedef union 14471 { 14472 14473 struct 14474 { 14475 UINT32 hilink6_cs_refclk0_dirsel0 : 2 ; 14476 UINT32 hilink6_cs_refclk0_dirsel1 : 2 ; 14477 UINT32 hilink6_cs_refclk0_dirsel2 : 2 ; 14478 UINT32 hilink6_cs_refclk0_dirsel3 : 2 ; 14479 UINT32 hilink6_cs_refclk0_dirsel4 : 2 ; 14480 UINT32 hilink6_cs_refclk1_dirsel0 : 2 ; 14481 UINT32 hilink6_cs_refclk1_dirsel1 : 2 ; 14482 UINT32 hilink6_cs_refclk1_dirsel2 : 2 ; 14483 UINT32 hilink6_cs_refclk1_dirsel3 : 2 ; 14484 UINT32 hilink6_cs_refclk1_dirsel4 : 2 ; 14485 UINT32 reserved_0 : 12 ; 14486 } Bits; 14487 14488 14489 UINT32 UInt32; 14490 14491 } u_sc_hilink6_macro_cs_refclk_dirsel; 14492 14493 14494 typedef union 14495 { 14496 14497 struct 14498 { 14499 UINT32 hilink6_lifeclk2dig_sel : 2 ; 14500 UINT32 reserved_0 : 30 ; 14501 } Bits; 14502 14503 14504 UINT32 UInt32; 14505 14506 } u_sc_hilink6_macro_lifeclk2dig_sel; 14507 14508 14509 typedef union 14510 { 14511 14512 struct 14513 { 14514 UINT32 hilink6_core_clk_selext : 1 ; 14515 UINT32 reserved_0 : 31 ; 14516 } Bits; 14517 14518 14519 UINT32 UInt32; 14520 14521 } u_sc_hilink6_macro_core_clk_selext; 14522 14523 14524 typedef union 14525 { 14526 14527 struct 14528 { 14529 UINT32 hilink6_core_clk_sel : 1 ; 14530 UINT32 reserved_0 : 31 ; 14531 } Bits; 14532 14533 14534 UINT32 UInt32; 14535 14536 } u_sc_hilink6_macro_core_clk_sel; 14537 14538 14539 typedef union 14540 { 14541 14542 struct 14543 { 14544 UINT32 hilink6_ctrl_bus_mode : 2 ; 14545 UINT32 reserved_0 : 30 ; 14546 } Bits; 14547 14548 14549 UINT32 UInt32; 14550 14551 } u_sc_hilink6_macro_ctrl_bus_mode; 14552 14553 14554 typedef union 14555 { 14556 14557 struct 14558 { 14559 UINT32 hilink6_macropwrdb : 1 ; 14560 UINT32 reserved_0 : 31 ; 14561 } Bits; 14562 14563 14564 UINT32 UInt32; 14565 14566 } u_sc_hilink6_macro_macropwrdb; 14567 14568 14569 typedef union 14570 { 14571 14572 struct 14573 { 14574 UINT32 hilink6_grstb : 1 ; 14575 UINT32 reserved_0 : 31 ; 14576 } Bits; 14577 14578 14579 UINT32 UInt32; 14580 14581 } u_sc_hilink6_macro_grstb; 14582 14583 14584 typedef union 14585 { 14586 14587 struct 14588 { 14589 UINT32 hilink6_bit_slip : 4 ; 14590 UINT32 reserved_0 : 28 ; 14591 } Bits; 14592 14593 14594 UINT32 UInt32; 14595 14596 } u_sc_hilink6_macro_bit_slip; 14597 14598 14599 typedef union 14600 { 14601 14602 struct 14603 { 14604 UINT32 hilink6_lrstb : 4 ; 14605 UINT32 reserved_0 : 28 ; 14606 } Bits; 14607 14608 14609 UINT32 UInt32; 14610 14611 } u_sc_hilink6_macro_lrstb; 14612 14613 14614 typedef union 14615 { 14616 14617 struct 14618 { 14619 UINT32 pcie0_phy_clk_req_n : 1 ; 14620 UINT32 pcie0_apb_cfg_sel : 2 ; 14621 UINT32 reserved_0 : 29 ; 14622 } Bits; 14623 14624 14625 UINT32 UInt32; 14626 14627 } u_sc_pcie0_clkreq; 14628 14629 14630 typedef union 14631 { 14632 14633 struct 14634 { 14635 UINT32 pcie0_cfg_max_wr_trans : 6 ; 14636 UINT32 reserved_0 : 2 ; 14637 UINT32 pcie0_wr_rate_limit : 4 ; 14638 UINT32 pcie0_ctrl_lat_stat_wr_en : 1 ; 14639 UINT32 reserved_1 : 3 ; 14640 UINT32 pcie0_en_device_wr_ooo : 1 ; 14641 UINT32 reserved_2 : 15 ; 14642 } Bits; 14643 14644 14645 UINT32 UInt32; 14646 14647 } u_sc_pcie0_axi_mstr_ooo_wr_cfg; 14648 14649 14650 typedef union 14651 { 14652 14653 struct 14654 { 14655 UINT32 pcie0_cfg_max_rd_trans : 6 ; 14656 UINT32 reserved_0 : 2 ; 14657 UINT32 pcie0_rd_rate_limit : 4 ; 14658 UINT32 pcie0_ctrl_lat_stat_rd_en : 1 ; 14659 UINT32 reserved_1 : 3 ; 14660 UINT32 pcie0_en_device_rd_ooo : 1 ; 14661 UINT32 reserved_2 : 15 ; 14662 } Bits; 14663 14664 14665 UINT32 UInt32; 14666 14667 } u_sc_pcie0_axi_mstr_ooo_rd_cfg; 14668 14669 14670 typedef union 14671 { 14672 14673 struct 14674 { 14675 UINT32 pcie1hilink_phy_clk_req_n : 1 ; 14676 UINT32 pcie1vsemi_phy_clk_req_n : 1 ; 14677 UINT32 pcie1_apb_cfg_sel : 2 ; 14678 UINT32 reserved_0 : 28 ; 14679 } Bits; 14680 14681 14682 UINT32 UInt32; 14683 14684 } u_sc_pcie1_clkreq; 14685 14686 14687 typedef union 14688 { 14689 14690 struct 14691 { 14692 UINT32 pcie1_cfg_max_wr_trans : 6 ; 14693 UINT32 reserved_0 : 2 ; 14694 UINT32 pcie1_wr_rate_limit : 4 ; 14695 UINT32 pcie1_ctrl_lat_stat_wr_en : 1 ; 14696 UINT32 reserved_1 : 3 ; 14697 UINT32 pcie1_en_device_wr_ooo : 1 ; 14698 UINT32 reserved_2 : 15 ; 14699 } Bits; 14700 14701 14702 UINT32 UInt32; 14703 14704 } u_sc_pcie1_axi_mstr_ooo_wr_cfg; 14705 14706 14707 typedef union 14708 { 14709 14710 struct 14711 { 14712 UINT32 pcie1_cfg_max_rd_trans : 6 ; 14713 UINT32 reserved_0 : 2 ; 14714 UINT32 pcie1_rd_rate_limit : 4 ; 14715 UINT32 pcie1_ctrl_lat_stat_rd_en : 1 ; 14716 UINT32 reserved_1 : 3 ; 14717 UINT32 pcie1_en_device_rd_ooo : 1 ; 14718 UINT32 reserved_2 : 15 ; 14719 } Bits; 14720 14721 14722 UINT32 UInt32; 14723 14724 } u_sc_pcie1_axi_mstr_ooo_rd_cfg; 14725 14726 14727 typedef union 14728 { 14729 14730 struct 14731 { 14732 UINT32 pcie2hilink_phy_clk_req_n : 1 ; 14733 UINT32 pcie2vsemi_phy_clk_req_n : 1 ; 14734 UINT32 pcie2_apb_cfg_sel : 2 ; 14735 UINT32 reserved_0 : 28 ; 14736 } Bits; 14737 14738 14739 UINT32 UInt32; 14740 14741 } u_sc_pcie2_clkreq; 14742 14743 14744 typedef union 14745 { 14746 14747 struct 14748 { 14749 UINT32 pcie2_cfg_max_wr_trans : 6 ; 14750 UINT32 reserved_0 : 2 ; 14751 UINT32 pcie2_wr_rate_limit : 4 ; 14752 UINT32 pcie2_ctrl_lat_stat_wr_en : 1 ; 14753 UINT32 reserved_1 : 3 ; 14754 UINT32 pcie2_en_device_wr_ooo : 1 ; 14755 UINT32 reserved_2 : 15 ; 14756 } Bits; 14757 14758 14759 UINT32 UInt32; 14760 14761 } u_sc_pcie2_axi_mstr_ooo_wr_cfg; 14762 14763 14764 typedef union 14765 { 14766 14767 struct 14768 { 14769 UINT32 pcie2_cfg_max_rd_trans : 6 ; 14770 UINT32 reserved_0 : 2 ; 14771 UINT32 pcie2_rd_rate_limit : 4 ; 14772 UINT32 pcie2_ctrl_lat_stat_rd_en : 1 ; 14773 UINT32 reserved_1 : 3 ; 14774 UINT32 pcie2_en_device_rd_ooo : 1 ; 14775 UINT32 reserved_2 : 15 ; 14776 } Bits; 14777 14778 14779 UINT32 UInt32; 14780 14781 } u_sc_pcie2_axi_mstr_ooo_rd_cfg; 14782 14783 14784 typedef union 14785 { 14786 14787 struct 14788 { 14789 UINT32 pcie3_phy_clk_req_n : 1 ; 14790 UINT32 pcie3_apb_cfg_sel : 2 ; 14791 UINT32 reserved_0 : 29 ; 14792 } Bits; 14793 14794 14795 UINT32 UInt32; 14796 14797 } u_sc_pcie3_clkreq; 14798 14799 14800 typedef union 14801 { 14802 14803 struct 14804 { 14805 UINT32 ctrl_rfs_smmu : 8 ; 14806 UINT32 reserved_0 : 24 ; 14807 } Bits; 14808 14809 14810 UINT32 UInt32; 14811 14812 } u_sc_smmu_mem_ctrl0; 14813 14814 14815 typedef union 14816 { 14817 14818 struct 14819 { 14820 UINT32 tsel_hc_smmu : 3 ; 14821 UINT32 reserved_0 : 29 ; 14822 } Bits; 14823 14824 14825 UINT32 UInt32; 14826 14827 } u_sc_smmu_mem_ctrl1; 14828 14829 14830 typedef union 14831 { 14832 14833 struct 14834 { 14835 UINT32 test_hc_smmu : 2 ; 14836 UINT32 reserved_0 : 30 ; 14837 } Bits; 14838 14839 14840 UINT32 UInt32; 14841 14842 } u_sc_smmu_mem_ctrl2; 14843 14844 14845 typedef union 14846 { 14847 14848 struct 14849 { 14850 UINT32 ctrl_rft_sllc0 : 10 ; 14851 UINT32 reserved_0 : 22 ; 14852 } Bits; 14853 14854 14855 UINT32 UInt32; 14856 14857 } u_sc_sllc0_mem_ctrl; 14858 14859 14860 typedef union 14861 { 14862 14863 struct 14864 { 14865 UINT32 ctrl_rfs_sas : 8 ; 14866 UINT32 reserved_0 : 24 ; 14867 } Bits; 14868 14869 14870 UINT32 UInt32; 14871 14872 } u_sc_sas_mem_ctrl; 14873 14874 14875 typedef union 14876 { 14877 14878 struct 14879 { 14880 UINT32 ctrl_rft_pcie : 10 ; 14881 UINT32 reserved_0 : 22 ; 14882 } Bits; 14883 14884 14885 UINT32 UInt32; 14886 14887 } u_sc_pcie_mem_ctrl0; 14888 14889 14890 typedef union 14891 { 14892 14893 struct 14894 { 14895 UINT32 ctrl_rashsd_pcie : 8 ; 14896 UINT32 reserved_0 : 24 ; 14897 } Bits; 14898 14899 14900 UINT32 UInt32; 14901 14902 } u_sc_pcie_mem_ctrl1; 14903 14904 14905 typedef union 14906 { 14907 14908 struct 14909 { 14910 UINT32 ctrl_rfs_pcie : 8 ; 14911 UINT32 reserved_0 : 24 ; 14912 } Bits; 14913 14914 14915 UINT32 UInt32; 14916 14917 } u_sc_pcie_mem_ctrl2; 14918 14919 14920 typedef union 14921 { 14922 14923 struct 14924 { 14925 UINT32 skew_en : 1 ; 14926 UINT32 reserved_0 : 31 ; 14927 } Bits; 14928 14929 14930 UINT32 UInt32; 14931 14932 } u_sc_skew_common_0; 14933 14934 14935 typedef union 14936 { 14937 14938 struct 14939 { 14940 UINT32 skew_addr_offset : 5 ; 14941 UINT32 reserved_0 : 27 ; 14942 } Bits; 14943 14944 14945 UINT32 UInt32; 14946 14947 } u_sc_skew_common_1; 14948 14949 14950 typedef union 14951 { 14952 14953 struct 14954 { 14955 UINT32 skew_config_in : 8 ; 14956 UINT32 reserved_0 : 24 ; 14957 } Bits; 14958 14959 14960 UINT32 UInt32; 14961 14962 } u_sc_skew_common_2; 14963 14964 14965 typedef union 14966 { 14967 14968 struct 14969 { 14970 UINT32 skew_bypass_a : 1 ; 14971 UINT32 reserved_0 : 31 ; 14972 } Bits; 14973 14974 14975 UINT32 UInt32; 14976 14977 } u_sc_skew_a_0; 14978 14979 14980 typedef union 14981 { 14982 14983 struct 14984 { 14985 UINT32 skew_config_in_a : 2 ; 14986 UINT32 reserved_0 : 30 ; 14987 } Bits; 14988 14989 14990 UINT32 UInt32; 14991 14992 } u_sc_skew_a_1; 14993 14994 14995 typedef union 14996 { 14997 14998 struct 14999 { 15000 UINT32 skew_out_delay_sel_a : 2 ; 15001 UINT32 skew_in_delay_sel_a : 2 ; 15002 UINT32 reserved_0 : 28 ; 15003 } Bits; 15004 15005 15006 UINT32 UInt32; 15007 15008 } u_sc_skew_a_2; 15009 15010 15011 typedef union 15012 { 15013 15014 struct 15015 { 15016 UINT32 skew_sel_a_1 : 1 ; 15017 UINT32 skew_sel_a_0 : 1 ; 15018 UINT32 reserved_0 : 30 ; 15019 } Bits; 15020 15021 15022 UINT32 UInt32; 15023 15024 } u_sc_skew_a_3; 15025 15026 15027 typedef union 15028 { 15029 15030 struct 15031 { 15032 UINT32 skew_update_en_a : 1 ; 15033 UINT32 reserved_0 : 31 ; 15034 } Bits; 15035 15036 15037 UINT32 UInt32; 15038 15039 } u_sc_skew_a_4; 15040 15041 15042 typedef union 15043 { 15044 15045 struct 15046 { 15047 UINT32 skew_varible_set_a : 16 ; 15048 UINT32 reserved_0 : 16 ; 15049 } Bits; 15050 15051 15052 UINT32 UInt32; 15053 15054 } u_sc_skew_a_5; 15055 15056 15057 typedef union 15058 { 15059 15060 struct 15061 { 15062 UINT32 skew_dcell_set_a_h : 4 ; 15063 UINT32 reserved_0 : 28 ; 15064 } Bits; 15065 15066 15067 UINT32 UInt32; 15068 15069 } u_sc_skew_a_7; 15070 15071 15072 typedef union 15073 { 15074 15075 struct 15076 { 15077 UINT32 skew_sel_osc_a : 1 ; 15078 UINT32 reserved_0 : 31 ; 15079 } Bits; 15080 15081 15082 UINT32 UInt32; 15083 15084 } u_sc_skew_a_8; 15085 15086 15087 typedef union 15088 { 15089 15090 struct 15091 { 15092 UINT32 skew_bypass_b : 1 ; 15093 UINT32 reserved_0 : 31 ; 15094 } Bits; 15095 15096 15097 UINT32 UInt32; 15098 15099 } u_sc_skew_b_0; 15100 15101 15102 typedef union 15103 { 15104 15105 struct 15106 { 15107 UINT32 skew_config_in_b : 2 ; 15108 UINT32 reserved_0 : 30 ; 15109 } Bits; 15110 15111 15112 UINT32 UInt32; 15113 15114 } u_sc_skew_b_1; 15115 15116 15117 typedef union 15118 { 15119 15120 struct 15121 { 15122 UINT32 skew_out_delay_sel_b : 2 ; 15123 UINT32 skew_in_delay_sel_b : 2 ; 15124 UINT32 reserved_0 : 28 ; 15125 } Bits; 15126 15127 15128 UINT32 UInt32; 15129 15130 } u_sc_skew_b_2; 15131 15132 15133 typedef union 15134 { 15135 15136 struct 15137 { 15138 UINT32 skew_sel_b_1 : 1 ; 15139 UINT32 skew_sel_b_0 : 1 ; 15140 UINT32 reserved_0 : 30 ; 15141 } Bits; 15142 15143 15144 UINT32 UInt32; 15145 15146 } u_sc_skew_b_3; 15147 15148 15149 typedef union 15150 { 15151 15152 struct 15153 { 15154 UINT32 skew_update_en_b : 1 ; 15155 UINT32 reserved_0 : 31 ; 15156 } Bits; 15157 15158 15159 UINT32 UInt32; 15160 15161 } u_sc_skew_b_4; 15162 15163 15164 typedef union 15165 { 15166 15167 struct 15168 { 15169 UINT32 skew_varible_set_b : 16 ; 15170 UINT32 reserved_0 : 16 ; 15171 } Bits; 15172 15173 15174 UINT32 UInt32; 15175 15176 } u_sc_skew_b_5; 15177 15178 15179 typedef union 15180 { 15181 15182 struct 15183 { 15184 UINT32 skew_dcell_set_b_h : 4 ; 15185 UINT32 reserved_0 : 28 ; 15186 } Bits; 15187 15188 15189 UINT32 UInt32; 15190 15191 } u_sc_skew_b_7; 15192 15193 15194 typedef union 15195 { 15196 15197 struct 15198 { 15199 UINT32 skew_sel_osc_b : 1 ; 15200 UINT32 reserved_0 : 31 ; 15201 } Bits; 15202 15203 15204 UINT32 UInt32; 15205 15206 } u_sc_skew_b_8; 15207 15208 15209 typedef union 15210 { 15211 15212 struct 15213 { 15214 UINT32 clk_pcie0_st : 1 ; 15215 UINT32 clk_pcie0_pipe_st : 1 ; 15216 UINT32 reserved_0 : 30 ; 15217 } Bits; 15218 15219 15220 UINT32 UInt32; 15221 15222 } u_sc_pcie0_clk_st; 15223 15224 15225 typedef union 15226 { 15227 15228 struct 15229 { 15230 UINT32 clk_pcie1_st : 1 ; 15231 UINT32 clk_pcie1_pipe_st : 1 ; 15232 UINT32 reserved_0 : 30 ; 15233 } Bits; 15234 15235 15236 UINT32 UInt32; 15237 15238 } u_sc_pcie1_clk_st; 15239 15240 15241 typedef union 15242 { 15243 15244 struct 15245 { 15246 UINT32 clk_pcie2_st : 1 ; 15247 UINT32 clk_pcie2_pipe_st : 1 ; 15248 UINT32 reserved_0 : 30 ; 15249 } Bits; 15250 15251 15252 UINT32 UInt32; 15253 15254 } u_sc_pcie2_clk_st; 15255 15256 15257 typedef union 15258 { 15259 15260 struct 15261 { 15262 UINT32 clk_sas_st : 1 ; 15263 UINT32 clk_sas_mem_st : 1 ; 15264 UINT32 clk_sas_ahb_st : 1 ; 15265 UINT32 clk_sas_oob_st : 1 ; 15266 UINT32 clk_sas_ch0_rx_st : 1 ; 15267 UINT32 clk_sas_ch1_rx_st : 1 ; 15268 UINT32 clk_sas_ch2_rx_st : 1 ; 15269 UINT32 clk_sas_ch3_rx_st : 1 ; 15270 UINT32 clk_sas_ch4_rx_st : 1 ; 15271 UINT32 clk_sas_ch5_rx_st : 1 ; 15272 UINT32 clk_sas_ch6_rx_st : 1 ; 15273 UINT32 clk_sas_ch7_rx_st : 1 ; 15274 UINT32 clk_sas_ch0_tx_st : 1 ; 15275 UINT32 clk_sas_ch1_tx_st : 1 ; 15276 UINT32 clk_sas_ch2_tx_st : 1 ; 15277 UINT32 clk_sas_ch3_tx_st : 1 ; 15278 UINT32 clk_sas_ch4_tx_st : 1 ; 15279 UINT32 clk_sas_ch5_tx_st : 1 ; 15280 UINT32 clk_sas_ch6_tx_st : 1 ; 15281 UINT32 clk_sas_ch7_tx_st : 1 ; 15282 UINT32 reserved_0 : 12 ; 15283 } Bits; 15284 15285 15286 UINT32 UInt32; 15287 15288 } u_sc_sas_clk_st; 15289 15290 15291 typedef union 15292 { 15293 15294 struct 15295 { 15296 UINT32 clk_pcie3_st : 1 ; 15297 UINT32 clk_pcie3_pipe_st : 1 ; 15298 UINT32 reserved_0 : 30 ; 15299 } Bits; 15300 15301 15302 UINT32 UInt32; 15303 15304 } u_sc_pcie3_clk_st; 15305 15306 15307 typedef union 15308 { 15309 15310 struct 15311 { 15312 UINT32 clk_its_st : 1 ; 15313 UINT32 reserved_0 : 31 ; 15314 } Bits; 15315 15316 15317 UINT32 UInt32; 15318 15319 } u_sc_its_clk_st; 15320 15321 15322 typedef union 15323 { 15324 15325 struct 15326 { 15327 UINT32 clk_sllc_st : 1 ; 15328 UINT32 reserved_0 : 31 ; 15329 } Bits; 15330 15331 15332 UINT32 UInt32; 15333 15334 } u_sc_sllc_clk_st; 15335 15336 15337 typedef union 15338 { 15339 15340 struct 15341 { 15342 UINT32 pcie0_srst_st : 1 ; 15343 UINT32 reserved_0 : 31 ; 15344 } Bits; 15345 15346 15347 UINT32 UInt32; 15348 15349 } u_sc_pcie0_reset_st; 15350 15351 15352 typedef union 15353 { 15354 15355 struct 15356 { 15357 UINT32 pcie1_srst_st : 1 ; 15358 UINT32 reserved_0 : 31 ; 15359 } Bits; 15360 15361 15362 UINT32 UInt32; 15363 15364 } u_sc_pcie1_reset_st; 15365 15366 15367 typedef union 15368 { 15369 15370 struct 15371 { 15372 UINT32 pcie2_srst_st : 1 ; 15373 UINT32 reserved_0 : 31 ; 15374 } Bits; 15375 15376 15377 UINT32 UInt32; 15378 15379 } u_sc_pcie2_reset_st; 15380 15381 15382 typedef union 15383 { 15384 15385 struct 15386 { 15387 UINT32 sas_srst_st : 1 ; 15388 UINT32 sas_oob_srst_st : 1 ; 15389 UINT32 sas_ahb_srst_st : 1 ; 15390 UINT32 sas_ch0_rx_srst_st : 1 ; 15391 UINT32 sas_ch1_rx_srst_st : 1 ; 15392 UINT32 sas_ch2_rx_srst_st : 1 ; 15393 UINT32 sas_ch3_rx_srst_st : 1 ; 15394 UINT32 sas_ch4_rx_srst_st : 1 ; 15395 UINT32 sas_ch5_rx_srst_st : 1 ; 15396 UINT32 sas_ch6_rx_srst_st : 1 ; 15397 UINT32 sas_ch7_rx_srst_st : 1 ; 15398 UINT32 sas_ch0_tx_srst_st : 1 ; 15399 UINT32 sas_ch1_tx_srst_st : 1 ; 15400 UINT32 sas_ch2_tx_srst_st : 1 ; 15401 UINT32 sas_ch3_tx_srst_st : 1 ; 15402 UINT32 sas_ch4_tx_srst_st : 1 ; 15403 UINT32 sas_ch5_tx_srst_st : 1 ; 15404 UINT32 sas_ch6_tx_srst_st : 1 ; 15405 UINT32 sas_ch7_tx_srst_st : 1 ; 15406 UINT32 reserved_0 : 13 ; 15407 } Bits; 15408 15409 15410 UINT32 UInt32; 15411 15412 } u_sc_sas_reset_st; 15413 15414 15415 typedef union 15416 { 15417 15418 struct 15419 { 15420 UINT32 mctp0_srst_st : 1 ; 15421 UINT32 reserved_0 : 31 ; 15422 } Bits; 15423 15424 15425 UINT32 UInt32; 15426 15427 } u_sc_mctp0_reset_st; 15428 15429 15430 typedef union 15431 { 15432 15433 struct 15434 { 15435 UINT32 mctp1_srst_st : 1 ; 15436 UINT32 reserved_0 : 31 ; 15437 } Bits; 15438 15439 15440 UINT32 UInt32; 15441 15442 } u_sc_mctp1_reset_st; 15443 15444 15445 typedef union 15446 { 15447 15448 struct 15449 { 15450 UINT32 mctp2_srst_st : 1 ; 15451 UINT32 reserved_0 : 31 ; 15452 } Bits; 15453 15454 15455 UINT32 UInt32; 15456 15457 } u_sc_mctp2_reset_st; 15458 15459 15460 typedef union 15461 { 15462 15463 struct 15464 { 15465 UINT32 sllc_tsvrx0_srst_st : 1 ; 15466 UINT32 sllc_tsvrx1_srst_st : 1 ; 15467 UINT32 sllc_tsvrx2_srst_st : 1 ; 15468 UINT32 sllc_tsvrx3_srst_st : 1 ; 15469 UINT32 reserved_0 : 28 ; 15470 } Bits; 15471 15472 15473 UINT32 UInt32; 15474 15475 } u_sc_sllc_tsvrx_reset_st; 15476 15477 15478 typedef union 15479 { 15480 15481 struct 15482 { 15483 UINT32 pcie0_hilink_pcs_lane0_srst_st : 1 ; 15484 UINT32 pcie0_hilink_pcs_lane1_srst_st : 1 ; 15485 UINT32 pcie0_hilink_pcs_lane2_srst_st : 1 ; 15486 UINT32 pcie0_hilink_pcs_lane3_srst_st : 1 ; 15487 UINT32 pcie0_hilink_pcs_lane4_srst_st : 1 ; 15488 UINT32 pcie0_hilink_pcs_lane5_srst_st : 1 ; 15489 UINT32 pcie0_hilink_pcs_lane6_srst_st : 1 ; 15490 UINT32 pcie0_hilink_pcs_lane7_srst_st : 1 ; 15491 UINT32 pcie1_hilink_pcs_lane0_srst_st : 1 ; 15492 UINT32 pcie1_hilink_pcs_lane1_srst_st : 1 ; 15493 UINT32 pcie1_hilink_pcs_lane2_srst_st : 1 ; 15494 UINT32 pcie1_hilink_pcs_lane3_srst_st : 1 ; 15495 UINT32 pcie1_hilink_pcs_lane4_srst_st : 1 ; 15496 UINT32 pcie1_hilink_pcs_lane5_srst_st : 1 ; 15497 UINT32 pcie1_hilink_pcs_lane6_srst_st : 1 ; 15498 UINT32 pcie1_hilink_pcs_lane7_srst_st : 1 ; 15499 UINT32 pcie2_hilink_pcs_lane0_srst_st : 1 ; 15500 UINT32 pcie2_hilink_pcs_lane1_srst_st : 1 ; 15501 UINT32 pcie2_hilink_pcs_lane2_srst_st : 1 ; 15502 UINT32 pcie2_hilink_pcs_lane3_srst_st : 1 ; 15503 UINT32 pcie2_hilink_pcs_lane4_srst_st : 1 ; 15504 UINT32 pcie2_hilink_pcs_lane5_srst_st : 1 ; 15505 UINT32 pcie2_hilink_pcs_lane6_srst_st : 1 ; 15506 UINT32 pcie2_hilink_pcs_lane7_srst_st : 1 ; 15507 UINT32 pcie3_hilink_pcs_lane0_srst_st : 1 ; 15508 UINT32 pcie3_hilink_pcs_lane1_srst_st : 1 ; 15509 UINT32 pcie3_hilink_pcs_lane2_srst_st : 1 ; 15510 UINT32 pcie3_hilink_pcs_lane3_srst_st : 1 ; 15511 UINT32 pcie3_hilink_pcs_lane4_srst_st : 1 ; 15512 UINT32 pcie3_hilink_pcs_lane5_srst_st : 1 ; 15513 UINT32 pcie3_hilink_pcs_lane6_srst_st : 1 ; 15514 UINT32 pcie3_hilink_pcs_lane7_srst_st : 1 ; 15515 } Bits; 15516 15517 15518 UINT32 UInt32; 15519 15520 } u_sc_pcie_hilink_pcs_reset_st; 15521 15522 15523 typedef union 15524 { 15525 15526 struct 15527 { 15528 UINT32 pcie3_srst_st : 1 ; 15529 UINT32 reserved_0 : 31 ; 15530 } Bits; 15531 15532 15533 UINT32 UInt32; 15534 15535 } u_sc_pcie3_reset_st; 15536 15537 15538 typedef union 15539 { 15540 15541 struct 15542 { 15543 UINT32 mctp3_srst_st : 1 ; 15544 UINT32 reserved_0 : 31 ; 15545 } Bits; 15546 15547 15548 UINT32 UInt32; 15549 15550 } u_sc_mctp3_reset_st; 15551 15552 15553 typedef union 15554 { 15555 15556 struct 15557 { 15558 UINT32 its_srst_st : 1 ; 15559 UINT32 reserved_0 : 31 ; 15560 } Bits; 15561 15562 15563 UINT32 UInt32; 15564 15565 } u_sc_its_reset_st; 15566 15567 15568 typedef union 15569 { 15570 15571 struct 15572 { 15573 UINT32 sllc_srst_st : 1 ; 15574 UINT32 reserved_0 : 31 ; 15575 } Bits; 15576 15577 15578 UINT32 UInt32; 15579 15580 } u_sc_sllc_reset_st; 15581 15582 15583 typedef union 15584 { 15585 15586 struct 15587 { 15588 UINT32 pcie0_pcs_local_srst_st : 1 ; 15589 UINT32 pcie1_pcs_local_srst_st : 1 ; 15590 UINT32 pcie2_pcs_local_srst_st : 1 ; 15591 UINT32 pcie3_pcs_local_srst_st : 1 ; 15592 UINT32 reserved_0 : 28 ; 15593 } Bits; 15594 15595 15596 UINT32 UInt32; 15597 15598 } u_sc_pcs_local_reset_st; 15599 15600 15601 typedef union 15602 { 15603 15604 struct 15605 { 15606 UINT32 hilink0_plloutoflock : 2 ; 15607 UINT32 reserved_0 : 30 ; 15608 } Bits; 15609 15610 15611 UINT32 UInt32; 15612 15613 } u_sc_hilink0_macro_plloutoflock; 15614 15615 15616 typedef union 15617 { 15618 15619 struct 15620 { 15621 UINT32 hilink0_prbs_err : 8 ; 15622 UINT32 reserved_0 : 24 ; 15623 } Bits; 15624 15625 15626 UINT32 UInt32; 15627 15628 } u_sc_hilink0_macro_prbs_err; 15629 15630 15631 typedef union 15632 { 15633 15634 struct 15635 { 15636 UINT32 hilink0_los : 8 ; 15637 UINT32 reserved_0 : 24 ; 15638 } Bits; 15639 15640 15641 UINT32 UInt32; 15642 15643 } u_sc_hilink0_macro_los; 15644 15645 15646 typedef union 15647 { 15648 15649 struct 15650 { 15651 UINT32 hilink1_plloutoflock : 2 ; 15652 UINT32 reserved_0 : 30 ; 15653 } Bits; 15654 15655 15656 UINT32 UInt32; 15657 15658 } u_sc_hilink1_macro_plloutoflock; 15659 15660 15661 typedef union 15662 { 15663 15664 struct 15665 { 15666 UINT32 hilink1_prbs_err : 8 ; 15667 UINT32 reserved_0 : 24 ; 15668 } Bits; 15669 15670 15671 UINT32 UInt32; 15672 15673 } u_sc_hilink1_macro_prbs_err; 15674 15675 15676 typedef union 15677 { 15678 15679 struct 15680 { 15681 UINT32 hilink1_los : 8 ; 15682 UINT32 reserved_0 : 24 ; 15683 } Bits; 15684 15685 15686 UINT32 UInt32; 15687 15688 } u_sc_hilink1_macro_los; 15689 15690 15691 typedef union 15692 { 15693 15694 struct 15695 { 15696 UINT32 hilink5_plloutoflock : 2 ; 15697 UINT32 reserved_0 : 30 ; 15698 } Bits; 15699 15700 15701 UINT32 UInt32; 15702 15703 } u_sc_hilink5_macro_plloutoflock; 15704 15705 15706 typedef union 15707 { 15708 15709 struct 15710 { 15711 UINT32 hilink5_prbs_err : 4 ; 15712 UINT32 reserved_0 : 28 ; 15713 } Bits; 15714 15715 15716 UINT32 UInt32; 15717 15718 } u_sc_hilink5_macro_prbs_err; 15719 15720 15721 typedef union 15722 { 15723 15724 struct 15725 { 15726 UINT32 hilink5_los : 4 ; 15727 UINT32 reserved_0 : 28 ; 15728 } Bits; 15729 15730 15731 UINT32 UInt32; 15732 15733 } u_sc_hilink5_macro_los; 15734 15735 15736 typedef union 15737 { 15738 15739 struct 15740 { 15741 UINT32 hilink6_plloutoflock : 2 ; 15742 UINT32 reserved_0 : 30 ; 15743 } Bits; 15744 15745 15746 UINT32 UInt32; 15747 15748 } u_sc_hilink6_macro_plloutoflock; 15749 15750 15751 typedef union 15752 { 15753 15754 struct 15755 { 15756 UINT32 hilink6_prbs_err : 4 ; 15757 UINT32 reserved_0 : 28 ; 15758 } Bits; 15759 15760 15761 UINT32 UInt32; 15762 15763 } u_sc_hilink6_macro_prbs_err; 15764 15765 15766 typedef union 15767 { 15768 15769 struct 15770 { 15771 UINT32 hilink6_los : 4 ; 15772 UINT32 reserved_0 : 28 ; 15773 } Bits; 15774 15775 15776 UINT32 UInt32; 15777 15778 } u_sc_hilink6_macro_los; 15779 15780 15781 typedef union 15782 { 15783 15784 struct 15785 { 15786 UINT32 pcie0_mac_phy_rxeqinprogress : 8 ; 15787 UINT32 reserved_0 : 24 ; 15788 } Bits; 15789 15790 15791 UINT32 UInt32; 15792 15793 } u_sc_pcie0_rxeqinpro_stat; 15794 15795 15796 typedef union 15797 { 15798 15799 struct 15800 { 15801 UINT32 pcie0_cfg_link_eq_req_int : 1 ; 15802 UINT32 pcie0_xmlh_ltssm_state_rcvry_eq : 1 ; 15803 UINT32 reserved_0 : 30 ; 15804 } Bits; 15805 15806 15807 UINT32 UInt32; 15808 15809 } u_sc_pcie0_linkint_rcvry_stat; 15810 15811 15812 typedef union 15813 { 15814 15815 struct 15816 { 15817 UINT32 pcie0_gm_cmposer_lookup_err : 1 ; 15818 UINT32 pcie0_radmx_cmposer_lookup_err : 1 ; 15819 UINT32 pcie0_pm_xtlh_block_tlp : 1 ; 15820 UINT32 pcie0_cfg_mem_space_en : 1 ; 15821 UINT32 pcie0_cfg_rcb : 1 ; 15822 UINT32 pcie0_rdlh_link_up : 1 ; 15823 UINT32 pcie0_pm_curnt_state : 3 ; 15824 UINT32 pcie0_cfg_aer_rc_err_int : 1 ; 15825 UINT32 pcie0_cfg_aer_int_msg_num : 5 ; 15826 UINT32 pcie0_xmlh_link_up : 1 ; 15827 UINT32 pcie0_wake : 1 ; 15828 UINT32 pcie0_cfg_eml_control : 1 ; 15829 UINT32 pcie0_hp_pme : 1 ; 15830 UINT32 pcie0_hp_int : 1 ; 15831 UINT32 pcie0_hp_msi : 1 ; 15832 UINT32 pcie0_pm_status : 1 ; 15833 UINT32 pcie0_ref_clk_req_n : 1 ; 15834 UINT32 pcie0_p2_exit_reg : 1 ; 15835 UINT32 pcie0_radm_msg_req_id_low : 8 ; 15836 } Bits; 15837 15838 15839 UINT32 UInt32; 15840 15841 }U_SC_PCIE0_SYS_STATE0; 15842 15843 15844 typedef union 15845 { 15846 15847 struct 15848 { 15849 UINT32 pcie0_axi_parity_errs_reg : 4 ; 15850 UINT32 pcie0_app_parity_errs_reg : 3 ; 15851 UINT32 pcie0_pm_linkst_in_l1 : 1 ; 15852 UINT32 pcie0_pm_linkst_in_l2 : 1 ; 15853 UINT32 pcie0_pm_linkst_l2_exit : 1 ; 15854 UINT32 pcie0_mac_phy_power_down : 2 ; 15855 UINT32 pcie0_radm_correctabl_err_reg : 1 ; 15856 UINT32 pcie0_radm_nonfatal_err_reg : 1 ; 15857 UINT32 pcie0_radm_fatal_err_reg : 1 ; 15858 UINT32 pcie0_radm_pm_to_pme_reg : 1 ; 15859 UINT32 pcie0_radm_pm_to_ack_reg : 1 ; 15860 UINT32 pcie0_radm_cpl_timeout_reg : 1 ; 15861 UINT32 pcie0_radm_msg_unlock_reg : 1 ; 15862 UINT32 pcie0_cfg_pme_msi_reg : 1 ; 15863 UINT32 pcie0_bridge_flush_not_reg : 1 ; 15864 UINT32 pcie0_link_req_rst_not_reg : 1 ; 15865 UINT32 pcie0_cfg_aer_rc_err_msi : 1 ; 15866 UINT32 pcie0_cfg_sys_err_rc : 1 ; 15867 UINT32 pcie0_radm_msg_req_id_high : 8 ; 15868 } Bits; 15869 15870 15871 UINT32 UInt32; 15872 15873 } U_SC_PCIE0_SYS_STATE1; 15874 15875 15876 typedef union 15877 { 15878 15879 struct 15880 { 15881 UINT32 pcie0_ltssm_state : 6 ; 15882 UINT32 pcie0_mac_phy_rate : 2 ; 15883 UINT32 pcie0_slv_err_int : 1 ; 15884 UINT32 pcie0_retry_sram_addr : 10 ; 15885 UINT32 pcie0_mstr_rresp_int : 1 ; 15886 UINT32 pcie0_mstr_bresp_int : 1 ; 15887 UINT32 pcie0_radm_inta_reg : 1 ; 15888 UINT32 pcie0_radm_intb_reg : 1 ; 15889 UINT32 pcie0_radm_intc_reg : 1 ; 15890 UINT32 pcie0_radm_intd_reg : 1 ; 15891 UINT32 pcie0_cfg_pme_int_reg : 1 ; 15892 UINT32 pcie0_radm_vendor_msg_reg : 1 ; 15893 UINT32 pcie0_bridge_flush_not : 1 ; 15894 UINT32 pcie0_link_req_rst_not : 1 ; 15895 UINT32 reserved_0 : 3 ; 15896 } Bits; 15897 15898 15899 UINT32 UInt32; 15900 15901 } U_SC_PCIE0_SYS_STATE4; 15902 15903 15904 typedef union 15905 { 15906 15907 struct 15908 { 15909 UINT32 pcie0_curr_wr_latency : 16 ; 15910 UINT32 pcie0_curr_wr_port_sts : 1 ; 15911 UINT32 reserved_0 : 15 ; 15912 } Bits; 15913 15914 15915 UINT32 UInt32; 15916 15917 } u_sc_pcie0_axi_mstr_ooo_wr_sts1; 15918 15919 15920 typedef union 15921 { 15922 15923 struct 15924 { 15925 UINT32 pcie0_curr_rd_latency : 16 ; 15926 UINT32 pcie0_curr_rd_port_sts : 1 ; 15927 UINT32 reserved_0 : 15 ; 15928 } Bits; 15929 15930 15931 UINT32 UInt32; 15932 15933 } u_sc_pcie0_axi_mstr_ooo_rd_sts1; 15934 15935 15936 typedef union 15937 { 15938 15939 struct 15940 { 15941 UINT32 pcie0_rob_ecc_err_detect : 1 ; 15942 UINT32 pcie0_rob_ecc_err_multpl : 1 ; 15943 UINT32 reserved_0 : 30 ; 15944 } Bits; 15945 15946 15947 UINT32 UInt32; 15948 15949 } u_sc_pcie0_dsize_brg_ecc_err; 15950 15951 15952 typedef union 15953 { 15954 15955 struct 15956 { 15957 UINT32 pcie0_pciephy_ctrl_error : 1 ; 15958 UINT32 reserved_0 : 31 ; 15959 } Bits; 15960 15961 15962 UINT32 UInt32; 15963 15964 } u_sc_pcie0_pciephy_ctrl_error; 15965 15966 15967 typedef union 15968 { 15969 15970 struct 15971 { 15972 UINT32 pcie1_mac_phy_rxeqinprogress : 8 ; 15973 UINT32 reserved_0 : 24 ; 15974 } Bits; 15975 15976 15977 UINT32 UInt32; 15978 15979 } u_sc_pcie1_rxeqinpro_stat; 15980 15981 15982 typedef union 15983 { 15984 15985 struct 15986 { 15987 UINT32 pcie1_cfg_link_eq_req_int : 1 ; 15988 UINT32 pcie1_xmlh_ltssm_state_rcvry_eq : 1 ; 15989 UINT32 reserved_0 : 30 ; 15990 } Bits; 15991 15992 15993 UINT32 UInt32; 15994 15995 } u_sc_pcie1_linkint_rcvry_stat; 15996 15997 15998 typedef union 15999 { 16000 16001 struct 16002 { 16003 UINT32 pcie1_gm_cmposer_lookup_err : 1 ; 16004 UINT32 pcie1_radmx_cmposer_lookup_err : 1 ; 16005 UINT32 pcie1_pm_xtlh_block_tlp : 1 ; 16006 UINT32 pcie1_cfg_mem_space_en : 1 ; 16007 UINT32 pcie1_cfg_rcb : 1 ; 16008 UINT32 pcie1_rdlh_link_up : 1 ; 16009 UINT32 pcie1_pm_curnt_state : 3 ; 16010 UINT32 pcie1_cfg_aer_rc_err_int : 1 ; 16011 UINT32 pcie1_cfg_aer_int_msg_num : 5 ; 16012 UINT32 pcie1_xmlh_link_up : 1 ; 16013 UINT32 pcie1_wake : 1 ; 16014 UINT32 pcie1_cfg_eml_control : 1 ; 16015 UINT32 pcie1_hp_pme : 1 ; 16016 UINT32 pcie1_hp_int : 1 ; 16017 UINT32 pcie1_hp_msi : 1 ; 16018 UINT32 pcie1_pm_status : 1 ; 16019 UINT32 pcie1_ref_clk_req_n : 1 ; 16020 UINT32 pcie1_p2_exit_reg : 1 ; 16021 UINT32 pcie1_radm_msg_req_id_low : 8 ; 16022 } Bits; 16023 16024 16025 UINT32 UInt32; 16026 16027 } u_sc_pcie1_sys_state0; 16028 16029 16030 typedef union 16031 { 16032 16033 struct 16034 { 16035 UINT32 pcie1_axi_parity_errs_reg : 4 ; 16036 UINT32 pcie1_app_parity_errs_reg : 3 ; 16037 UINT32 pcie1_pm_linkst_in_l1 : 1 ; 16038 UINT32 pcie1_pm_linkst_in_l2 : 1 ; 16039 UINT32 pcie1_pm_linkst_l2_exit : 1 ; 16040 UINT32 pcie1_mac_phy_power_down : 2 ; 16041 UINT32 pcie1_radm_correctabl_err_reg : 1 ; 16042 UINT32 pcie1_radm_nonfatal_err_reg : 1 ; 16043 UINT32 pcie1_radm_fatal_err_reg : 1 ; 16044 UINT32 pcie1_radm_pm_to_pme_reg : 1 ; 16045 UINT32 pcie1_radm_pm_to_ack_reg : 1 ; 16046 UINT32 pcie1_radm_cpl_timeout_reg : 1 ; 16047 UINT32 pcie1_radm_msg_unlock_reg : 1 ; 16048 UINT32 pcie1_cfg_pme_msi_reg : 1 ; 16049 UINT32 pcie1_bridge_flush_not_reg : 1 ; 16050 UINT32 pcie1_link_req_rst_not_reg : 1 ; 16051 UINT32 pcie1_cfg_aer_rc_err_msi : 1 ; 16052 UINT32 pcie1_cfg_sys_err_rc : 1 ; 16053 UINT32 pcie1_radm_msg_req_id_high : 8 ; 16054 } Bits; 16055 16056 16057 UINT32 UInt32; 16058 16059 } u_sc_pcie1_sys_state1; 16060 16061 16062 typedef union 16063 { 16064 16065 struct 16066 { 16067 UINT32 pcie1_ltssm_state : 6 ; 16068 UINT32 pcie1_mac_phy_rate : 2 ; 16069 UINT32 pcie1_slv_err_int : 1 ; 16070 UINT32 pcie1_retry_sram_addr : 10 ; 16071 UINT32 pcie1_mstr_rresp_int : 1 ; 16072 UINT32 pcie1_mstr_bresp_int : 1 ; 16073 UINT32 pcie1_radm_inta_reg : 1 ; 16074 UINT32 pcie1_radm_intb_reg : 1 ; 16075 UINT32 pcie1_radm_intc_reg : 1 ; 16076 UINT32 pcie1_radm_intd_reg : 1 ; 16077 UINT32 pcie1_cfg_pme_int_reg : 1 ; 16078 UINT32 pcie1_radm_vendor_msg_reg : 1 ; 16079 UINT32 pcie1_bridge_flush_not : 1 ; 16080 UINT32 pcie1_link_req_rst_not : 1 ; 16081 UINT32 reserved_0 : 3 ; 16082 } Bits; 16083 16084 16085 UINT32 UInt32; 16086 16087 } u_sc_pcie1_sys_state4; 16088 16089 16090 typedef union 16091 { 16092 16093 struct 16094 { 16095 UINT32 pcie1_curr_wr_latency : 16 ; 16096 UINT32 pcie1_curr_wr_port_sts : 1 ; 16097 UINT32 reserved_0 : 15 ; 16098 } Bits; 16099 16100 16101 UINT32 UInt32; 16102 16103 } u_sc_pcie1_axi_mstr_ooo_wr_sts1; 16104 16105 16106 typedef union 16107 { 16108 16109 struct 16110 { 16111 UINT32 pcie1_curr_rd_latency : 16 ; 16112 UINT32 pcie1_curr_rd_port_sts : 1 ; 16113 UINT32 reserved_0 : 15 ; 16114 } Bits; 16115 16116 16117 UINT32 UInt32; 16118 16119 } u_sc_pcie1_axi_mstr_ooo_rd_sts1; 16120 16121 16122 typedef union 16123 { 16124 16125 struct 16126 { 16127 UINT32 pcie1_rob_ecc_err_detect : 1 ; 16128 UINT32 pcie1_rob_ecc_err_multpl : 1 ; 16129 UINT32 reserved_0 : 30 ; 16130 } Bits; 16131 16132 16133 UINT32 UInt32; 16134 16135 } u_sc_pcie1_dsize_brg_ecc_err; 16136 16137 16138 typedef union 16139 { 16140 16141 struct 16142 { 16143 UINT32 pcie1_pciephy_ctrl_error : 1 ; 16144 UINT32 reserved_0 : 31 ; 16145 } Bits; 16146 16147 16148 UINT32 UInt32; 16149 16150 } u_sc_pcie1_pciephy_ctrl_error; 16151 16152 16153 typedef union 16154 { 16155 16156 struct 16157 { 16158 UINT32 pcie2_mac_phy_rxeqinprogress : 8 ; 16159 UINT32 reserved_0 : 24 ; 16160 } Bits; 16161 16162 16163 UINT32 UInt32; 16164 16165 } u_sc_pcie2_rxeqinpro_stat; 16166 16167 16168 typedef union 16169 { 16170 16171 struct 16172 { 16173 UINT32 pcie2_cfg_link_eq_req_int : 1 ; 16174 UINT32 pcie2_xmlh_ltssm_state_rcvry_eq : 1 ; 16175 UINT32 reserved_0 : 30 ; 16176 } Bits; 16177 16178 16179 UINT32 UInt32; 16180 16181 } u_sc_pcie2_linkint_rcvry_stat; 16182 16183 16184 typedef union 16185 { 16186 16187 struct 16188 { 16189 UINT32 pcie2_gm_cmposer_lookup_err : 1 ; 16190 UINT32 pcie2_radmx_cmposer_lookup_err : 1 ; 16191 UINT32 pcie2_pm_xtlh_block_tlp : 1 ; 16192 UINT32 pcie2_cfg_mem_space_en : 1 ; 16193 UINT32 pcie2_cfg_rcb : 1 ; 16194 UINT32 pcie2_rdlh_link_up : 1 ; 16195 UINT32 pcie2_pm_curnt_state : 3 ; 16196 UINT32 pcie2_cfg_aer_rc_err_int : 1 ; 16197 UINT32 pcie2_cfg_aer_int_msg_num : 5 ; 16198 UINT32 pcie2_xmlh_link_up : 1 ; 16199 UINT32 pcie2_wake : 1 ; 16200 UINT32 pcie2_cfg_eml_control : 1 ; 16201 UINT32 pcie2_hp_pme : 1 ; 16202 UINT32 pcie2_hp_int : 1 ; 16203 UINT32 pcie2_hp_msi : 1 ; 16204 UINT32 pcie2_pm_status : 1 ; 16205 UINT32 pcie2_ref_clk_req_n : 1 ; 16206 UINT32 pcie2_p2_exit_reg : 1 ; 16207 UINT32 pcie2_radm_msg_req_id_low : 8 ; 16208 } Bits; 16209 16210 16211 UINT32 UInt32; 16212 16213 } u_sc_pcie2_sys_state0; 16214 16215 16216 typedef union 16217 { 16218 16219 struct 16220 { 16221 UINT32 pcie2_axi_parity_errs_reg : 4 ; 16222 UINT32 pcie2_app_parity_errs_reg : 3 ; 16223 UINT32 pcie2_pm_linkst_in_l1 : 1 ; 16224 UINT32 pcie2_pm_linkst_in_l2 : 1 ; 16225 UINT32 pcie2_pm_linkst_l2_exit : 1 ; 16226 UINT32 pcie2_mac_phy_power_down : 2 ; 16227 UINT32 pcie2_radm_correctabl_err_reg : 1 ; 16228 UINT32 pcie2_radm_nonfatal_err_reg : 1 ; 16229 UINT32 pcie2_radm_fatal_err_reg : 1 ; 16230 UINT32 pcie2_radm_pm_to_pme_reg : 1 ; 16231 UINT32 pcie2_radm_pm_to_ack_reg : 1 ; 16232 UINT32 pcie2_radm_cpl_timeout_reg : 1 ; 16233 UINT32 pcie2_radm_msg_unlock_reg : 1 ; 16234 UINT32 pcie2_cfg_pme_msi_reg : 1 ; 16235 UINT32 pcie2_bridge_flush_not_reg : 1 ; 16236 UINT32 pcie2_link_req_rst_not_reg : 1 ; 16237 UINT32 pcie2_cfg_aer_rc_err_msi : 1 ; 16238 UINT32 pcie2_cfg_sys_err_rc : 1 ; 16239 UINT32 pcie2_radm_msg_req_id_high : 8 ; 16240 } Bits; 16241 16242 16243 UINT32 UInt32; 16244 16245 } u_sc_pcie2_sys_state1; 16246 16247 16248 typedef union 16249 { 16250 16251 struct 16252 { 16253 UINT32 pcie2_ltssm_state : 6 ; 16254 UINT32 pcie2_mac_phy_rate : 2 ; 16255 UINT32 pcie2_slv_err_int : 1 ; 16256 UINT32 pcie2_retry_sram_addr : 10 ; 16257 UINT32 pcie2_mstr_rresp_int : 1 ; 16258 UINT32 pcie2_mstr_bresp_int : 1 ; 16259 UINT32 pcie2_radm_inta_reg : 1 ; 16260 UINT32 pcie2_radm_intb_reg : 1 ; 16261 UINT32 pcie2_radm_intc_reg : 1 ; 16262 UINT32 pcie2_radm_intd_reg : 1 ; 16263 UINT32 pcie2_cfg_pme_int_reg : 1 ; 16264 UINT32 pcie2_radm_vendor_msg_reg : 1 ; 16265 UINT32 pcie2_bridge_flush_not : 1 ; 16266 UINT32 pcie2_link_req_rst_not : 1 ; 16267 UINT32 reserved_0 : 3 ; 16268 } Bits; 16269 16270 16271 UINT32 UInt32; 16272 16273 } u_sc_pcie2_sys_state4; 16274 16275 16276 typedef union 16277 { 16278 16279 struct 16280 { 16281 UINT32 pcie2_curr_wr_latency : 16 ; 16282 UINT32 pcie2_curr_wr_port_sts : 1 ; 16283 UINT32 reserved_0 : 15 ; 16284 } Bits; 16285 16286 16287 UINT32 UInt32; 16288 16289 } u_sc_pcie2_axi_mstr_ooo_wr_sts1; 16290 16291 16292 typedef union 16293 { 16294 16295 struct 16296 { 16297 UINT32 pcie2_curr_rd_latency : 16 ; 16298 UINT32 pcie2_curr_rd_port_sts : 1 ; 16299 UINT32 reserved_0 : 15 ; 16300 } Bits; 16301 16302 16303 UINT32 UInt32; 16304 16305 } u_sc_pcie2_axi_mstr_ooo_rd_sts1; 16306 16307 16308 typedef union 16309 { 16310 16311 struct 16312 { 16313 UINT32 pcie2_rob_ecc_err_detect : 1 ; 16314 UINT32 pcie2_rob_ecc_err_multpl : 1 ; 16315 UINT32 reserved_0 : 30 ; 16316 } Bits; 16317 16318 16319 UINT32 UInt32; 16320 16321 } u_sc_pcie2_dsize_brg_ecc_err; 16322 16323 16324 typedef union 16325 { 16326 16327 struct 16328 { 16329 UINT32 pcie2_pciephy_ctrl_error : 1 ; 16330 UINT32 reserved_0 : 31 ; 16331 } Bits; 16332 16333 16334 UINT32 UInt32; 16335 16336 } u_sc_pcie2_pciephy_ctrl_error; 16337 16338 16339 typedef union 16340 { 16341 16342 struct 16343 { 16344 UINT32 pcie3_gm_cmposer_lookup_err : 1 ; 16345 UINT32 pcie3_radmx_cmposer_lookup_err : 1 ; 16346 UINT32 pcie3_pm_xtlh_block_tlp : 1 ; 16347 UINT32 pcie3_cfg_mem_space_en : 1 ; 16348 UINT32 pcie3_cfg_rcb : 1 ; 16349 UINT32 pcie3_rdlh_link_up : 1 ; 16350 UINT32 pcie3_pm_curnt_state : 3 ; 16351 UINT32 pcie3_cfg_aer_rc_err_int : 1 ; 16352 UINT32 pcie3_cfg_aer_int_msg_num : 5 ; 16353 UINT32 pcie3_xmlh_link_up : 1 ; 16354 UINT32 pcie3_wake : 1 ; 16355 UINT32 pcie3_cfg_eml_control : 1 ; 16356 UINT32 pcie3_hp_pme : 1 ; 16357 UINT32 pcie3_hp_int : 1 ; 16358 UINT32 pcie3_hp_msi : 1 ; 16359 UINT32 pcie3_pm_status : 1 ; 16360 UINT32 pcie3_ref_clk_req_n : 1 ; 16361 UINT32 pcie3_p2_exit_reg : 1 ; 16362 UINT32 pcie3_radm_msg_req_id_low : 8 ; 16363 } Bits; 16364 16365 16366 UINT32 UInt32; 16367 16368 } u_sc_pcie3_sys_state0; 16369 16370 16371 typedef union 16372 { 16373 16374 struct 16375 { 16376 UINT32 pcie3_axi_parity_errs_reg : 4 ; 16377 UINT32 pcie3_app_parity_errs_reg : 3 ; 16378 UINT32 pcie3_pm_linkst_in_l1 : 1 ; 16379 UINT32 pcie3_pm_linkst_in_l2 : 1 ; 16380 UINT32 pcie3_pm_linkst_l2_exit : 1 ; 16381 UINT32 pcie3_mac_phy_power_down : 2 ; 16382 UINT32 pcie3_radm_correctabl_err_reg : 1 ; 16383 UINT32 pcie3_radm_nonfatal_err_reg : 1 ; 16384 UINT32 pcie3_radm_fatal_err_reg : 1 ; 16385 UINT32 pcie3_radm_pm_to_pme_reg : 1 ; 16386 UINT32 pcie3_radm_pm_to_ack_reg : 1 ; 16387 UINT32 pcie3_radm_cpl_timeout_reg : 1 ; 16388 UINT32 pcie3_radm_msg_unlock_reg : 1 ; 16389 UINT32 pcie3_cfg_pme_msi_reg : 1 ; 16390 UINT32 pcie3_bridge_flush_not_reg : 1 ; 16391 UINT32 pcie3_link_req_rst_not_reg : 1 ; 16392 UINT32 pcie3_cfg_aer_rc_err_msi : 1 ; 16393 UINT32 pcie3_cfg_sys_err_rc : 1 ; 16394 UINT32 pcie3_radm_msg_req_id_high : 8 ; 16395 } Bits; 16396 16397 16398 UINT32 UInt32; 16399 16400 } u_sc_pcie3_sys_state1; 16401 16402 16403 typedef union 16404 { 16405 16406 struct 16407 { 16408 UINT32 pcie3_ltssm_state : 6 ; 16409 UINT32 pcie3_mac_phy_rate : 2 ; 16410 UINT32 pcie3_slv_err_int : 1 ; 16411 UINT32 pcie3_retry_sram_addr : 10 ; 16412 UINT32 pcie3_mstr_rresp_int : 1 ; 16413 UINT32 pcie3_mstr_bresp_int : 1 ; 16414 UINT32 pcie3_radm_inta_reg : 1 ; 16415 UINT32 pcie3_radm_intb_reg : 1 ; 16416 UINT32 pcie3_radm_intc_reg : 1 ; 16417 UINT32 pcie3_radm_intd_reg : 1 ; 16418 UINT32 pcie3_cfg_pme_int_reg : 1 ; 16419 UINT32 pcie3_radm_vendor_msg_reg : 1 ; 16420 UINT32 pcie3_bridge_flush_not : 1 ; 16421 UINT32 pcie3_link_req_rst_not : 1 ; 16422 UINT32 reserved_0 : 3 ; 16423 } Bits; 16424 16425 16426 UINT32 UInt32; 16427 16428 } u_sc_pcie3_sys_state4; 16429 16430 16431 typedef union 16432 { 16433 16434 struct 16435 { 16436 UINT32 pcie3_pciephy_ctrl_error : 1 ; 16437 UINT32 reserved_0 : 31 ; 16438 } Bits; 16439 16440 16441 UINT32 UInt32; 16442 16443 } u_sc_pcie3_pciephy_ctrl_error; 16444 16445 16446 typedef union 16447 { 16448 16449 struct 16450 { 16451 UINT32 skew_lock_a : 1 ; 16452 UINT32 reserved_0 : 31 ; 16453 } Bits; 16454 16455 16456 UINT32 UInt32; 16457 16458 } u_sc_skew_st_a_0; 16459 16460 16461 typedef union 16462 { 16463 16464 struct 16465 { 16466 UINT32 skew_varible_out_a : 16 ; 16467 UINT32 reserved_0 : 16 ; 16468 } Bits; 16469 16470 16471 UINT32 UInt32; 16472 16473 } u_sc_skew_st_a_1; 16474 16475 16476 typedef union 16477 { 16478 16479 struct 16480 { 16481 UINT32 skew_dcell_out_a_h : 4 ; 16482 UINT32 reserved_0 : 28 ; 16483 } Bits; 16484 16485 16486 UINT32 UInt32; 16487 16488 } u_sc_skew_st_a_3; 16489 16490 16491 typedef union 16492 { 16493 16494 struct 16495 { 16496 UINT32 skew_lock_b : 1 ; 16497 UINT32 reserved_0 : 31 ; 16498 } Bits; 16499 16500 16501 UINT32 UInt32; 16502 16503 } u_sc_skew_st_b_0; 16504 16505 16506 typedef union 16507 { 16508 16509 struct 16510 { 16511 UINT32 skew_varible_out_b : 16 ; 16512 UINT32 reserved_0 : 16 ; 16513 } Bits; 16514 16515 16516 UINT32 UInt32; 16517 16518 } u_sc_skew_st_b_1; 16519 16520 16521 typedef union 16522 { 16523 16524 struct 16525 { 16526 UINT32 skew_dcell_out_b_h : 4 ; 16527 UINT32 reserved_0 : 28 ; 16528 } Bits; 16529 16530 16531 UINT32 UInt32; 16532 16533 } u_sc_skew_st_b_3; 16534 16535 #endif 16536 16537 16538
