1 /** @file 2 * 3 * Copyright (c) 2016, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2016, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef __PCIE_INIT_H__ 17 #define __PCIE_INIT_H__ 18 19 #include "PcieInitLib.h" 20 #include <Library/DebugLib.h> 21 #include <Library/BaseLib.h> 22 #include <Library/UefiLib.h> 23 24 extern EFI_GUID gEfiPcieRootBridgeProtocolGuid; 25 26 #define PCIE_LOG_ID 1 27 28 #define PCIE_CONFIG_SPACE_SIZE 0x1000 //4k 29 #define PCIE_MEMORY_SPACE_SIZE 0x800000 //8M 30 #define PCIE_IO_SPACE_SIZE 0x800000 //8M 31 #define PCIE_TYPE1_MEM_SIZE (PCIE_MEMORY_SPACE_SIZE + PCIE_IO_SPACE_SIZE) 32 33 #define CONFIG_SPACE_BASE_ADDR_LOW 0xe2000000 34 #define CONFIG_SPACE_BASE_ADDR_HIGH 0x0 35 #define CONFIG_SPACE_ADDR_LIMIT (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE - 1) 36 37 #define PCIE_MEM_BASE_ADDR_LOW (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE) 38 #define PCIE_MEM_BASE_ADDR_HIGH 0x0 39 #define PCIE_MEM_ADDR_LIMIT (PCIE_MEM_BASE_ADDR_LOW + PCIE_MEMORY_SPACE_SIZE - PCIE_CONFIG_SPACE_SIZE - 1) 40 41 #define PCIE_IO_BASE_ADDR_LOW (PCIE_MEM_ADDR_LIMIT - 1) 42 #define PCIE_IO_BASE_ADDR_HIGH 0x0 43 #define PCIE_IO_ADDR_LIMIT (PCIE_IO_BASE_ADDR_LOW + PCIE_IO_SPACE_SIZE - 1) 44 45 #define PCIE_INBOUND_BASE 0xD0000000 46 47 48 #define PCIE_ALL_DMA_BASE (0x100000000) 49 #define PCIE0_ALL_DMA_BASE (PCIE_ALL_DMA_BASE) 50 #define PCIE0_ALL_DMA_SIZE (0x8000000) 51 #define PCIE0_ALL_BAR01_BASE (0x10000000) 52 #define PCIE0_ALL_BAR23_BASE (PCIE0_ALL_BAR01_BASE + PCIE_MAX_AXI_SIZE) 53 #define PCIE0_ALL_TRANSLATE01_BASE 0x2c0000000 //(HRD_ATTR_TRAN_ADDR_BASE_HOST_ADDR) 54 #define PCIE0_ALL_TRANSLATE01_SIZE (PCIE_MAX_AXI_SIZE) 55 #define PCIE0_ALL_TRANSLATE23_BASE (PCIE0_ALL_TRANSLATE01_BASE + PCIE0_ALL_TRANSLATE01_SIZE) 56 #define PCIE0_ALL_TRANSLATE23_SIZE (PCIE0_ALL_DMA_SIZE) 57 58 59 #define PCIE0_REG_BASE (0xb0070000) 60 #define PCIE1_REG_BASE (0xb0080000) 61 #define PCIE2_REG_BASE (0xb0090000) 62 #define PCIE3_REG_BASE (0xb00a0000) 63 64 #define PCIE_BASE_BAR (0xf0000000) 65 #define PCIE_BAR_SIZE (0x1000000) 66 67 68 #define PCIE_AXI_SIZE (0x1000000) 69 #define PCIE0_AXI_BASE (0xb3000000) 70 #define PCIE1_AXI_BASE (PCIE0_AXI_BASE + PCIE_AXI_SIZE) 71 #define PCIE2_AXI_BASE (PCIE1_AXI_BASE + PCIE_AXI_SIZE) 72 #define PCIE3_AXI_BASE (PCIE2_AXI_BASE + PCIE_AXI_SIZE) 73 74 //#define PCIE_CONFIG_SPACE_SIZE (0x1000) 75 #define PCIE0_CONFIG_BASE (PCIE1_AXI_BASE - PCIE_CONFIG_SPACE_SIZE) 76 #define PCIE1_CONFIG_BASE (PCIE2_AXI_BASE - PCIE_CONFIG_SPACE_SIZE) 77 #define PCIE2_CONFIG_BASE (PCIE3_AXI_BASE - PCIE_CONFIG_SPACE_SIZE) 78 #define PCIE3_CONFIG_BASE (PCIE3_AXI_BASE + PCIE_AXI_SIZE - PCIE_CONFIG_SPACE_SIZE) 79 80 81 #define PCIE0_TRANSLATE_BASE (0x30000000) 82 #define PCIE1_TRANSLATE_BASE (PCIE0_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE) 83 #define PCIE2_TRANSLATE_BASE (PCIE1_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE) 84 #define PCIE3_TRANSLATE_BASE (PCIE2_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE) 85 86 #define PCIE0_BAR_BASE (PCIE0_AXI_BASE) 87 #define PCIE1_BAR_BASE (PCIE1_AXI_BASE) 88 #define PCIE2_BAR_BASE (PCIE2_AXI_BASE) 89 #define PCIE3_BAR_BASE (PCIE3_AXI_BASE) 90 91 92 #endif 93 94
