1 /******************************************************************************* 2 Copyright (C) 2016 Marvell International Ltd. 3 4 Marvell BSD License Option 5 6 If you received this File from Marvell, you may opt to use, redistribute and/or 7 modify this File under the following licensing terms. 8 Redistribution and use in source and binary forms, with or without modification, 9 are permitted provided that the following conditions are met: 10 11 * Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 * Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 * Neither the name of Marvell nor the names of its contributors may be 19 used to endorse or promote products derived from this software without 20 specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 23 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 26 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 33 *******************************************************************************/ 34 35 #include "SdMmcPciHcDxe.h" 36 37 #include <Library/IoLib.h> 38 39 #define SD_BAR_INDEX 0 40 41 #define SIZE_512B 0x200 42 43 /* Register Offset of SD Host Controller SOCP self-defined register */ 44 45 #define SDHC_IPID 0x0100 46 #define SDHC_SYS_CFG_INFO 0x0104 47 #define SLOT_TYPE_SDIO_SHIFT 24 48 #define SLOT_TYPE_EMMC_MASK 0xff 49 #define SLOT_TYPE_EMMC_SHIFT 16 50 #define SLOT_TYPE_SD_SDIO_MMC_MASK 0xff 51 #define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8 52 53 #define SDHC_SYS_OP_CTRL 0x0108 54 #define AUTO_CLKGATE_DISABLE_MASK (0x1<<20) 55 #define SDCLK_IDLEOFF_ENABLE_SHIFT 8 56 #define SLOT_ENABLE_SHIFT 0 57 58 #define SDHC_SYS_EXT_OP_CTRL 0x010c 59 #define SDHC_TEST_OUT 0x0110 60 #define SDHC_TESTOUT_MUXSEL 0x0114 61 62 #define SDHC_SLOT_EXT_INT_STATUS 0x0120 63 #define SDHC_SLOT_EXT_ERR_STATUS 0x0122 64 #define SDHC_SLOT_EXT_INT_STATUS_EN 0x0124 65 #define SDHC_SLOT_EXT_ERR_STATUS_EN 0x0126 66 67 #define SDHC_SLOT_OP_STATUS_CTRL 0x0128 68 #define TUNING_PROG_FIXED_DELAY_MASK 0x7ff 69 #define FORCE_SEL_INVERSE_CLK_SHIFT 11 70 71 #define SDHC_SLOT_FIFO_CTRL 0x012c 72 #define SDHC_SLOT_FIFO_DEFAULT_CONFIG 0x315 73 74 #define SDHC_SLOT_eMMC_CTRL 0x0130 75 #define ENABLE_DATA_STROBE_SHIFT 24 76 #define SET_EMMC_RSTN_SHIFT 16 77 #define eMMC_VCCQ_MASK 0x3 78 #define eMMC_VCCQ_1_8V 0x1 79 #define eMMC_VCCQ_1_2V 0x2 80 #define eMMC_VCCQ_3_3V 0x3 81 82 #define SDHC_SLOT_OUTPUT_DLY_CTRL 0x0134 83 #define SDHC_SLOT_DCM_CTRL 0x0137 84 85 #define SDHC_SLOT_DLL_CTRL 0x0138 86 #define SELECT_DEF_DLL 0x1 87 88 #define SDHC_SLOT_DLL_PHASE_SEL 0x013c 89 #define DLL_UPDATE_STROBE 7 90 91 #define SDHC_SLOT_STROBE_DLY_CTRL 0x0140 92 #define STROBE_DELAY_FIXED_MASK 0xffff 93 94 #define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144 95 #define RETUNING_COMPATIBLE 0x1 96 97 #define SDHC_SLOT_AUTO_RETUNING_CTRL 0x0148 98 #define ENABLE_AUTO_RETUNING 0x1 99 100 #define SDHC_SLOT_EXT_PRESENT_STATE 0x014c 101 #define SDHC_SLOT_DLL_CUR_DLY_VAL 0x0150 102 #define SDHC_SLOT_TUNING_CUR_DLY_VAL 0x0154 103 #define SDHC_SLOT_STROBE_CUR_DLY_VAL 0x0158 104 #define SDHC_SLOT_SUB_CMD_STRL 0x015c 105 106 #define SDHC_SLOT_CQ_TASK_INFO 0x0160 107 108 #define SDHC_SLOT_TUNING_DEBUG_INFO 0x01f0 109 #define SDHC_SLOT_DATAIN_DEBUG_INFO 0x01f4 110 111 #define SDHC_CMD_RESET_BIT (1 << 1) 112 #define SDHC_DATA_RESET_BIT (1 << 2) 113 114 #define SDHC_CMD_INHIBIT (1 << 0) 115 #define SDHC_DATA_INHIBIT (1 << 1) 116 117 #define SDHC_REG_SIZE_1B 1 118 #define SDHC_REG_SIZE_2B 2 119 #define SDHC_REG_SIZE_4B 4 120 121 #define SDHC_DAT_BUF_PORT_ADDR 0xF06E0020 122 123 /* Command register bits description */ 124 #define RESP_TYPE_136_BITS (1 << 0) 125 #define RESP_TYPE_48_BITS (1 << 1) 126 #define RESP_TYPE_48_BITS_NO_CRC ((1 << 0) | (1 << 1)) 127 #define CMD_CRC_CHK_EN (1 << 3) 128 #define CMD_INDEX_CHK_EN (1 << 4) 129 #define DATA_PRESENT (1 << 5) 130 131 /* Transfer mode register bits description */ 132 #define SDHC_TRNS_BLK_CNT_EN (1 << 1) 133 #define SDHC_TRNS_MULTI_BLK_SEL (1 << 5) 134 #define SDHC_TRNS_TO_HOST_DIR (1 << 4) 135 136 /* Block size register bits description */ 137 #define BLK_SIZE_HOST_DMA_BDRY_OFFSET 12 138 #define BLK_SIZE_512KB 0x7 139 140 /* Int status register bits description */ 141 #define NOR_INT_STS_CMD_COMPLETE (1 << 0) 142 #define NOR_INT_STS_XFER_COMPLETE (1 << 1) 143 #define NOR_INT_STS_TX_RDY (1 << 4) 144 #define NOR_INT_STS_RX_RDY (1 << 5) 145 #define NOR_INT_STS_CARD_INS (1 << 6) 146 #define NOR_INT_STS_CARD_INT (1 << 8) 147 #define NOR_INT_STS_ERR_INT (1 << 15) 148 #define ERR_INT_STS_CMD_TIMEOUT_ERR (1 << 16) 149 #define ERR_INT_STS_DATA_TIMEOUT_ERR (1 << 20) 150 151 #define NOR_INT_SIG_EN_CARD_INT (1 << 8) 152 153 #define PRESENT_STATE_BUFFER_RD_EN (1 << 11) 154 #define PRESENT_STATE_BUFFER_WR_EN (1 << 10) 155 156 #define SDHC_CLR_IRQ_STS_MASK 0xFFFF 157 #define SDHC_CLR_ALL_IRQ_MASK 0xFFFFFFFFUL 158 159 /* Max clock in Hz */ 160 #define XENON_MMC_MAX_CLK 400000000 161 #define XENON_MMC_CLK_RATIO 2046 162 #define XENON_MMC_BASE_CLK XENON_MMC_MAX_CLK / XENON_MMC_CLK_RATIO 163 #define XENON_MMC_MIN_CLK 100000 164 165 #define XENON_MMC_CMD_MAX_TIMEOUT 3200 166 #define XENON_MMC_CMD_DEFAULT_TIMEOUT 100 167 168 /* Tuning Parameter */ 169 #define TMR_RETUN_NO_PRESENT 0xf 170 #define XENON_MAX_TUN_COUNT 0xb 171 172 #define EMMC_PHY_REG_BASE 0x170 173 #define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE 174 #define OUTPUT_QSN_PHASE_SELECT (1 << 17) 175 #define SAMPL_INV_QSP_PHASE_SELECT (1 << 18) 176 #define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 177 #define PHY_INITIALIZAION (1 << 31) 178 #define WAIT_CYCLE_BEFORE_USING_MASK 0xf 179 #define WAIT_CYCLE_BEFORE_USING_SHIFT 12 180 #define FC_SYNC_EN_DURATION_MASK 0xf 181 #define FC_SYNC_EN_DURATION_SHIFT 8 182 #define FC_SYNC_RST_EN_DURATION_MASK 0xf 183 #define FC_SYNC_RST_EN_DURATION_SHIFT 4 184 #define FC_SYNC_RST_DURATION_MASK 0xf 185 #define FC_SYNC_RST_DURATION_SHIFT 0 186 187 #define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4) 188 #define DQ_ASYNC_MODE (1 << 4) 189 #define DQ_DDR_MODE_SHIFT 8 190 #define DQ_DDR_MODE_MASK 0xff 191 #define CMD_DDR_MODE (1 << 16) 192 193 #define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8) 194 #define REC_EN_SHIFT 24 195 #define REC_EN_MASK 0xf 196 #define FC_DQ_RECEN (1 << 24) 197 #define FC_CMD_RECEN (1 << 25) 198 #define FC_QSP_RECEN (1 << 26) 199 #define FC_QSN_RECEN (1 << 27) 200 #define OEN_QSN (1 << 28) 201 #define AUTO_RECEN_CTRL (1 << 30) 202 203 #define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc) 204 #define EMMC_PHY_PAD_CONTROL2 (EMMC_PHY_REG_BASE + 0x10) 205 #define EMMC_PHY_DLL_CONTROL (EMMC_PHY_REG_BASE + 0x14) 206 #define DLL_DELAY_TEST_LOWER_SHIFT 8 207 #define DLL_DELAY_TEST_LOWER_MASK 0xff 208 #define DLL_BYPASS_EN 0x1 209 210 #define EMMC_LOGIC_TIMING_ADJUST (EMMC_PHY_REG_BASE + 0x18) 211 #define EMMC_LOGIC_TIMING_ADJUST_LOW (EMMC_PHY_REG_BASE + 0x1c) 212 213 #define LOGIC_TIMING_VALUE 0x5a54 /* Recommend by HW team */ 214 215 #define QSN_PHASE_SLOW_MODE_BIT (1 << 29) 216 217 /* XENON only have one slot 0 */ 218 #define XENON_MMC_SLOT_ID (0) 219 220 #define MMC_TIMING_LEGACY 0 221 #define MMC_TIMING_MMC_HS 1 222 #define MMC_TIMING_SD_HS 2 223 #define MMC_TIMING_UHS_SDR12 3 224 #define MMC_TIMING_UHS_SDR25 4 225 #define MMC_TIMING_UHS_SDR50 5 226 #define MMC_TIMING_UHS_SDR104 6 227 #define MMC_TIMING_UHS_DDR50 7 228 #define MMC_TIMING_MMC_HS200 8 229 #define MMC_TIMING_MMC_HS400 10 230 231 /* Data time out default value 0xE: TMCLK x 227 */ 232 #define DATA_TIMEOUT_DEF_VAL 0xE 233 234 /* Max retry count for INT status ready */ 235 #define SDHC_INT_STATUS_POLL_RETRY 1000 236 #define SDHC_INT_STATUS_POLL_RETRY_DATA_TRAN 100000 237 238 /* Take 2.5 seconds as generic time out value, 1 microsecond as unit */ 239 #define SD_GENERIC_TIMEOUT 2500 * 1000 240 241 /* SDMA start address should allign with 0x8, align mask 0x7 */ 242 #define DMA_START_ADDR_ALIGN_MASK 0x7 243 244 #define SDHCI_RETUNE_EVT_INTSIG 0x00001000 245 246 /* MMC modes */ 247 #define XENON_MMC_MODE_EMMC 0 248 #define XENON_MMC_MODE_SD_SDIO 1 249 250 /* MMC Voltage */ 251 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 252 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 253 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 254 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 255 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 256 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 257 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 258 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 259 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 260 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 261 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 262 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 263 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 264 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 265 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 266 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 267 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 268 269 /* SDHCI FLAGS */ 270 #define SDHCI_POWER_ON 0x01 271 #define SDHCI_POWER_180 0x0A 272 #define SDHCI_POWER_300 0x0C 273 #define SDHCI_POWER_330 0x0E 274 275 #define SDHCI_DIVIDER_SHIFT 8 276 #define SDHCI_DIVIDER_HI_SHIFT 6 277 #define SDHCI_DIV_MASK 0xFF 278 #define SDHCI_DIV_MASK_LEN 8 279 #define SDHCI_DIV_HI_MASK 0x300 280 #define SDHCI_CLOCK_CARD_EN 0x0004 281 #define SDHCI_CLOCK_INT_STABLE 0x0002 282 #define SDHCI_CLOCK_INT_EN 0x0001 283 284 #define SDHCI_VENDOR_VER_MASK 0xFF00 285 #define SDHCI_VENDOR_VER_SHIFT 8 286 #define SDHCI_SPEC_VER_MASK 0x00FF 287 #define SDHCI_SPEC_VER_SHIFT 0 288 #define SDHCI_SPEC_100 0 289 #define SDHCI_SPEC_200 1 290 #define SDHCI_SPEC_300 2 291 292 #define SDHCI_SIGNAL_ENABLE 0x38 293 294 #define SDHCI_MAX_DIV_SPEC_200 256 295 #define SDHCI_MAX_DIV_SPEC_300 2046 296 297 /* SD DEVICE STATUS FLAGS */ 298 #define CURRENT_STATE_MASK (0xF << 9) 299 #define CURRENT_STATE_N_READY_MASK (7 << 9) 300 #define READY_FOR_DATA (1 << 8) 301 #define CARD_STATUS_ERROR_MASK (~0x0206BF7F) 302 303 #define RCA_BITS_OFFSET 16 304 305 UINTN 306 XenonSetClk ( 307 IN EFI_PCI_IO_PROTOCOL *PciIo, 308 IN SD_MMC_HC_PRIVATE_DATA *Private, 309 IN UINT32 Clock 310 ); 311 312 VOID 313 XenonPhyInit ( 314 IN EFI_PCI_IO_PROTOCOL *PciIo 315 ); 316 317 VOID 318 XenonReset ( 319 IN SD_MMC_HC_PRIVATE_DATA *Private, 320 IN UINT8 Slot, 321 IN UINT8 Mask 322 ); 323 324 EFI_STATUS 325 XenonTransferData ( 326 IN SD_MMC_HC_PRIVATE_DATA *Private, 327 IN UINT8 Slot, 328 IN OUT VOID *Buffer, 329 IN UINT32 DataLen, 330 IN UINT16 BlockSize, 331 IN UINT16 Blocks, 332 IN BOOLEAN Read 333 ); 334 335 EFI_STATUS 336 XenonInit ( 337 IN SD_MMC_HC_PRIVATE_DATA *Private 338 ); 339 340 EFI_STATUS 341 SdCardSendStatus ( 342 IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, 343 IN UINT8 Slot, 344 IN UINT16 Rca, 345 OUT UINT32 *DevStatus 346 ); 347
