1 /** @file 2 3 Copyright (c) 2017, Linaro Limited. All rights reserved. 4 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 #ifndef __DW_USB3_DXE_H__ 16 #define __DW_USB3_DXE_H__ 17 18 #define DW_USB3_BASE FixedPcdGet32 (PcdDwUsb3DxeBaseAddress) 19 20 #define GSBUCFG0 (DW_USB3_BASE + 0xC100) 21 #define GCTL (DW_USB3_BASE + 0xC110) 22 23 #define GCTL_PWRDNSCALE_MASK (0x1FFF << 19) 24 #define GCTL_PWRDNSCALE(x) (((x) & 0x1FFF) << 19) 25 #define GCTL_U2RSTECN BIT16 26 #define GCTL_PRTCAPDIR_MASK (BIT13 | BIT12) 27 #define GCTL_PRTCAPDIR_HOST BIT12 28 #define GCTL_PRTCAPDIR_DEVICE BIT13 29 #define GCTL_PRTCAPDIR_OTG (BIT13 | BIT12) 30 #define GCTL_U2EXIT_LFPS BIT2 31 32 #define GUSB2PHYCFG(x) (DW_USB3_BASE + 0xC200 + (((x) & 0xF) << 2)) 33 34 #define GUSB2PHYCFG_USBTRDTIM_MASK (0xF << 10) 35 #define GUSB2PHYCFG_USBTRDTIM(x) (((x) & 0xF) << 10) 36 #define GUSB2PHYCFG_SUSPHY BIT6 37 38 #define GUSB3PIPECTL(x) (DW_USB3_BASE + 0xC2C0 + (((x) & 0x3) << 2)) 39 40 #define PIPECTL_DELAYP1TRANS BIT18 41 #define PIPECTL_SUSPEND_EN BIT17 42 #define PIPECTL_LFPS_FILTER BIT9 43 #define PIPECTL_TX_DEMPH_MASK (0x3 << 1) 44 #define PIPECTL_TX_DEMPH(x) (((x) & 0x3) << 1) 45 46 #define GTXFIFOSIZ(x) (DW_USB3_BASE + 0xC300 + (((x) & 0x1F) << 2)) 47 #define GRXFIFOSIZ(x) (DW_USB3_BASE + 0xC380 + (((x) & 0x1F) << 2)) 48 49 #define FIFOSIZ_ADDR(x) (((x) & 0xFFFF) << 16) 50 #define FIFOSIZ_DEP(x) ((x) & 0xFFFF) 51 52 #define GEVNTADRL(x) (DW_USB3_BASE + 0xC400 + (((x) & 0x1F) << 2)) 53 #define GEVNTADRH(x) (DW_USB3_BASE + 0xC404 + (((x) & 0x1F) << 2)) 54 #define GEVNTSIZ(x) (DW_USB3_BASE + 0xC408 + (((x) & 0x1F) << 2)) 55 56 #define GEVNTSIZ_EVNTINTMASK BIT31 57 #define GEVNTSIZ_EVNTSIZ_MASK (0xFFFF) 58 #define GEVNTSIZ_EVNTSIZ(x) ((x) & 0xFFFF) 59 60 #define GEVNTCOUNT(x) (DW_USB3_BASE + 0xC40C + (((x) & 0x1F) << 2)) 61 #define GEVNTCOUNT_EVNTCOUNT_MASK (0xFFFF) 62 #define GEVNTCOUNT_EVNTCOUNT(x) ((x) & 0xFFFF) 63 64 // Non-Endpoint specific event flag 65 #define GEVNT_INTTYPE_MASK (0x7F << 1) 66 #define GEVNT_INTTYPE(x) (((x) & 0x7F) << 1) 67 #define EVENT_I2C_INT 4 68 #define EVENT_CARKIT_INT 3 69 #define EVENT_OTG_INT 1 70 #define EVENT_DEV_INT 0 71 72 #define GEVNT_NON_EP BIT0 73 // Endpoint specific event flag 74 #define GEVNT_DEPEVT_INTTYPE_MASK (0xF << 6) 75 #define GEVNT_DEPEVT_INTTYPE(x) (((x) & 0xF) << 6) 76 #define GEVNT_DEPEVT_INTTYPE_EPCMD_CMPL (7 << 6) 77 #define GEVNT_DEPEVT_INTTYPE_STRM_EVT (6 << 6) 78 #define GEVNT_DEPEVT_INTTYPE_FIFOXRUN (4 << 6) 79 #define GEVNT_DEPEVT_INTTYPE_XFER_NRDY (3 << 6) 80 #define GEVNT_DEPEVT_INTTYPE_XFER_IN_PROG (2 << 6) 81 #define GEVNT_DEPEVT_INTTYPE_XFER_CMPL (1 << 6) 82 #define GEVNT_DEPEVT_EPNUM_MASK (0x1F << 1) 83 #define GEVNT_DEPEVT_EPNUM_SHIFT 1 84 #define GEVNT_DEPEVT_EPNUM(x) (((x) & 0x1F) << 1) 85 // Devices specific event flag 86 #define GEVNT_DEVT_MASK (0xF << 8) 87 #define GEVNT_DEVT_SHIFT 8 88 #define GEVNT_DEVT(x) (((x) & 0xF) << 8) 89 #define GEVNT_DEVT_INACT_TIMEOUT_RCVD (0x15 << 8) 90 #define GEVNT_DEVT_VNDR_DEV_TST_RCVD (0x14 << 8) 91 #define GEVNT_DEVT_OVERFLOW (0x13 << 8) 92 #define GEVNT_DEVT_CMD_CMPL (0x12 << 8) 93 #define GEVNT_DEVT_ERRATICERR (0x11 << 8) 94 #define GEVNT_DEVT_SOF (0x7 << 8) 95 #define GEVNT_DEVT_EOPF (0x6 << 8) 96 #define GEVNT_DEVT_HIBER_REQ (0x5 << 8) 97 #define GEVNT_DEVT_WKUP (0x4 << 8) 98 #define GEVNT_DEVT_ULST_CHNG (0x3 << 8) 99 #define GEVNT_DEVT_CONNDONE (0x2 << 8) 100 #define GEVNT_DEVT_USBRESET (0x1 << 8) 101 #define GEVNT_DEVT_DISCONN (0x0 << 8) 102 103 #define DCFG (DW_USB3_BASE + 0xC700) 104 105 #define DCFG_NUMP_MASK (0x1F << 17) 106 #define DCFG_NUMP(x) (((x) & 0x1F) << 17) 107 #define DCFG_DEVADDR_MASK (0x7F << 3) 108 #define DCFG_DEVADDR(x) (((x) & 0x7F) << 3) 109 #define DCFG_DEVSPD_MASK (0x7) 110 #define DCFG_DEVSPD(x) ((x) & 0x7) 111 #define DEVSPD_HS_PHY_30MHZ_OR_60MHZ 0 112 #define DEVSPD_FS_PHY_30MHZ_OR_60MHZ 1 113 #define DEVSPD_LS_PHY_6MHZ 2 114 #define DEVSPD_FS_PHY_48MHZ 3 115 #define DEVSPD_SS_PHY_125MHZ_OR_250MHZ 4 116 117 #define DCTL (DW_USB3_BASE + 0xC704) 118 119 #define DCTL_RUN_STOP BIT31 120 #define DCTL_CSFTRST BIT30 121 #define DCTL_INIT_U2_EN BIT12 122 #define DCTL_ACCEPT_U2_EN BIT11 123 #define DCTL_INIT_U1_EN BIT10 124 #define DCTL_ACCEPT_U1_EN BIT9 125 126 #define DEVTEN (DW_USB3_BASE + 0xC708) 127 #define DEVTEN_CONNECTDONEEN BIT2 128 #define DEVTEN_USBRSTEN BIT1 129 #define DEVTEN_DISCONNEN BIT0 130 131 #define DSTS (DW_USB3_BASE + 0xC70C) 132 #define DSTS_GET_DEVSPD(x) ((x) & 0x7) 133 134 #define DALEPENA (DW_USB3_BASE + 0xC720) 135 136 #define DEPCMDPAR2(x) (DW_USB3_BASE + 0xC800 + ((x) & 0x1F) * 0x10) 137 #define DEPCMDPAR1(x) (DW_USB3_BASE + 0xC804 + ((x) & 0x1F) * 0x10) 138 #define DEPCMDPAR0(x) (DW_USB3_BASE + 0xC808 + ((x) & 0x1F) * 0x10) 139 #define DEPCMD(x) (DW_USB3_BASE + 0xc80C + ((x) & 0x1F) * 0x10) 140 141 #define DEPCMD_COMMANDPARAM_MASK (0xFFFF << 16) 142 #define DEPCMD_COMMANDPARAM(x) (((x) & 0xFFFF) << 16) 143 /* Stream Number or uFrame (input) */ 144 #define DEPCMD_STR_NUM_OR_UF_MASK (0xFFFF << 16) 145 #define DEPCMD_STR_NUM_OR_UF(x) (((x) & 0xFFFF) << 16) 146 /* Transfer Resource Index (output) */ 147 #define DEPCMD_XFER_RSRC_IDX_SHIFT 16 148 #define DEPCMD_XFER_RSRC_IDX_MASK (0x7F << 16) 149 #define DEPCMD_XFER_RSRC_IDX(x) (((x) & 0x7F) << 16) 150 #define GET_DEPCMD_XFER_RSRC_IDX(x) (((x) >> 16) & 0x7F) 151 #define DEPCMD_CMDACT BIT10 152 #define DEPCMD_CMDTYPE_MASK 0xFF 153 #define DEPCMD_CMDTYPE(x) ((x) & 0xFF) 154 155 /* EP registers range as: OUT0, IN0, OUT1, IN1, ... */ 156 #define EP_OUT_IDX(x) ((x) * 2) 157 #define EP_IN_IDX(x) (((x) * 2) + 1) 158 159 #define CMDTYPE_SET_EP_CFG 1 160 #define CMDTYPE_SET_XFER_CFG 2 161 #define CMDTYPE_GET_EP_STATE 3 162 #define CMDTYPE_SET_STALL 4 163 #define CMDTYPE_CLR_STALL 5 164 #define CMDTYPE_START_XFER 6 165 #define CMDTYPE_UPDATE_XFER 7 166 #define CMDTYPE_END_XFER 8 167 #define CMDTYPE_START_NEW_CFG 9 168 169 #define EPTYPE_CONTROL 0 170 #define EPTYPE_ISOC 1 171 #define EPTYPE_BULK 2 172 #define EPTYPE_INTR 3 173 174 #define CFG_ACTION_INIT 0 175 #define CFG_ACTION_RESTORE 1 176 #define CFG_ACTION_MODIFY 2 177 178 #define EPCFG0_CFG_ACTION_MASK (0x3 << 30) 179 #define EPCFG0_CFG_ACTION(x) (((x) & 0x3) << 30) 180 #define EPCFG0_BRSTSIZ_MASK (0xF << 22) 181 #define EPCFG0_BRSTSIZ(x) (((x) & 0xF) << 22) 182 #define EPCFG0_TXFNUM_MASK (0x1F << 17) 183 #define EPCFG0_TXFNUM(x) (((x) & 0x1F) << 17) 184 #define EPCFG0_MPS_MASK (0x7FF << 3) 185 #define EPCFG0_MPS(x) (((x) & 0x7FF) << 3) 186 #define EPCFG0_EPTYPE_MASK (0x3 << 1) 187 #define EPCFG0_EPTYPE_SHIFT 1 188 #define EPCFG0_EPTYPE(x) (((x) & 0x3) << 1) 189 190 /* Endpoint Number */ 191 #define EPCFG1_EP_NUM_MASK (0xF << 26) 192 #define EPCFG1_EP_NUM(x) (((x) & 0xF) << 26) 193 /* Endpoint Direction */ 194 #define EPCFG1_EP_DIR_IN BIT25 195 /* Stream Not Ready */ 196 #define EPCFG1_XFER_NRDY BIT10 197 /* XferInProgress Enable */ 198 #define EPCFG1_XFER_IN_PROG BIT9 199 /* Stream Completed */ 200 #define EPCFG1_XFER_CMPL BIT8 201 202 #define USB_SPEED_UNKNOWN 0 203 #define USB_SPEED_LOW 1 204 #define USB_SPEED_FULL 2 205 #define USB_SPEED_HIGH 3 206 #define USB_SPEED_VARIABLE 4 207 #define USB_SPEED_SUPER 5 208 209 // DMA registers 210 #define DSCSTS_TRBRSP_MASK (0xF << 28) 211 #define DSCSTS_TRBRSP(x) (((x) & 0xF) << 28) 212 #define GET_DSCSTS_TRBRSP(x) (((x) >> 28) & 0xF) 213 #define TRBRSP_MISSED_ISOC_IN 1 214 #define TRBRSP_SETUP_PEND 2 215 #define TRBRSP_XFER_IN_PROG 4 216 #define DSCSTS_PCM1_MASK (0x3 << 24) 217 #define DSCSTS_PCM1(x) (((x) & 0x3) << 24) 218 #define DSCSTS_XFERCNT_MASK 0xFFFFFF 219 #define DSCSTS_XFERCNT(x) ((x) & 0xFFFFFF) 220 #define GET_DSCSTS_XFERCNT(x) ((x) & 0xFFFFFF) 221 222 #define DSCCTL_STRMID_SOFN(x) (((x) & 0xFFFF) << 14) 223 #define DSCCTL_IOC BIT11 224 #define DSCCTL_ISP BIT10 225 #define DSCCTL_TRBCTL_MASK (0x3F << 4) 226 #define DSCCTL_TRBCTL(x) (((x) & 0x3F) << 4) 227 #define DSCCTL_LST BIT1 228 #define DSCCTL_HWO BIT0 229 #define TRBCTL_NORMAL 1 230 #define TRBCTL_SETUP 2 231 #define TRBCTL_STATUS_2 3 232 #define TRBCTL_STATUS_3 4 233 #define TRBCTL_CTLDATA_1ST 5 234 #define TRBCTL_ISOC_1ST 6 235 #define TRBCTL_ISOC 7 236 #define TRBCTL_LINK 8 237 #define TRBCTL_NORMAL_ZLP 9 238 239 240 #define UE_DIR_IN 0x80 241 #define UE_DIR_OUT 0 242 #define UE_SET_DIR(a, d) ((a) | (((d) & 1) << 7)) 243 #define UE_GET_DIR(a) ((a) & 0x80) 244 #define UE_ADDR 0x0F 245 #define UE_GET_ADDR(a) ((a) & UE_ADDR) 246 247 #define UT_GET_DIR(a) ((a) & 0x80) 248 #define UT_WRITE 0x00 249 #define UT_READ 0x80 250 251 #define UT_GET_TYPE(a) ((a) & 0x60) 252 #define UT_STANDARD 0x00 253 #define UT_CLASS 0x20 254 #define UT_VENDOR 0x40 255 256 #define UT_GET_RECIPIENT(a) ((a) & 0x1f) 257 #define UT_DEVICE 0x00 258 #define UT_INTERFACE 0x01 259 #define UT_ENDPOINT 0x02 260 #define UT_OTHER 0x03 261 262 #define UR_GET_STATUS 0x00 263 #define UR_CLEAR_FEATURE 0x01 264 #define UR_SET_FEATURE 0x03 265 #define UR_SET_ADDRESS 0x05 266 #define UR_GET_DESCRIPTOR 0x06 267 #define UR_SET_DESCRIPTOR 0x07 268 #define UR_GET_CONFIG 0x08 269 #define UR_SET_CONFIG 0x09 270 #define UR_GET_INTERFACE 0x0A 271 #define UR_SET_INTERFACE 0x0B 272 #define UR_SYNCH_FRAME 0x0C 273 #define UR_SET_SEL 0x30 274 #define UR_SET_ISOC_DELAY 0x31 275 276 /* Feature numbers */ 277 #define UF_ENDPOINT_HALT 0 278 #define UF_DEVICE_REMOTE_WAKEUP 1 279 #define UF_TEST_MODE 2 280 #define UF_DEVICE_B_HNP_ENABLE 3 281 #define UF_DEVICE_A_HNP_SUPPORT 4 282 #define UF_DEVICE_A_ALT_HNP_SUPPORT 5 283 #define UF_FUNCTION_SUSPEND 0 284 #define UF_U1_ENABLE 48 285 #define UF_U2_ENABLE 49 286 #define UF_LTM_ENABLE 50 287 288 #define UDESC_DEVICE 0x01 289 #define UDESC_CONFIG 0x02 290 #define UDESC_STRING 0x03 291 #define UDESC_INTERFACE 0x04 292 #define UDESC_ENDPOINT 0x05 293 #define UDESC_SS_USB_COMPANION 0x30 294 #define UDESC_DEVICE_QUALIFIER 0x06 295 #define UDESC_BOS 0x0f 296 #define UDESC_DEVICE_CAPABILITY 0x10 297 298 #define STRING_LANGUAGE 0 299 #define STRING_MANUFACTURER 1 300 #define STRING_PRODUCT 2 301 #define STRING_SERIAL 3 302 303 #define CONFIG_VALUE 1 304 305 #define USB3_BULK_IN_EP 1 306 #define USB3_BULK_OUT_EP 1 307 308 #define USB_ENUM_ADB_PORT_VID 0x18D1 309 #define USB_ENUM_ADB_PORT_PID 0xD00D 310 #define USB_ENUM_INTERFACE_ADB_SUBCLASS 0x42 311 #define USB_ENUM_INTERFACE_ADB_PROTOCOL 0x03 312 313 struct usb3_pcd; 314 315 typedef enum pcd_state { 316 USB3_STATE_UNCONNECTED, /* no host */ 317 USB3_STATE_DEFAULT, 318 USB3_STATE_ADDRESSED, 319 USB3_STATE_CONFIGURED, 320 } pcdstate_e; 321 322 typedef enum ep0_state { 323 EP0_IDLE, 324 EP0_IN_DATA_PHASE, 325 EP0_OUT_DATA_PHASE, 326 EP0_IN_WAIT_NRDY, 327 EP0_OUT_WAIT_NRDY, 328 EP0_IN_STATUS_PHASE, 329 EP0_OUT_STATUS_PHASE, 330 EP0_STALL, 331 } ep0state_e; 332 333 typedef struct usb3_dma_desc { 334 /** Buffer Pointer - Low address quadlet */ 335 UINT32 bptl; 336 337 /** Buffer Pointer - High address quadlet */ 338 UINT32 bpth; 339 340 /** Status quadlet. Fields defined in enum @ref desc_sts_data. */ 341 UINT32 status; 342 343 /** Control quadlet. Fields defined in enum @ref desc_ctl_data. */ 344 UINT32 control; 345 } usb3_dma_desc_t; 346 347 typedef struct usb3_pcd_req { 348 usb3_dma_desc_t *trb; 349 UINT64 trbdma; 350 351 UINT32 length; 352 UINT32 actual; 353 354 UINT64 *bufdma; 355 int (*complete)(unsigned actual, int status); 356 } usb3_pcd_req_t; 357 358 typedef struct usb_device_request { 359 UINT8 bmRequestType; 360 UINT8 bRequest; 361 UINT16 wValue; 362 UINT16 wIndex; 363 UINT16 wLength; 364 } usb_device_request_t; 365 366 #pragma pack(1) 367 /** USB_DT_DEVICE: Device descriptor */ 368 typedef struct usb_device_descriptor { 369 UINT8 bLength; 370 UINT8 bDescriptorType; 371 372 UINT16 bcdUSB; 373 #define USB_CLASS_COMM 0x02 374 #define USB_CLASS_VENDOR_SPEC 0xFF 375 #define USB_SC_VENDOR_SPEC 0xFF 376 #define USB_PR_VENDOR_SPEC 0xFF 377 UINT8 bDeviceClass; 378 UINT8 bDeviceSubClass; 379 UINT8 bDeviceProtocol; 380 UINT8 bMaxPacketSize0; 381 UINT16 idVendor; 382 UINT16 idProduct; 383 UINT16 bcdDevice; 384 UINT8 iManufacturer; 385 UINT8 iProduct; 386 UINT8 iSerialNumber; 387 UINT8 bNumConfigurations; 388 } usb_device_descriptor_t; 389 390 /* USB_DT_CONFIG: Config descriptor */ 391 typedef struct usb_config_descriptor { 392 UINT8 bLength; 393 UINT8 bDescriptorType; 394 395 UINT16 wTotalLength; 396 UINT8 bNumInterfaces; 397 #define CONFIG_VALUE 1 398 UINT8 bConfigurationValue; 399 UINT8 iConfiguration; 400 #define USB_CONFIG_ATT_ONE (1 << 7) 401 UINT8 bmAttributes; 402 #define USB_CONFIG_VBUS_DRAW (0xFA) 403 UINT8 bMaxPower; 404 } usb_config_descriptor_t; 405 406 /* USB_DT_DEVICE_QUALIFIER: Device Qualifier descriptor */ 407 typedef struct usb_qualifier_descriptor { 408 UINT8 bLength; 409 UINT8 bDescriptorType; 410 411 UINT16 bcdUSB; 412 UINT8 bDeviceClass; 413 UINT8 bDeviceSubClass; 414 UINT8 bDeviceProtocol; 415 UINT8 bMaxPacketSize0; 416 UINT8 bNumConfigurations; 417 UINT8 bRESERVED; 418 } usb_qualifier_descriptor_t; 419 420 /* USB_DT_INTERFACE: Interface descriptor */ 421 typedef struct usb_interface_descriptor { 422 UINT8 bLength; 423 UINT8 bDescriptorType; 424 425 UINT8 bInterfaceNumber; 426 UINT8 bAlternateSetting; 427 UINT8 bNumEndpoints; 428 UINT8 bInterfaceClass; 429 UINT8 bInterfaceSubClass; 430 UINT8 bInterfaceProtocol; 431 UINT8 iInterface; 432 } usb_interface_descriptor_t; 433 434 /* USB_DT_ENDPOINT: Endpoint descriptor */ 435 typedef struct usb_endpoint_descriptor { 436 UINT8 bLength; 437 UINT8 bDescriptorType; 438 439 UINT8 bEndpointAddress; 440 UINT8 bmAttributes; 441 #define USB_ENDPOINT_XFER_CONTROL 0x00 442 #define USB_ENDPOINT_XFER_ISOC 0x01 443 #define USB_ENDPOINT_XFER_BULK 0x02 444 #define USB_ENDPOINT_XFER_INT 0x03 445 UINT16 wMaxPacketSize; 446 UINT8 bInterval; 447 } usb_endpoint_descriptor_t; 448 449 /* USB_DT_SS_ENDPOINT_COMP: SuperSpeed Endpoint Companion descriptor */ 450 typedef struct usb_ss_ep_comp_descriptor { 451 UINT8 bLength; 452 UINT8 bDescriptorType; 453 454 UINT8 bMaxBurst; 455 UINT8 bmAttributes; 456 UINT16 wBytesPerInterval; 457 } usb_ss_ep_comp_descriptor_t; 458 459 /* WUSB BOS Descriptor (Binary device Object Store) */ 460 typedef struct wusb_bos_desc { 461 UINT8 bLength; 462 UINT8 bDescriptorType; 463 UINT16 wTotalLength; 464 UINT8 bNumDeviceCaps; 465 } wusb_bos_desc_t; 466 467 #define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02 468 typedef struct usb_dev_cap_20_ext_desc { 469 UINT8 bLength; 470 UINT8 bDescriptorType; 471 UINT8 bDevCapabilityType; 472 #define USB_20_EXT_LPM 0x02 473 UINT32 bmAttributes; 474 } usb_dev_cap_20_ext_desc_t; 475 476 #define USB_DEVICE_CAPABILITY_SS_USB 0x03 477 typedef struct usb_dev_cap_ss_usb { 478 UINT8 bLength; 479 UINT8 bDescriptorType; 480 UINT8 bDevCapabilityType; 481 #define USB_DC_SS_USB_LTM_CAPABLE 0x02 482 UINT8 bmAttributes; 483 #define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01 484 #define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02 485 #define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04 486 #define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08 487 UINT32 wSpeedsSupported; 488 UINT8 bFunctionalitySupport; 489 UINT8 bU1DevExitLat; 490 UINT32 wU2DevExitLat; 491 } usb_dev_cap_ss_usb_t; 492 493 #define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04 494 typedef struct usb_dev_cap_container_id { 495 UINT8 bLength; 496 UINT8 bDescriptorType; 497 UINT8 bDevCapabilityType; 498 UINT8 bReserved; 499 UINT8 containerID[16]; 500 } usb_dev_cap_container_id_t; 501 #pragma pack() 502 503 typedef union usb_setup_pkt { 504 usb_device_request_t req; 505 UINT32 d32[2]; 506 UINT8 d8[8]; 507 } usb_setup_pkt_t; 508 509 typedef struct usb3_pcd_ep { 510 struct usb3_pcd *pcd; 511 512 UINT8 EpInIdx; 513 UINT8 EpOutIdx; 514 UINT8 phys; 515 516 //UINT8 phys; 517 UINT8 num; 518 UINT8 type; 519 UINT8 maxburst; 520 UINT16 maxpacket; 521 /* Tx FIFO # for IN EPs */ 522 UINT8 tx_fifo_num; 523 524 /* The Transfer Resource Index from the Start Transfer command */ 525 UINT8 tri_out; 526 UINT8 tri_in; 527 528 UINT8 stopped; 529 /* Send ZLP */ 530 UINT8 send_zlp; 531 /* True if 3-stage control transfer */ 532 UINT8 three_stage; 533 /* True if transfer has been started on EP */ 534 UINT8 xfer_started; 535 /* EP direction 0 = OUT */ 536 UINT8 is_in; 537 /* True if endpoint is active */ 538 UINT8 active; 539 /* Initial data pid of bulk endpoint */ 540 UINT8 data_pid_start; 541 542 /* ep_desc (excluding ep0) */ 543 usb3_dma_desc_t *ep_desc; 544 545 #if 0 546 /* TRB descriptor must be aligned to 16 bytes */ 547 UINT8 epx_desc[32]; 548 #endif 549 550 /* request (excluding ep0) */ 551 usb3_pcd_req_t req; 552 } usb3_pcd_ep_t; 553 554 typedef struct usb3_pcd { 555 //struct usb3_device *usb3_dev; 556 557 INT32 link_state; 558 pcdstate_e state; 559 UINT8 new_config; 560 ep0state_e ep0state; 561 562 UINT32 eps_enabled; 563 UINT32 ltm_enable; 564 565 usb3_pcd_ep_t ep0; 566 usb3_pcd_ep_t out_ep; 567 usb3_pcd_ep_t in_ep; 568 569 /* 570 usb3_dev_global_regs_t *dev_global_regs; 571 usb3_dev_ep_regs_t *out_ep_regs; 572 usb3_dev_ep_regs_t *in_ep_regs; 573 */ 574 575 usb3_pcd_req_t ep0_req; 576 577 UINT8 speed; 578 579 usb3_dma_desc_t *ep0_setup_desc; 580 usb3_dma_desc_t *ep0_in_desc; 581 usb3_dma_desc_t *ep0_out_desc; 582 583 /* TRB descriptor must be aligned to 16 bytes */ 584 #if 0 585 UINT8 ep0_setup[32]; 586 UINT8 ep0_in[32]; 587 UINT8 ep0_out[32]; 588 589 usb_setup_pkt_t ep0_setup_pkt[5]; 590 591 #define USB3_STATUS_BUF_SIZE 512 592 UINT8 ep0_status_buf[USB3_STATUS_BUF_SIZE]; 593 594 #define USB3_BULK_BUF_SIZE 2048 595 UINT8 ss_bulk_buf[USB3_BULK_BUF_SIZE]; 596 #endif 597 598 UINT32 file_type; 599 UINT32 file_address; 600 UINT32 file_capacity; 601 UINT32 file_total_frame; 602 UINT32 file_curr_frame; 603 UINT32 file_next_frame; 604 UINT32 file_received; 605 UINT32 file_complete; 606 607 UINT16 test_mode_nr; 608 UINT16 test_mode; 609 } usb3_pcd_t; 610 611 struct usb_enum_port_param { 612 UINT16 idVendor; 613 UINT16 idProduct; 614 UINT8 bInterfaceSubClass; 615 UINT8 bInterfaceProtocol; 616 }; 617 618 #if 0 619 typedef struct usb3_pcd_req { 620 usb3_dma_desc_t *trb; 621 UINT64 trbdma; 622 623 UINT32 length; 624 UINT32 actual; 625 626 UINT64 *bufdma; 627 int (*complete)(unsigned actual, int status); 628 } usb3_pcd_req_t; 629 630 #endif 631 632 #endif /* __DW_USB3_DXE_H__ */ 633
