1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <auth_mod.h> 11 #include <bl1.h> 12 #include <bl_common.h> 13 #include <console.h> 14 #include <debug.h> 15 #include <errata_report.h> 16 #include <platform.h> 17 #include <platform_def.h> 18 #include <smcc_helpers.h> 19 #include <utils.h> 20 #include <uuid.h> 21 #include "bl1_private.h" 22 23 /* BL1 Service UUID */ 24 DEFINE_SVC_UUID(bl1_svc_uid, 25 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75, 26 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); 27 28 29 static void bl1_load_bl2(void); 30 31 /******************************************************************************* 32 * The next function has a weak definition. Platform specific code can override 33 * it if it wishes to. 34 ******************************************************************************/ 35 #pragma weak bl1_init_bl2_mem_layout 36 37 /******************************************************************************* 38 * Function that takes a memory layout into which BL2 has been loaded and 39 * populates a new memory layout for BL2 that ensures that BL1's data sections 40 * resident in secure RAM are not visible to BL2. 41 ******************************************************************************/ 42 void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 43 meminfo_t *bl2_mem_layout) 44 { 45 46 assert(bl1_mem_layout != NULL); 47 assert(bl2_mem_layout != NULL); 48 49 #if LOAD_IMAGE_V2 50 /* 51 * Remove BL1 RW data from the scope of memory visible to BL2. 52 * This is assuming BL1 RW data is at the top of bl1_mem_layout. 53 */ 54 assert(BL1_RW_BASE > bl1_mem_layout->total_base); 55 bl2_mem_layout->total_base = bl1_mem_layout->total_base; 56 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; 57 #else 58 /* Check that BL1's memory is lying outside of the free memory */ 59 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || 60 (BL1_RAM_BASE >= bl1_mem_layout->free_base + 61 bl1_mem_layout->free_size)); 62 63 /* Remove BL1 RW data from the scope of memory visible to BL2 */ 64 *bl2_mem_layout = *bl1_mem_layout; 65 reserve_mem(&bl2_mem_layout->total_base, 66 &bl2_mem_layout->total_size, 67 BL1_RAM_BASE, 68 BL1_RAM_LIMIT - BL1_RAM_BASE); 69 #endif /* LOAD_IMAGE_V2 */ 70 71 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 72 } 73 74 /******************************************************************************* 75 * Function to perform late architectural and platform specific initialization. 76 * It also queries the platform to load and run next BL image. Only called 77 * by the primary cpu after a cold boot. 78 ******************************************************************************/ 79 void bl1_main(void) 80 { 81 unsigned int image_id; 82 83 /* Announce our arrival */ 84 NOTICE(FIRMWARE_WELCOME_STR); 85 NOTICE("BL1: %s\n", version_string); 86 NOTICE("BL1: %s\n", build_message); 87 88 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, 89 (void *)BL1_RAM_LIMIT); 90 91 print_errata_status(); 92 93 #if ENABLE_ASSERTIONS 94 u_register_t val; 95 /* 96 * Ensure that MMU/Caches and coherency are turned on 97 */ 98 #ifdef AARCH32 99 val = read_sctlr(); 100 #else 101 val = read_sctlr_el3(); 102 #endif 103 assert(val & SCTLR_M_BIT); 104 assert(val & SCTLR_C_BIT); 105 assert(val & SCTLR_I_BIT); 106 /* 107 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 108 * provided platform value 109 */ 110 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 111 /* 112 * If CWG is zero, then no CWG information is available but we can 113 * at least check the platform value is less than the architectural 114 * maximum. 115 */ 116 if (val != 0) 117 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 118 else 119 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 120 #endif /* ENABLE_ASSERTIONS */ 121 122 /* Perform remaining generic architectural setup from EL3 */ 123 bl1_arch_setup(); 124 125 #if TRUSTED_BOARD_BOOT 126 /* Initialize authentication module */ 127 auth_mod_init(); 128 #endif /* TRUSTED_BOARD_BOOT */ 129 130 /* Perform platform setup in BL1. */ 131 bl1_platform_setup(); 132 133 /* Get the image id of next image to load and run. */ 134 image_id = bl1_plat_get_next_image_id(); 135 136 /* 137 * We currently interpret any image id other than 138 * BL2_IMAGE_ID as the start of firmware update. 139 */ 140 if (image_id == BL2_IMAGE_ID) 141 bl1_load_bl2(); 142 else 143 NOTICE("BL1-FWU: *******FWU Process Started*******\n"); 144 145 bl1_prepare_next_image(image_id); 146 147 console_flush(); 148 } 149 150 /******************************************************************************* 151 * This function locates and loads the BL2 raw binary image in the trusted SRAM. 152 * Called by the primary cpu after a cold boot. 153 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 154 * loader etc. 155 ******************************************************************************/ 156 void bl1_load_bl2(void) 157 { 158 image_desc_t *image_desc; 159 image_info_t *image_info; 160 entry_point_info_t *ep_info; 161 meminfo_t *bl1_tzram_layout; 162 meminfo_t *bl2_tzram_layout; 163 int err; 164 165 /* Get the image descriptor */ 166 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 167 assert(image_desc); 168 169 /* Get the image info */ 170 image_info = &image_desc->image_info; 171 172 /* Get the entry point info */ 173 ep_info = &image_desc->ep_info; 174 175 /* Find out how much free trusted ram remains after BL1 load */ 176 bl1_tzram_layout = bl1_plat_sec_mem_layout(); 177 178 INFO("BL1: Loading BL2\n"); 179 180 #if LOAD_IMAGE_V2 181 err = load_auth_image(BL2_IMAGE_ID, image_info); 182 #else 183 /* Load the BL2 image */ 184 err = load_auth_image(bl1_tzram_layout, 185 BL2_IMAGE_ID, 186 image_info->image_base, 187 image_info, 188 ep_info); 189 190 #endif /* LOAD_IMAGE_V2 */ 191 192 if (err) { 193 ERROR("Failed to load BL2 firmware.\n"); 194 plat_error_handler(err); 195 } 196 197 /* 198 * Create a new layout of memory for BL2 as seen by BL1 i.e. 199 * tell it the amount of total and free memory available. 200 * This layout is created at the first free address visible 201 * to BL2. BL2 will read the memory layout before using its 202 * memory for other purposes. 203 */ 204 #if LOAD_IMAGE_V2 205 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base; 206 #else 207 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base; 208 #endif /* LOAD_IMAGE_V2 */ 209 210 bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); 211 212 ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout; 213 NOTICE("BL1: Booting BL2\n"); 214 VERBOSE("BL1: BL2 memory layout address = %p\n", 215 (void *) bl2_tzram_layout); 216 } 217 218 /******************************************************************************* 219 * Function called just before handing over to the next BL to inform the user 220 * about the boot progress. In debug mode, also print details about the BL 221 * image's execution context. 222 ******************************************************************************/ 223 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) 224 { 225 #ifdef AARCH32 226 NOTICE("BL1: Booting BL32\n"); 227 #else 228 NOTICE("BL1: Booting BL31\n"); 229 #endif /* AARCH32 */ 230 print_entry_point_info(bl_ep_info); 231 } 232 233 #if SPIN_ON_BL1_EXIT 234 void print_debug_loop_message(void) 235 { 236 NOTICE("BL1: Debug loop, spinning forever\n"); 237 NOTICE("BL1: Please connect the debugger to continue\n"); 238 } 239 #endif 240 241 /******************************************************************************* 242 * Top level handler for servicing BL1 SMCs. 243 ******************************************************************************/ 244 register_t bl1_smc_handler(unsigned int smc_fid, 245 register_t x1, 246 register_t x2, 247 register_t x3, 248 register_t x4, 249 void *cookie, 250 void *handle, 251 unsigned int flags) 252 { 253 254 #if TRUSTED_BOARD_BOOT 255 /* 256 * Dispatch FWU calls to FWU SMC handler and return its return 257 * value 258 */ 259 if (is_fwu_fid(smc_fid)) { 260 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 261 handle, flags); 262 } 263 #endif 264 265 switch (smc_fid) { 266 case BL1_SMC_CALL_COUNT: 267 SMC_RET1(handle, BL1_NUM_SMC_CALLS); 268 269 case BL1_SMC_UID: 270 SMC_UUID_RET(handle, bl1_svc_uid); 271 272 case BL1_SMC_VERSION: 273 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); 274 275 default: 276 break; 277 } 278 279 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid); 280 SMC_RET1(handle, SMC_UNK); 281 } 282 283 /******************************************************************************* 284 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI 285 * compliance when invoking bl1_smc_handler. 286 ******************************************************************************/ 287 register_t bl1_smc_wrapper(uint32_t smc_fid, 288 void *cookie, 289 void *handle, 290 unsigned int flags) 291 { 292 register_t x1, x2, x3, x4; 293 294 assert(handle); 295 296 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 297 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 298 } 299
