1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <aem_generic.h> 7 #include <arch.h> 8 #include <asm_macros.S> 9 #include <assert_macros.S> 10 #include <cpu_macros.S> 11 12 func aem_generic_core_pwr_dwn 13 /* Assert if cache is enabled */ 14 #if ENABLE_ASSERTIONS 15 ldcopr r0, SCTLR 16 tst r0, #SCTLR_C_BIT 17 ASM_ASSERT(eq) 18 #endif 19 /* --------------------------------------------- 20 * Flush L1 cache to PoU. 21 * --------------------------------------------- 22 */ 23 mov r0, #DC_OP_CISW 24 b dcsw_op_louis 25 endfunc aem_generic_core_pwr_dwn 26 27 28 func aem_generic_cluster_pwr_dwn 29 /* Assert if cache is enabled */ 30 #if ENABLE_ASSERTIONS 31 ldcopr r0, SCTLR 32 tst r0, #SCTLR_C_BIT 33 ASM_ASSERT(eq) 34 #endif 35 /* --------------------------------------------- 36 * Flush L1 and L2 caches to PoC. 37 * --------------------------------------------- 38 */ 39 mov r0, #DC_OP_CISW 40 b dcsw_op_all 41 endfunc aem_generic_cluster_pwr_dwn 42 43 /* cpu_ops for Base AEM FVP */ 44 declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \ 45 aem_generic_core_pwr_dwn, \ 46 aem_generic_cluster_pwr_dwn 47
