1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch.h> 7 #include <asm_macros.S> 8 #include <assert_macros.S> 9 #include <cortex_a53.h> 10 #include <cpu_macros.S> 11 #include <debug.h> 12 13 #if A53_DISABLE_NON_TEMPORAL_HINT 14 #undef ERRATA_A53_836870 15 #define ERRATA_A53_836870 1 16 #endif 17 18 /* --------------------------------------------- 19 * Disable intra-cluster coherency 20 * --------------------------------------------- 21 */ 22 func cortex_a53_disable_smp 23 ldcopr16 r0, r1, CORTEX_A53_ECTLR 24 bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT 25 stcopr16 r0, r1, CORTEX_A53_ECTLR 26 isb 27 dsb sy 28 bx lr 29 endfunc cortex_a53_disable_smp 30 31 /* -------------------------------------------------- 32 * Errata Workaround for Cortex A53 Errata #826319. 33 * This applies only to revision <= r0p2 of Cortex A53. 34 * Inputs: 35 * r0: variant[4:7] and revision[0:3] of current cpu. 36 * Shall clobber: r0-r3 37 * -------------------------------------------------- 38 */ 39 func errata_a53_826319_wa 40 /* 41 * Compare r0 against revision r0p2 42 */ 43 mov r2, lr 44 bl check_errata_826319 45 mov lr, r2 46 cmp r0, #ERRATA_NOT_APPLIES 47 beq 1f 48 ldcopr r0, CORTEX_A53_L2ACTLR 49 bic r0, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN 50 orr r0, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH 51 stcopr r0, CORTEX_A53_L2ACTLR 52 1: 53 bx lr 54 endfunc errata_a53_826319_wa 55 56 func check_errata_826319 57 mov r1, #0x02 58 b cpu_rev_var_ls 59 endfunc check_errata_826319 60 61 /* --------------------------------------------------------------------- 62 * Disable the cache non-temporal hint. 63 * 64 * This ignores the Transient allocation hint in the MAIR and treats 65 * allocations the same as non-transient allocation types. As a result, 66 * the LDNP and STNP instructions in AArch64 behave the same as the 67 * equivalent LDP and STP instructions. 68 * 69 * This is relevant only for revisions <= r0p3 of Cortex-A53. 70 * From r0p4 and onwards, the bit to disable the hint is enabled by 71 * default at reset. 72 * 73 * Inputs: 74 * r0: variant[4:7] and revision[0:3] of current cpu. 75 * Shall clobber: r0-r3 76 * --------------------------------------------------------------------- 77 */ 78 func a53_disable_non_temporal_hint 79 /* 80 * Compare r0 against revision r0p3 81 */ 82 mov r2, lr 83 bl check_errata_disable_non_temporal_hint 84 mov lr, r2 85 cmp r0, #ERRATA_NOT_APPLIES 86 beq 1f 87 ldcopr16 r0, r1, CORTEX_A53_CPUACTLR 88 orr64_imm r0, r1, CORTEX_A53_CPUACTLR_DTAH 89 stcopr16 r0, r1, CORTEX_A53_CPUACTLR 90 1: 91 bx lr 92 endfunc a53_disable_non_temporal_hint 93 94 func check_errata_disable_non_temporal_hint 95 mov r1, #0x03 96 b cpu_rev_var_ls 97 endfunc check_errata_disable_non_temporal_hint 98 99 /* -------------------------------------------------- 100 * Errata Workaround for Cortex A53 Errata #855873. 101 * 102 * This applies only to revisions >= r0p3 of Cortex A53. 103 * Earlier revisions of the core are affected as well, but don't 104 * have the chicken bit in the CPUACTLR register. It is expected that 105 * the rich OS takes care of that, especially as the workaround is 106 * shared with other erratas in those revisions of the CPU. 107 * Inputs: 108 * r0: variant[4:7] and revision[0:3] of current cpu. 109 * Shall clobber: r0-r3 110 * -------------------------------------------------- 111 */ 112 func errata_a53_855873_wa 113 /* 114 * Compare r0 against revision r0p3 and higher 115 */ 116 mov r2, lr 117 bl check_errata_855873 118 mov lr, r2 119 cmp r0, #ERRATA_NOT_APPLIES 120 beq 1f 121 ldcopr16 r0, r1, CORTEX_A53_CPUACTLR 122 orr64_imm r0, r1, CORTEX_A53_CPUACTLR_ENDCCASCI 123 stcopr16 r0, r1, CORTEX_A53_CPUACTLR 124 1: 125 bx lr 126 endfunc errata_a53_855873_wa 127 128 func check_errata_855873 129 mov r1, #0x03 130 b cpu_rev_var_hs 131 endfunc check_errata_855873 132 133 /* ------------------------------------------------- 134 * The CPU Ops reset function for Cortex-A53. 135 * Shall clobber: r0-r6 136 * ------------------------------------------------- 137 */ 138 func cortex_a53_reset_func 139 mov r5, lr 140 bl cpu_get_rev_var 141 mov r4, r0 142 143 #if ERRATA_A53_826319 144 mov r0, r4 145 bl errata_a53_826319_wa 146 #endif 147 148 #if ERRATA_A53_836870 149 mov r0, r4 150 bl a53_disable_non_temporal_hint 151 #endif 152 153 #if ERRATA_A53_855873 154 mov r0, r4 155 bl errata_a53_855873_wa 156 #endif 157 158 /* --------------------------------------------- 159 * Enable the SMP bit. 160 * --------------------------------------------- 161 */ 162 ldcopr16 r0, r1, CORTEX_A53_ECTLR 163 orr64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT 164 stcopr16 r0, r1, CORTEX_A53_ECTLR 165 isb 166 bx r5 167 endfunc cortex_a53_reset_func 168 169 /* ---------------------------------------------------- 170 * The CPU Ops core power down function for Cortex-A53. 171 * ---------------------------------------------------- 172 */ 173 func cortex_a53_core_pwr_dwn 174 push {r12, lr} 175 176 /* Assert if cache is enabled */ 177 #if ASM_ASSERTION 178 ldcopr r0, SCTLR 179 tst r0, #SCTLR_C_BIT 180 ASM_ASSERT(eq) 181 #endif 182 183 /* --------------------------------------------- 184 * Flush L1 caches. 185 * --------------------------------------------- 186 */ 187 mov r0, #DC_OP_CISW 188 bl dcsw_op_level1 189 190 /* --------------------------------------------- 191 * Come out of intra cluster coherency 192 * --------------------------------------------- 193 */ 194 pop {r12, lr} 195 b cortex_a53_disable_smp 196 endfunc cortex_a53_core_pwr_dwn 197 198 /* ------------------------------------------------------- 199 * The CPU Ops cluster power down function for Cortex-A53. 200 * Clobbers: r0-r3 201 * ------------------------------------------------------- 202 */ 203 func cortex_a53_cluster_pwr_dwn 204 push {r12, lr} 205 206 /* Assert if cache is enabled */ 207 #if ASM_ASSERTION 208 ldcopr r0, SCTLR 209 tst r0, #SCTLR_C_BIT 210 ASM_ASSERT(eq) 211 #endif 212 213 /* --------------------------------------------- 214 * Flush L1 caches. 215 * --------------------------------------------- 216 */ 217 mov r0, #DC_OP_CISW 218 bl dcsw_op_level1 219 220 /* --------------------------------------------- 221 * Disable the optional ACP. 222 * --------------------------------------------- 223 */ 224 bl plat_disable_acp 225 226 /* --------------------------------------------- 227 * Flush L2 caches. 228 * --------------------------------------------- 229 */ 230 mov r0, #DC_OP_CISW 231 bl dcsw_op_level2 232 233 /* --------------------------------------------- 234 * Come out of intra cluster coherency 235 * --------------------------------------------- 236 */ 237 pop {r12, lr} 238 b cortex_a53_disable_smp 239 endfunc cortex_a53_cluster_pwr_dwn 240 241 #if REPORT_ERRATA 242 /* 243 * Errata printing function for Cortex A53. Must follow AAPCS. 244 */ 245 func cortex_a53_errata_report 246 push {r12, lr} 247 248 bl cpu_get_rev_var 249 mov r4, r0 250 251 /* 252 * Report all errata. The revision-variant information is passed to 253 * checking functions of each errata. 254 */ 255 report_errata ERRATA_A53_826319, cortex_a53, 826319 256 report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint 257 report_errata ERRATA_A53_855873, cortex_a53, 855873 258 259 pop {r12, lr} 260 bx lr 261 endfunc cortex_a53_errata_report 262 #endif 263 264 declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ 265 cortex_a53_reset_func, \ 266 cortex_a53_core_pwr_dwn, \ 267 cortex_a53_cluster_pwr_dwn 268
