1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch.h> 7 #include <asm_macros.S> 8 #include <bl_common.h> 9 #include <cortex_a53.h> 10 #include <cpu_macros.S> 11 #include <debug.h> 12 #include <plat_macros.S> 13 14 #if A53_DISABLE_NON_TEMPORAL_HINT 15 #undef ERRATA_A53_836870 16 #define ERRATA_A53_836870 1 17 #endif 18 19 /* --------------------------------------------- 20 * Disable L1 data cache and unified L2 cache 21 * --------------------------------------------- 22 */ 23 func cortex_a53_disable_dcache 24 mrs x1, sctlr_el3 25 bic x1, x1, #SCTLR_C_BIT 26 msr sctlr_el3, x1 27 isb 28 ret 29 endfunc cortex_a53_disable_dcache 30 31 /* --------------------------------------------- 32 * Disable intra-cluster coherency 33 * --------------------------------------------- 34 */ 35 func cortex_a53_disable_smp 36 mrs x0, CORTEX_A53_ECTLR_EL1 37 bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT 38 msr CORTEX_A53_ECTLR_EL1, x0 39 isb 40 dsb sy 41 ret 42 endfunc cortex_a53_disable_smp 43 44 /* -------------------------------------------------- 45 * Errata Workaround for Cortex A53 Errata #826319. 46 * This applies only to revision <= r0p2 of Cortex A53. 47 * Inputs: 48 * x0: variant[4:7] and revision[0:3] of current cpu. 49 * Shall clobber: x0-x17 50 * -------------------------------------------------- 51 */ 52 func errata_a53_826319_wa 53 /* 54 * Compare x0 against revision r0p2 55 */ 56 mov x17, x30 57 bl check_errata_826319 58 cbz x0, 1f 59 mrs x1, CORTEX_A53_L2ACTLR_EL1 60 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN 61 orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH 62 msr CORTEX_A53_L2ACTLR_EL1, x1 63 1: 64 ret x17 65 endfunc errata_a53_826319_wa 66 67 func check_errata_826319 68 mov x1, #0x02 69 b cpu_rev_var_ls 70 endfunc check_errata_826319 71 72 /* --------------------------------------------------------------------- 73 * Disable the cache non-temporal hint. 74 * 75 * This ignores the Transient allocation hint in the MAIR and treats 76 * allocations the same as non-transient allocation types. As a result, 77 * the LDNP and STNP instructions in AArch64 behave the same as the 78 * equivalent LDP and STP instructions. 79 * 80 * This is relevant only for revisions <= r0p3 of Cortex-A53. 81 * From r0p4 and onwards, the bit to disable the hint is enabled by 82 * default at reset. 83 * 84 * Inputs: 85 * x0: variant[4:7] and revision[0:3] of current cpu. 86 * Shall clobber: x0-x17 87 * --------------------------------------------------------------------- 88 */ 89 func a53_disable_non_temporal_hint 90 /* 91 * Compare x0 against revision r0p3 92 */ 93 mov x17, x30 94 bl check_errata_disable_non_temporal_hint 95 cbz x0, 1f 96 mrs x1, CORTEX_A53_CPUACTLR_EL1 97 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH 98 msr CORTEX_A53_CPUACTLR_EL1, x1 99 1: 100 ret x17 101 endfunc a53_disable_non_temporal_hint 102 103 func check_errata_disable_non_temporal_hint 104 mov x1, #0x03 105 b cpu_rev_var_ls 106 endfunc check_errata_disable_non_temporal_hint 107 108 /* -------------------------------------------------- 109 * Errata Workaround for Cortex A53 Errata #855873. 110 * 111 * This applies only to revisions >= r0p3 of Cortex A53. 112 * Earlier revisions of the core are affected as well, but don't 113 * have the chicken bit in the CPUACTLR register. It is expected that 114 * the rich OS takes care of that, especially as the workaround is 115 * shared with other erratas in those revisions of the CPU. 116 * Inputs: 117 * x0: variant[4:7] and revision[0:3] of current cpu. 118 * Shall clobber: x0-x17 119 * -------------------------------------------------- 120 */ 121 func errata_a53_855873_wa 122 /* 123 * Compare x0 against revision r0p3 and higher 124 */ 125 mov x17, x30 126 bl check_errata_855873 127 cbz x0, 1f 128 129 mrs x1, CORTEX_A53_CPUACTLR_EL1 130 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI 131 msr CORTEX_A53_CPUACTLR_EL1, x1 132 1: 133 ret x17 134 endfunc errata_a53_855873_wa 135 136 func check_errata_855873 137 mov x1, #0x03 138 b cpu_rev_var_hs 139 endfunc check_errata_855873 140 141 /* 142 * Errata workaround for Cortex A53 Errata #835769. 143 * This applies to revisions <= r0p4 of Cortex A53. 144 * This workaround is statically enabled at build time. 145 */ 146 func check_errata_835769 147 mov x1, #0x04 148 b cpu_rev_var_ls 149 endfunc check_errata_835769 150 151 /* 152 * Errata workaround for Cortex A53 Errata #843419. 153 * This applies to revisions <= r0p4 of Cortex A53. 154 * This workaround is statically enabled at build time. 155 */ 156 func check_errata_843419 157 mov x1, #0x04 158 b cpu_rev_var_ls 159 endfunc check_errata_843419 160 161 /* ------------------------------------------------- 162 * The CPU Ops reset function for Cortex-A53. 163 * Shall clobber: x0-x19 164 * ------------------------------------------------- 165 */ 166 func cortex_a53_reset_func 167 mov x19, x30 168 bl cpu_get_rev_var 169 mov x18, x0 170 171 172 #if ERRATA_A53_826319 173 mov x0, x18 174 bl errata_a53_826319_wa 175 #endif 176 177 #if ERRATA_A53_836870 178 mov x0, x18 179 bl a53_disable_non_temporal_hint 180 #endif 181 182 #if ERRATA_A53_855873 183 mov x0, x18 184 bl errata_a53_855873_wa 185 #endif 186 187 /* --------------------------------------------- 188 * Enable the SMP bit. 189 * --------------------------------------------- 190 */ 191 mrs x0, CORTEX_A53_ECTLR_EL1 192 orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT 193 msr CORTEX_A53_ECTLR_EL1, x0 194 isb 195 ret x19 196 endfunc cortex_a53_reset_func 197 198 func cortex_a53_core_pwr_dwn 199 mov x18, x30 200 201 /* --------------------------------------------- 202 * Turn off caches. 203 * --------------------------------------------- 204 */ 205 bl cortex_a53_disable_dcache 206 207 /* --------------------------------------------- 208 * Flush L1 caches. 209 * --------------------------------------------- 210 */ 211 mov x0, #DCCISW 212 bl dcsw_op_level1 213 214 /* --------------------------------------------- 215 * Come out of intra cluster coherency 216 * --------------------------------------------- 217 */ 218 mov x30, x18 219 b cortex_a53_disable_smp 220 endfunc cortex_a53_core_pwr_dwn 221 222 func cortex_a53_cluster_pwr_dwn 223 mov x18, x30 224 225 /* --------------------------------------------- 226 * Turn off caches. 227 * --------------------------------------------- 228 */ 229 bl cortex_a53_disable_dcache 230 231 /* --------------------------------------------- 232 * Flush L1 caches. 233 * --------------------------------------------- 234 */ 235 mov x0, #DCCISW 236 bl dcsw_op_level1 237 238 /* --------------------------------------------- 239 * Disable the optional ACP. 240 * --------------------------------------------- 241 */ 242 bl plat_disable_acp 243 244 /* --------------------------------------------- 245 * Flush L2 caches. 246 * --------------------------------------------- 247 */ 248 mov x0, #DCCISW 249 bl dcsw_op_level2 250 251 /* --------------------------------------------- 252 * Come out of intra cluster coherency 253 * --------------------------------------------- 254 */ 255 mov x30, x18 256 b cortex_a53_disable_smp 257 endfunc cortex_a53_cluster_pwr_dwn 258 259 #if REPORT_ERRATA 260 /* 261 * Errata printing function for Cortex A53. Must follow AAPCS. 262 */ 263 func cortex_a53_errata_report 264 stp x8, x30, [sp, #-16]! 265 266 bl cpu_get_rev_var 267 mov x8, x0 268 269 /* 270 * Report all errata. The revision-variant information is passed to 271 * checking functions of each errata. 272 */ 273 report_errata ERRATA_A53_826319, cortex_a53, 826319 274 report_errata ERRATA_A53_835769, cortex_a53, 835769 275 report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint 276 report_errata ERRATA_A53_843419, cortex_a53, 843419 277 report_errata ERRATA_A53_855873, cortex_a53, 855873 278 279 ldp x8, x30, [sp], #16 280 ret 281 endfunc cortex_a53_errata_report 282 #endif 283 284 /* --------------------------------------------- 285 * This function provides cortex_a53 specific 286 * register information for crash reporting. 287 * It needs to return with x6 pointing to 288 * a list of register names in ascii and 289 * x8 - x15 having values of registers to be 290 * reported. 291 * --------------------------------------------- 292 */ 293 .section .rodata.cortex_a53_regs, "aS" 294 cortex_a53_regs: /* The ascii list of register names to be reported */ 295 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ 296 "cpuactlr_el1", "" 297 298 func cortex_a53_cpu_reg_dump 299 adr x6, cortex_a53_regs 300 mrs x8, CORTEX_A53_ECTLR_EL1 301 mrs x9, CORTEX_A53_MERRSR_EL1 302 mrs x10, CORTEX_A53_L2MERRSR_EL1 303 mrs x11, CORTEX_A53_CPUACTLR_EL1 304 ret 305 endfunc cortex_a53_cpu_reg_dump 306 307 declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ 308 cortex_a53_reset_func, \ 309 cortex_a53_core_pwr_dwn, \ 310 cortex_a53_cluster_pwr_dwn 311
