1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arm_def.h> 7 #include <plat_arm.h> 8 9 /* 10 * Table of memory regions for different BL stages to map using the MMU. 11 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 12 * takes care of mapping it. 13 */ 14 #ifdef IMAGE_BL1 15 const mmap_region_t plat_arm_mmap[] = { 16 ARM_MAP_SHARED_RAM, 17 V2M_MAP_FLASH0_RO, 18 V2M_MAP_IOFPGA, 19 CSS_MAP_DEVICE, 20 SOC_CSS_MAP_DEVICE, 21 #if TRUSTED_BOARD_BOOT 22 /* Map DRAM to authenticate NS_BL2U image. */ 23 ARM_MAP_NS_DRAM1, 24 #endif 25 {0} 26 }; 27 #endif 28 #ifdef IMAGE_BL2 29 const mmap_region_t plat_arm_mmap[] = { 30 ARM_MAP_SHARED_RAM, 31 V2M_MAP_FLASH0_RO, 32 #ifdef PLAT_ARM_MEM_PROT_ADDR 33 ARM_V2M_MAP_MEM_PROTECT, 34 #endif 35 V2M_MAP_IOFPGA, 36 CSS_MAP_DEVICE, 37 SOC_CSS_MAP_DEVICE, 38 ARM_MAP_NS_DRAM1, 39 #ifdef AARCH64 40 ARM_MAP_DRAM2, 41 #endif 42 #ifdef SPD_tspd 43 ARM_MAP_TSP_SEC_MEM, 44 #endif 45 #ifdef SPD_opteed 46 ARM_MAP_OPTEE_CORE_MEM, 47 ARM_OPTEE_PAGEABLE_LOAD_MEM, 48 #endif 49 {0} 50 }; 51 #endif 52 #ifdef IMAGE_BL2U 53 const mmap_region_t plat_arm_mmap[] = { 54 ARM_MAP_SHARED_RAM, 55 CSS_MAP_DEVICE, 56 SOC_CSS_MAP_DEVICE, 57 {0} 58 }; 59 #endif 60 #ifdef IMAGE_BL31 61 const mmap_region_t plat_arm_mmap[] = { 62 ARM_MAP_SHARED_RAM, 63 V2M_MAP_IOFPGA, 64 CSS_MAP_DEVICE, 65 #ifdef PLAT_ARM_MEM_PROT_ADDR 66 ARM_V2M_MAP_MEM_PROTECT, 67 #endif 68 SOC_CSS_MAP_DEVICE, 69 {0} 70 }; 71 #endif 72 #ifdef IMAGE_BL32 73 const mmap_region_t plat_arm_mmap[] = { 74 #ifdef AARCH32 75 ARM_MAP_SHARED_RAM, 76 #endif 77 V2M_MAP_IOFPGA, 78 CSS_MAP_DEVICE, 79 SOC_CSS_MAP_DEVICE, 80 {0} 81 }; 82 #endif 83 84 ARM_CASSERT_MMAP 85
