1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arm_def.h> 11 #include <board_arm_def.h> 12 #include <common_def.h> 13 #include <tzc400.h> 14 #include <utils_def.h> 15 #include <v2m_def.h> 16 #include "../fvp_def.h" 17 18 /* Required platform porting definitions */ 19 #define PLATFORM_CORE_COUNT \ 20 (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) 21 22 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 23 PLATFORM_CORE_COUNT) + 1 24 25 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 26 27 /* 28 * Other platform porting definitions are provided by included headers 29 */ 30 31 /* 32 * Required ARM standard platform porting definitions 33 */ 34 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 35 36 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 37 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ 38 39 #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 40 #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ 41 42 /* No SCP in FVP */ 43 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) 44 45 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) 46 47 /* 48 * Load address of BL33 for this platform port 49 */ 50 #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) 51 52 53 /* 54 * PL011 related constants 55 */ 56 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 57 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 58 59 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 60 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 61 62 #define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 63 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 64 65 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 66 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 67 68 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 69 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 70 71 #define PLAT_FVP_SMMUV3_BASE 0x2b400000 72 73 /* CCI related constants */ 74 #define PLAT_FVP_CCI400_BASE 0x2c090000 75 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 76 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 77 78 /* CCI-500/CCI-550 on Base platform */ 79 #define PLAT_FVP_CCI5XX_BASE 0x2a000000 80 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 81 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 82 83 /* CCN related constants. Only CCN 502 is currently supported */ 84 #define PLAT_ARM_CCN_BASE 0x2e000000 85 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 86 87 /* System timer related constants */ 88 #define PLAT_ARM_NSTIMER_FRAME_ID 1 89 90 /* Mailbox base address */ 91 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 92 93 94 /* TrustZone controller related constants 95 * 96 * Currently only filters 0 and 2 are connected on Base FVP. 97 * Filter 0 : CPU clusters (no access to DRAM by default) 98 * Filter 1 : not connected 99 * Filter 2 : LCDs (access to VRAM allowed by default) 100 * Filter 3 : not connected 101 * Programming unconnected filters will have no effect at the 102 * moment. These filter could, however, be connected in future. 103 * So care should be taken not to configure the unused filters. 104 * 105 * Allow only non-secure access to all DRAM to supported devices. 106 * Give access to the CPUs and Virtio. Some devices 107 * would normally use the default ID so allow that too. 108 */ 109 #define PLAT_ARM_TZC_BASE 0x2a4a0000 110 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 111 112 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 113 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 114 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 115 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 116 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 117 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 118 119 /* 120 * GIC related constants to cater for both GICv2 and GICv3 instances of an 121 * FVP. They could be overriden at runtime in case the FVP implements the legacy 122 * VE memory map. 123 */ 124 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 125 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 126 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 127 128 /* 129 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 130 * terminology. On a GICv2 system or mode, the lists will be merged and treated 131 * as Group 0 interrupts. 132 */ 133 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 134 FVP_IRQ_TZ_WDOG, \ 135 FVP_IRQ_SEC_SYS_TIMER 136 137 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 138 139 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 140 ARM_G1S_IRQ_PROPS(grp), \ 141 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ 142 GIC_INTR_CFG_LEVEL), \ 143 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 144 GIC_INTR_CFG_LEVEL) 145 146 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 147 148 #endif /* __PLATFORM_DEF_H__ */ 149
