1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __HI6220_REGS_ACPU_H__ 8 #define __HI6220_REGS_ACPU_H__ 9 10 #define ACPU_CTRL_BASE 0xF6504000 11 12 #define ACPU_SC_CPU_CTRL (ACPU_CTRL_BASE + 0x000) 13 #define ACPU_SC_CPU_STAT (ACPU_CTRL_BASE + 0x008) 14 #define ACPU_SC_CPU_STAT_SC_STANDBYWFIL2 (1 << 0) 15 #define ACPU_SC_CPU_STAT_SC_STANDBYWFIL2_SHIFT (0) 16 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI0 (1 << 1) 17 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI0_SHIFT (1) 18 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI1 (1 << 2) 19 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI1_SHIFT (2) 20 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI2 (1 << 3) 21 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI2_SHIFT (3) 22 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI3 (1 << 4) 23 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI3_SHIFT (4) 24 #define ACPU_SC_CPU_STAT_A53_1_STANDBYWFIL2 (1 << 8) 25 #define ACPU_SC_CPU_STAT_A53_1_STANDBYWFIL2_SHIFT (8) 26 #define ACPU_SC_CPU_STAT_A53_1_STANDBYWFI (1 << 9) 27 #define ACPU_SC_CPU_STAT_A53_1_STANDBYWFI_SHIFT (9) 28 #define ACPU_SC_CPU_STAT_L2FLSHUDONE0 (1 << 16) 29 #define ACPU_SC_CPU_STAT_L2FLSHUDONE0_SHIFT (16) 30 #define ACPU_SC_CPU_STAT_L2FLSHUDONE1 (1 << 17) 31 #define ACPU_SC_CPU_STAT_L2FLSHUDONE1_SHIFT (17) 32 #define ACPU_SC_CPU_STAT_CCI400_ACTIVE (1 << 18) 33 #define ACPU_SC_CPU_STAT_CCI400_ACTIVE_SHIFT (18) 34 #define ACPU_SC_CPU_STAT_CLK_DIV_STATUS_VD (1 << 20) 35 #define ACPU_SC_CPU_STAT_CLK_DIV_STATUS_VD_SHIFT (20) 36 37 #define ACPU_SC_CLKEN (ACPU_CTRL_BASE + 0x00c) 38 #define HPM_L2_1_CLKEN (1 << 9) 39 #define G_CPU_1_CLKEN (1 << 8) 40 #define HPM_L2_CLKEN (1 << 1) 41 #define G_CPU_CLKEN (1 << 0) 42 43 #define ACPU_SC_CLKDIS (ACPU_CTRL_BASE + 0x010) 44 #define ACPU_SC_CLK_STAT (ACPU_CTRL_BASE + 0x014) 45 #define ACPU_SC_RSTEN (ACPU_CTRL_BASE + 0x018) 46 #define SRST_PRESET1_RSTEN (1 << 11) 47 #define SRST_PRESET0_RSTEN (1 << 10) 48 #define SRST_CLUSTER1_RSTEN (1 << 9) 49 #define SRST_CLUSTER0_RSTEN (1 << 8) 50 #define SRST_L2_HPM_1_RSTEN (1 << 5) 51 #define SRST_AARM_L2_1_RSTEN (1 << 4) 52 #define SRST_L2_HPM_0_RSTEN (1 << 3) 53 #define SRST_AARM_L2_0_RSTEN (1 << 1) 54 #define SRST_CLUSTER1 (SRST_PRESET1_RSTEN | \ 55 SRST_CLUSTER1_RSTEN | \ 56 SRST_L2_HPM_1_RSTEN | \ 57 SRST_AARM_L2_1_RSTEN) 58 #define SRST_CLUSTER0 (SRST_PRESET0_RSTEN | \ 59 SRST_CLUSTER0_RSTEN | \ 60 SRST_L2_HPM_0_RSTEN | \ 61 SRST_AARM_L2_0_RSTEN) 62 63 #define ACPU_SC_RSTDIS (ACPU_CTRL_BASE + 0x01c) 64 #define ACPU_SC_RST_STAT (ACPU_CTRL_BASE + 0x020) 65 #define ACPU_SC_PDBGUP_MBIST (ACPU_CTRL_BASE + 0x02c) 66 #define PDBGUP_CLUSTER1_SHIFT 8 67 68 #define ACPU_SC_VD_CTRL (ACPU_CTRL_BASE + 0x054) 69 #define ACPU_SC_VD_MASK_PATTERN_CTRL (ACPU_CTRL_BASE + 0x058) 70 #define ACPU_SC_VD_MASK_PATTERN_VAL (0xCCB << 12) 71 #define ACPU_SC_VD_MASK_PATTERN_MASK ((0x1 << 13) - 1) 72 73 #define ACPU_SC_VD_DLY_FIXED_CTRL (ACPU_CTRL_BASE + 0x05c) 74 #define ACPU_SC_VD_DLY_TABLE0_CTRL (ACPU_CTRL_BASE + 0x060) 75 #define ACPU_SC_VD_DLY_TABLE1_CTRL (ACPU_CTRL_BASE + 0x064) 76 #define ACPU_SC_VD_DLY_TABLE2_CTRL (ACPU_CTRL_BASE + 0x068) 77 #define ACPU_SC_VD_HPM_CTRL (ACPU_CTRL_BASE + 0x06c) 78 #define ACPU_SC_A53_CLUSTER_MTCMOS_EN (ACPU_CTRL_BASE + 0x088) 79 #define PW_MTCMOS_EN_A53_1_EN (1 << 1) 80 #define PW_MTCMOS_EN_A53_0_EN (1 << 0) 81 82 #define ACPU_SC_A53_CLUSTER_MTCMOS_STA (ACPU_CTRL_BASE + 0x090) 83 #define ACPU_SC_A53_CLUSTER_ISO_EN (ACPU_CTRL_BASE + 0x098) 84 #define PW_ISO_A53_1_EN (1 << 1) 85 #define PW_ISO_A53_0_EN (1 << 0) 86 87 #define ACPU_SC_A53_CLUSTER_ISO_DIS (ACPU_CTRL_BASE + 0x09c) 88 #define ACPU_SC_A53_CLUSTER_ISO_STA (ACPU_CTRL_BASE + 0x0a0) 89 #define ACPU_SC_A53_1_MTCMOS_TIMER (ACPU_CTRL_BASE + 0x0b4) 90 #define ACPU_SC_A53_0_MTCMOS_TIMER (ACPU_CTRL_BASE + 0x0bc) 91 #define ACPU_SC_A53_x_MTCMOS_TIMER(x) ((x) ? ACPU_SC_A53_1_MTCMOS_TIMER : ACPU_SC_A53_0_MTCMOS_TIMER) 92 93 #define ACPU_SC_SNOOP_PWD (ACPU_CTRL_BASE + 0xe4) 94 #define PD_DETECT_START1 (1 << 16) 95 #define PD_DETECT_START0 (1 << 0) 96 97 #define ACPU_SC_CPU0_CTRL (ACPU_CTRL_BASE + 0x100) 98 #define CPU_CTRL_AARCH64_MODE (1 << 7) 99 100 #define ACPU_SC_CPU0_STAT (ACPU_CTRL_BASE + 0x104) 101 #define ACPU_SC_CPU0_CLKEN (ACPU_CTRL_BASE + 0x108) 102 #define CPU_CLKEN_HPM (1 << 1) 103 104 #define ACPU_SC_CPU0_CLK_STAT (ACPU_CTRL_BASE + 0x110) 105 106 #define ACPU_SC_CPU0_RSTEN (ACPU_CTRL_BASE + 0x114) 107 #define ACPU_SC_CPU0_RSTDIS (ACPU_CTRL_BASE + 0x118) 108 #define ACPU_SC_CPU0_MTCMOS_EN (ACPU_CTRL_BASE + 0x120) 109 #define CPU_MTCMOS_PW (1 << 0) 110 111 #define ACPU_SC_CPU0_PW_ISOEN (ACPU_CTRL_BASE + 0x130) 112 #define CPU_PW_ISO (1 << 0) 113 114 #define ACPU_SC_CPU0_PW_ISODIS (ACPU_CTRL_BASE + 0x134) 115 #define ACPU_SC_CPU0_PW_ISO_STAT (ACPU_CTRL_BASE + 0x138) 116 #define ACPU_SC_CPU0_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x154) 117 #define CPU_MTCMOS_TIMER_STA (1 << 0) 118 119 #define ACPU_SC_CPU0_RVBARADDR (ACPU_CTRL_BASE + 0x158) 120 #define ACPU_SC_CPU1_CTRL (ACPU_CTRL_BASE + 0x200) 121 #define ACPU_SC_CPU1_STAT (ACPU_CTRL_BASE + 0x204) 122 #define ACPU_SC_CPU1_CLKEN (ACPU_CTRL_BASE + 0x208) 123 #define ACPU_SC_CPU1_CLK_STAT (ACPU_CTRL_BASE + 0x210) 124 #define ACPU_SC_CPU1_RSTEN (ACPU_CTRL_BASE + 0x214) 125 #define ACPU_SC_CPU1_RSTDIS (ACPU_CTRL_BASE + 0x218) 126 #define ACPU_SC_CPU1_MTCMOS_EN (ACPU_CTRL_BASE + 0x220) 127 #define ACPU_SC_CPU1_PW_ISODIS (ACPU_CTRL_BASE + 0x234) 128 #define ACPU_SC_CPU1_PW_ISO_STAT (ACPU_CTRL_BASE + 0x238) 129 #define ACPU_SC_CPU1_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x254) 130 #define ACPU_SC_CPU1_RVBARADDR (ACPU_CTRL_BASE + 0x258) 131 #define ACPU_SC_CPU2_CTRL (ACPU_CTRL_BASE + 0x300) 132 #define ACPU_SC_CPU2_STAT (ACPU_CTRL_BASE + 0x304) 133 #define ACPU_SC_CPU2_CLKEN (ACPU_CTRL_BASE + 0x308) 134 #define ACPU_SC_CPU2_CLK_STAT (ACPU_CTRL_BASE + 0x310) 135 #define ACPU_SC_CPU2_RSTEN (ACPU_CTRL_BASE + 0x314) 136 #define ACPU_SC_CPU2_RSTDIS (ACPU_CTRL_BASE + 0x318) 137 #define ACPU_SC_CPU2_MTCMOS_EN (ACPU_CTRL_BASE + 0x320) 138 #define ACPU_SC_CPU2_PW_ISODIS (ACPU_CTRL_BASE + 0x334) 139 #define ACPU_SC_CPU2_PW_ISO_STAT (ACPU_CTRL_BASE + 0x338) 140 #define ACPU_SC_CPU2_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x354) 141 #define ACPU_SC_CPU2_RVBARADDR (ACPU_CTRL_BASE + 0x358) 142 #define ACPU_SC_CPU3_CTRL (ACPU_CTRL_BASE + 0x400) 143 #define ACPU_SC_CPU3_STAT (ACPU_CTRL_BASE + 0x404) 144 #define ACPU_SC_CPU3_CLKEN (ACPU_CTRL_BASE + 0x408) 145 #define ACPU_SC_CPU3_CLK_STAT (ACPU_CTRL_BASE + 0x410) 146 #define ACPU_SC_CPU3_RSTEN (ACPU_CTRL_BASE + 0x414) 147 #define ACPU_SC_CPU3_RSTDIS (ACPU_CTRL_BASE + 0x418) 148 #define ACPU_SC_CPU3_MTCMOS_EN (ACPU_CTRL_BASE + 0x420) 149 #define ACPU_SC_CPU3_PW_ISODIS (ACPU_CTRL_BASE + 0x434) 150 #define ACPU_SC_CPU3_PW_ISO_STAT (ACPU_CTRL_BASE + 0x438) 151 #define ACPU_SC_CPU3_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x454) 152 #define ACPU_SC_CPU3_RVBARADDR (ACPU_CTRL_BASE + 0x458) 153 #define ACPU_SC_CPU4_CTRL (ACPU_CTRL_BASE + 0x500) 154 #define ACPU_SC_CPU4_STAT (ACPU_CTRL_BASE + 0x504) 155 #define ACPU_SC_CPU4_CLKEN (ACPU_CTRL_BASE + 0x508) 156 #define ACPU_SC_CPU4_CLK_STAT (ACPU_CTRL_BASE + 0x510) 157 #define ACPU_SC_CPU4_RSTEN (ACPU_CTRL_BASE + 0x514) 158 #define ACPU_SC_CPU4_RSTDIS (ACPU_CTRL_BASE + 0x518) 159 #define ACPU_SC_CPU4_MTCMOS_EN (ACPU_CTRL_BASE + 0x520) 160 #define ACPU_SC_CPU4_PW_ISODIS (ACPU_CTRL_BASE + 0x534) 161 #define ACPU_SC_CPU4_PW_ISO_STAT (ACPU_CTRL_BASE + 0x538) 162 #define ACPU_SC_CPU4_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x554) 163 #define ACPU_SC_CPU4_RVBARADDR (ACPU_CTRL_BASE + 0x558) 164 #define ACPU_SC_CPU5_CTRL (ACPU_CTRL_BASE + 0x600) 165 #define ACPU_SC_CPU5_STAT (ACPU_CTRL_BASE + 0x604) 166 #define ACPU_SC_CPU5_CLKEN (ACPU_CTRL_BASE + 0x608) 167 #define ACPU_SC_CPU5_CLK_STAT (ACPU_CTRL_BASE + 0x610) 168 #define ACPU_SC_CPU5_RSTEN (ACPU_CTRL_BASE + 0x614) 169 #define ACPU_SC_CPU5_RSTDIS (ACPU_CTRL_BASE + 0x618) 170 #define ACPU_SC_CPU5_MTCMOS_EN (ACPU_CTRL_BASE + 0x620) 171 #define ACPU_SC_CPU5_PW_ISODIS (ACPU_CTRL_BASE + 0x634) 172 #define ACPU_SC_CPU5_PW_ISO_STAT (ACPU_CTRL_BASE + 0x638) 173 #define ACPU_SC_CPU5_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x654) 174 #define ACPU_SC_CPU5_RVBARADDR (ACPU_CTRL_BASE + 0x658) 175 #define ACPU_SC_CPU6_CTRL (ACPU_CTRL_BASE + 0x700) 176 #define ACPU_SC_CPU6_STAT (ACPU_CTRL_BASE + 0x704) 177 #define ACPU_SC_CPU6_CLKEN (ACPU_CTRL_BASE + 0x708) 178 #define ACPU_SC_CPU6_CLK_STAT (ACPU_CTRL_BASE + 0x710) 179 #define ACPU_SC_CPU6_RSTEN (ACPU_CTRL_BASE + 0x714) 180 #define ACPU_SC_CPU6_RSTDIS (ACPU_CTRL_BASE + 0x718) 181 #define ACPU_SC_CPU6_MTCMOS_EN (ACPU_CTRL_BASE + 0x720) 182 #define ACPU_SC_CPU6_PW_ISODIS (ACPU_CTRL_BASE + 0x734) 183 #define ACPU_SC_CPU6_PW_ISO_STAT (ACPU_CTRL_BASE + 0x738) 184 #define ACPU_SC_CPU6_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x754) 185 #define ACPU_SC_CPU6_RVBARADDR (ACPU_CTRL_BASE + 0x758) 186 #define ACPU_SC_CPU7_CTRL (ACPU_CTRL_BASE + 0x800) 187 #define ACPU_SC_CPU7_STAT (ACPU_CTRL_BASE + 0x804) 188 #define ACPU_SC_CPU7_CLKEN (ACPU_CTRL_BASE + 0x808) 189 #define ACPU_SC_CPU7_CLK_STAT (ACPU_CTRL_BASE + 0x810) 190 #define ACPU_SC_CPU7_RSTEN (ACPU_CTRL_BASE + 0x814) 191 #define ACPU_SC_CPU7_RSTDIS (ACPU_CTRL_BASE + 0x818) 192 #define ACPU_SC_CPU7_MTCMOS_EN (ACPU_CTRL_BASE + 0x820) 193 #define ACPU_SC_CPU7_PW_ISODIS (ACPU_CTRL_BASE + 0x834) 194 #define ACPU_SC_CPU7_PW_ISO_STAT (ACPU_CTRL_BASE + 0x838) 195 #define ACPU_SC_CPU7_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x854) 196 #define ACPU_SC_CPU7_RVBARADDR (ACPU_CTRL_BASE + 0x858) 197 #define ACPU_SC_CPUx_CTRL(x) ((x < 8) ? (ACPU_SC_CPU0_CTRL + 0x100 * x) : ACPU_SC_CPU0_CTRL) 198 #define ACPU_SC_CPUx_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_STAT + 0x100 * x) : ACPU_SC_CPU0_STAT) 199 #define ACPU_SC_CPUx_CLKEN(x) ((x < 8) ? (ACPU_SC_CPU0_CLKEN + 0x100 * x) : ACPU_SC_CPU0_CLKEN) 200 #define ACPU_SC_CPUx_CLK_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_CLK_STAT + 0x100 * x) : ACPU_SC_CPU0_CLK_STAT) 201 #define ACPU_SC_CPUx_RSTEN(x) ((x < 8) ? (ACPU_SC_CPU0_RSTEN + 0x100 * x) : ACPU_SC_CPU0_RSTEN) 202 #define ACPU_SC_CPUx_RSTDIS(x) ((x < 8) ? (ACPU_SC_CPU0_RSTDIS + 0x100 * x) : ACPU_SC_CPU0_RSTDIS) 203 #define ACPU_SC_CPUx_MTCMOS_EN(x) ((x < 8) ? (ACPU_SC_CPU0_MTCMOS_EN + 0x100 * x) : ACPU_SC_CPU0_MTCMOS_EN) 204 #define ACPU_SC_CPUx_PW_ISODIS(x) ((x < 8) ? (ACPU_SC_CPU0_PW_ISODIS + 0x100 * x) : ACPU_SC_CPU0_PW_ISODIS) 205 #define ACPU_SC_CPUx_PW_ISO_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_PW_ISO_STAT + 0x100 * x) : ACPU_SC_CPU0_PW_ISO_STAT) 206 #define ACPU_SC_CPUx_MTCMOS_TIMER_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_MTCMOS_TIMER_STAT + 0x100 * x) : ACPU_SC_CPU0_MTCMOS_TIMER_STAT) 207 #define ACPU_SC_CPUx_RVBARADDR(x) ((x < 8) ? (ACPU_SC_CPU0_RVBARADDR + 0x100 * x) : ACPU_SC_CPU0_RVBARADDR) 208 209 #define ACPU_SC_CPU_STAT_CLKDIV_VD_MASK (3 << 20) 210 211 #define ACPU_SC_VD_CTRL_TUNE_EN_DIF (1 << 0) 212 #define ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT (0) 213 #define ACPU_SC_VD_CTRL_TUNE (1 << 1) 214 #define ACPU_SC_VD_CTRL_TUNE_SHIFT (1) 215 #define ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF (1 << 7) 216 #define ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT (7) 217 #define ACPU_SC_VD_CTRL_CALIBRATE_EN_INI (1 << 8) 218 #define ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT (8) 219 #define ACPU_SC_VD_CTRL_CLK_DIS_CNT_CLR (1 << 9) 220 #define ACPU_SC_VD_CTRL_CLK_DIS_CNT_CLR_SHIFT (9) 221 #define ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN (1 << 10) 222 #define ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT (10) 223 #define ACPU_SC_VD_CTRL_TUNE_EN_INT (1 << 11) 224 #define ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT (11) 225 #define ACPU_SC_VD_CTRL_SHIFT_TABLE0 (1 << 12) 226 #define ACPU_SC_VD_CTRL_SHIFT_TABLE0_MASK (0xf << 12) 227 #define ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT (12) 228 #define ACPU_SC_VD_CTRL_SHIFT_TABLE1 (1 << 16) 229 #define ACPU_SC_VD_CTRL_SHIFT_TABLE1_MASK (0xf << 16) 230 #define ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT (16) 231 #define ACPU_SC_VD_CTRL_SHIFT_TABLE2 (1 << 20) 232 #define ACPU_SC_VD_CTRL_SHIFT_TABLE2_MASK (0xf << 20) 233 #define ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT (20) 234 #define ACPU_SC_VD_CTRL_SHIFT_TABLE3 (1 << 24) 235 #define ACPU_SC_VD_CTRL_SHIFT_TABLE3_MASK (0xf << 24) 236 #define ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT (24) 237 #define ACPU_SC_VD_CTRL_FORCE_CLK_EN (1 << 28) 238 #define ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT (28) 239 #define ACPU_SC_VD_CTRL_DIV_EN_DIF (1 << 29) 240 #define ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT (29) 241 242 #define ACPU_SC_VD_SHIFT_TABLE_TUNE_VAL \ 243 ((0x1 << ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT) | \ 244 (0x3 << ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT) | \ 245 (0x5 << ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT) | \ 246 (0x6 << ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT) | \ 247 (0x7 << ACPU_SC_VD_CTRL_TUNE_SHIFT)) 248 249 #define ACPU_SC_VD_SHIFT_TABLE_TUNE_MASK \ 250 ((0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT) | \ 251 (0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT) | \ 252 (0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT) | \ 253 (0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT) | \ 254 (0x3F << ACPU_SC_VD_CTRL_TUNE_SHIFT)) 255 256 #define ACPU_SC_VD_HPM_CTRL_OSC_DIV (1 << 0) 257 #define ACPU_SC_VD_HPM_CTRL_OSC_DIV_SHIFT (0) 258 #define ACPU_SC_VD_HPM_CTRL_OSC_DIV_MASK (0x000000FF) 259 #define ACPU_SC_VD_HPM_CTRL_DLY_EXP (1 << 8) 260 #define ACPU_SC_VD_HPM_CTRL_DLY_EXP_SHIFT (8) 261 #define ACPU_SC_VD_HPM_CTRL_DLY_EXP_MASK (0x001FFF00) 262 263 #define HPM_OSC_DIV_VAL \ 264 (0x56 << ACPU_SC_VD_HPM_CTRL_OSC_DIV_SHIFT) 265 #define HPM_OSC_DIV_MASK \ 266 (ACPU_SC_VD_HPM_CTRL_OSC_DIV_MASK) 267 268 #define HPM_DLY_EXP_VAL \ 269 (0xC7A << ACPU_SC_VD_HPM_CTRL_DLY_EXP_SHIFT) 270 #define HPM_DLY_EXP_MASK \ 271 (ACPU_SC_VD_HPM_CTRL_DLY_EXP_MASK) 272 273 #define ACPU_SC_VD_EN_ASIC_VAL \ 274 ((0x0 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \ 275 (0x0 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \ 276 (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \ 277 (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \ 278 (0X0 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \ 279 (0X0 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \ 280 (0x0 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT)) 281 282 #define ACPU_SC_VD_EN_SFT_VAL \ 283 ((0x0 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \ 284 (0x0 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \ 285 (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \ 286 (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \ 287 (0x0 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \ 288 (0x0 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \ 289 (0x0 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT)) 290 291 #define ACPU_SC_VD_EN_MASK \ 292 ((0x1 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \ 293 (0x1 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \ 294 (0x1 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \ 295 (0x1 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \ 296 (0x1 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \ 297 (0x1 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \ 298 (0x1 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT)) 299 300 #endif /* __HI6220_REGS_ACPU_H__ */ 301
