1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <debug.h> 8 #include <mmio.h> 9 #include <pmc.h> 10 #include <tegra_def.h> 11 12 #define SB_CSR 0x0 13 #define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) 14 15 /* CPU reset vector */ 16 #define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */ 17 #define SB_AA64_RESET_HI 0x34 /* width = 11:0 */ 18 19 extern void tegra_secure_entrypoint(void); 20 21 /******************************************************************************* 22 * Setup secondary CPU vectors 23 ******************************************************************************/ 24 void plat_secondary_setup(void) 25 { 26 uint32_t val; 27 uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; 28 29 INFO("Setting up secondary CPU boot\n"); 30 31 /* setup secondary CPU vector */ 32 mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW, 33 (reset_addr & 0xFFFFFFFF) | 1); 34 val = reset_addr >> 32; 35 mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF); 36 37 /* configure PMC */ 38 tegra_pmc_cpu_setup(reset_addr); 39 tegra_pmc_lock_cpu_vectors(); 40 } 41
