1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLAT_DEF_H__ 8 #define __PLAT_DEF_H__ 9 10 #define MAJOR_VERSION (1) 11 #define MINOR_VERSION (2) 12 13 #define SIZE_K(n) ((n) * 1024) 14 15 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 16 #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 17 18 #define UART2_BASE 0xff130000 19 #define UART2_SIZE SIZE_K(64) 20 21 #define PMU_BASE 0xff140000 22 #define PMU_SIZE SIZE_K(64) 23 24 #define SGRF_BASE 0xff0d0000 25 #define SGRF_SIZE SIZE_K(64) 26 27 #define CRU_BASE 0xff440000 28 #define CRU_SIZE SIZE_K(64) 29 30 #define GRF_BASE 0xff100000 31 #define GRF_SIZE SIZE_K(64) 32 33 #define GPIO0_BASE 0xff210000 34 #define GPIO0_SIZE SIZE_K(32) 35 36 #define GPIO1_BASE 0xff220000 37 #define GPIO1_SIZE SIZE_K(32) 38 39 #define GPIO2_BASE 0xff230000 40 #define GPIO2_SIZE SIZE_K(64) 41 42 #define GPIO3_BASE 0xff240000 43 #define GPIO3_SIZE SIZE_K(64) 44 45 #define STIME_BASE 0xff1d0000 46 #define STIME_SIZE SIZE_K(64) 47 48 #define INTMEM_BASE 0xff090000 49 #define INTMEM_SIZE SIZE_K(32) 50 51 #define SRAM_LDS_BASE (INTMEM_BASE + SIZE_K(4)) 52 #define SRAM_LDS_SIZE (INTMEM_SIZE - SIZE_K(4)) 53 54 #define PMUSRAM_BASE INTMEM_BASE 55 #define PMUSRAM_SIZE SIZE_K(4) 56 #define PMUSRAM_RSIZE SIZE_K(4) 57 58 #define VOP_BASE 0xff370000 59 #define VOP_SIZE SIZE_K(16) 60 61 #define DDR_PHY_BASE 0xff400000 62 #define DDR_PHY_SIZE SIZE_K(4) 63 64 #define SERVER_MSCH_BASE 0xff720000 65 #define SERVER_MSCH_SIZE SIZE_K(4) 66 67 #define DDR_UPCTL_BASE 0xff780000 68 #define DDR_UPCTL_SIZE SIZE_K(12) 69 70 #define DDR_MONITOR_BASE 0xff790000 71 #define DDR_MONITOR_SIZE SIZE_K(4) 72 73 #define FIREWALL_DDR_BASE 0xff7c0000 74 #define FIREWALL_DDR_SIZE SIZE_K(64) 75 76 #define FIREWALL_CFG_BASE 0xff7d0000 77 #define FIREWALL_CFG_SIZE SIZE_K(64) 78 79 #define GIC400_BASE 0xff810000 80 #define GIC400_SIZE SIZE_K(64) 81 82 #define DDR_GRF_BASE 0xff798000 83 #define DDR_GRF_SIZE SIZE_K(16) 84 85 #define PWM_BASE 0xff1b0000 86 #define PWM_SIZE SIZE_K(64) 87 88 #define DDR_PARAM_BASE 0x02000000 89 #define DDR_PARAM_SIZE SIZE_K(4) 90 91 #define EFUSE8_BASE 0xff260000 92 #define EFUSE8_SIZE SIZE_K(4) 93 94 #define EFUSE32_BASE 0xff0b0000 95 #define EFUSE32_SIZE SIZE_K(4) 96 97 /************************************************************************** 98 * UART related constants 99 **************************************************************************/ 100 #define RK3328_UART2_BASE UART2_BASE 101 #define RK3328_BAUDRATE 1500000 102 #define RK3328_UART_CLOCK 24000000 103 104 /****************************************************************************** 105 * System counter frequency related constants 106 ******************************************************************************/ 107 #define SYS_COUNTER_FREQ_IN_TICKS 24000000U 108 #define SYS_COUNTER_FREQ_IN_MHZ 24 109 110 /****************************************************************************** 111 * GIC-400 & interrupt handling related constants 112 ******************************************************************************/ 113 114 /* Base rk_platform compatible GIC memory map */ 115 #define RK3328_GICD_BASE (GIC400_BASE + 0x1000) 116 #define RK3328_GICC_BASE (GIC400_BASE + 0x2000) 117 #define RK3328_GICR_BASE 0 /* no GICR in GIC-400 */ 118 119 /****************************************************************************** 120 * sgi, ppi 121 ******************************************************************************/ 122 #define RK_IRQ_SEC_PHY_TIMER 29 123 124 #define RK_IRQ_SEC_SGI_0 8 125 #define RK_IRQ_SEC_SGI_1 9 126 #define RK_IRQ_SEC_SGI_2 10 127 #define RK_IRQ_SEC_SGI_3 11 128 #define RK_IRQ_SEC_SGI_4 12 129 #define RK_IRQ_SEC_SGI_5 13 130 #define RK_IRQ_SEC_SGI_6 14 131 #define RK_IRQ_SEC_SGI_7 15 132 133 /* 134 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 135 * terminology. On a GICv2 system or mode, the lists will be merged and treated 136 * as Group 0 interrupts. 137 */ 138 #define RK_G1S_IRQS RK_IRQ_SEC_PHY_TIMER, RK_IRQ_SEC_SGI_6 139 140 #define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/ 141 #define SHARE_MEM_PAGE_NUM 15 142 #define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) 143 144 #endif /* __PLAT_DEF_H__ */ 145
