1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PMU_BITS_H__ 8 #define __PMU_BITS_H__ 9 10 enum pmu_powerdomain_id { 11 PD_CPUL0 = 0, 12 PD_CPUL1, 13 PD_CPUL2, 14 PD_CPUL3, 15 PD_CPUB0, 16 PD_CPUB1, 17 PD_SCUL, 18 PD_SCUB, 19 PD_TCPD0, 20 PD_TCPD1, 21 PD_CCI, 22 PD_PERILP, 23 PD_PERIHP, 24 PD_CENTER, 25 PD_VIO, 26 PD_GPU, 27 PD_VCODEC, 28 PD_VDU, 29 PD_RGA, 30 PD_IEP, 31 PD_VO, 32 PD_ISP0 = 22, 33 PD_ISP1, 34 PD_HDCP, 35 PD_GMAC, 36 PD_EMMC, 37 PD_USB3, 38 PD_EDP, 39 PD_GIC, 40 PD_SD, 41 PD_SDIOAUDIO, 42 PD_END 43 }; 44 45 enum powerdomain_state { 46 PMU_POWER_ON = 0, 47 PMU_POWER_OFF, 48 }; 49 50 enum pmu_bus_id { 51 BUS_ID_GPU = 0, 52 BUS_ID_PERILP, 53 BUS_ID_PERIHP, 54 BUS_ID_VCODEC, 55 BUS_ID_VDU, 56 BUS_ID_RGA, 57 BUS_ID_IEP, 58 BUS_ID_VOPB, 59 BUS_ID_VOPL, 60 BUS_ID_ISP0, 61 BUS_ID_ISP1, 62 BUS_ID_HDCP, 63 BUS_ID_USB3, 64 BUS_ID_PERILPM0, 65 BUS_ID_CENTER, 66 BUS_ID_CCIM0, 67 BUS_ID_CCIM1, 68 BUS_ID_VIO, 69 BUS_ID_MSCH0, 70 BUS_ID_MSCH1, 71 BUS_ID_ALIVE, 72 BUS_ID_PMU, 73 BUS_ID_EDP, 74 BUS_ID_GMAC, 75 BUS_ID_EMMC, 76 BUS_ID_CENTER1, 77 BUS_ID_PMUM0, 78 BUS_ID_GIC, 79 BUS_ID_SD, 80 BUS_ID_SDIOAUDIO, 81 }; 82 83 enum pmu_bus_state { 84 BUS_ACTIVE, 85 BUS_IDLE, 86 }; 87 88 /* pmu_cpuapm bit */ 89 enum pmu_cores_pm_by_wfi { 90 core_pm_en = 0, 91 core_pm_int_wakeup_en, 92 core_pm_resv, 93 core_pm_sft_wakeup_en 94 }; 95 96 enum pmu_wkup_cfg0 { 97 PMU_GPIO0A_POSE_WKUP_EN = 0, 98 PMU_GPIO0B_POSE_WKUP_EN = 8, 99 PMU_GPIO0C_POSE_WKUP_EN = 16, 100 PMU_GPIO0D_POSE_WKUP_EN = 24, 101 }; 102 103 enum pmu_wkup_cfg1 { 104 PMU_GPIO0A_NEGEDGE_WKUP_EN = 0, 105 PMU_GPIO0B_NEGEDGE_WKUP_EN = 7, 106 PMU_GPIO0C_NEGEDGE_WKUP_EN = 16, 107 PMU_GPIO0D_NEGEDGE_WKUP_EN = 24, 108 }; 109 110 enum pmu_wkup_cfg2 { 111 PMU_GPIO1A_POSE_WKUP_EN = 0, 112 PMU_GPIO1B_POSE_WKUP_EN = 7, 113 PMU_GPIO1C_POSE_WKUP_EN = 16, 114 PMU_GPIO1D_POSE_WKUP_EN = 24, 115 }; 116 117 enum pmu_wkup_cfg3 { 118 PMU_GPIO1A_NEGEDGE_WKUP_EN = 0, 119 PMU_GPIO1B_NEGEDGE_WKUP_EN = 7, 120 PMU_GPIO1C_NEGEDGE_WKUP_EN = 16, 121 PMU_GPIO1D_NEGEDGE_WKUP_EN = 24, 122 }; 123 124 /* pmu_wkup_cfg4 */ 125 enum pmu_wkup_cfg4 { 126 PMU_CLUSTER_L_WKUP_EN = 0, 127 PMU_CLUSTER_B_WKUP_EN, 128 PMU_GPIO_WKUP_EN, 129 PMU_SDIO_WKUP_EN, 130 131 PMU_SDMMC_WKUP_EN, 132 PMU_TIMER_WKUP_EN = 6, 133 PMU_USBDEV_WKUP_EN, 134 135 PMU_SFT_WKUP_EN, 136 PMU_M0_WDT_WKUP_EN, 137 PMU_TIMEOUT_WKUP_EN, 138 PMU_PWM_WKUP_EN, 139 140 PMU_PCIE_WKUP_EN = 13, 141 }; 142 143 enum pmu_pwrdn_con { 144 PMU_A53_L0_PWRDWN_EN = 0, 145 PMU_A53_L1_PWRDWN_EN, 146 PMU_A53_L2_PWRDWN_EN, 147 PMU_A53_L3_PWRDWN_EN, 148 149 PMU_A72_B0_PWRDWN_EN, 150 PMU_A72_B1_PWRDWN_EN, 151 PMU_SCU_L_PWRDWN_EN, 152 PMU_SCU_B_PWRDWN_EN, 153 154 PMU_TCPD0_PWRDWN_EN, 155 PMU_TCPD1_PWRDWN_EN, 156 PMU_CCI_PWRDWN_EN, 157 PMU_PERILP_PWRDWN_EN, 158 159 PMU_PERIHP_PWRDWN_EN, 160 PMU_CENTER_PWRDWN_EN, 161 PMU_VIO_PWRDWN_EN, 162 PMU_GPU_PWRDWN_EN, 163 164 PMU_VCODEC_PWRDWN_EN, 165 PMU_VDU_PWRDWN_EN, 166 PMU_RGA_PWRDWN_EN, 167 PMU_IEP_PWRDWN_EN, 168 169 PMU_VO_PWRDWN_EN, 170 PMU_ISP0_PWRDWN_EN = 22, 171 PMU_ISP1_PWRDWN_EN, 172 173 PMU_HDCP_PWRDWN_EN, 174 PMU_GMAC_PWRDWN_EN, 175 PMU_EMMC_PWRDWN_EN, 176 PMU_USB3_PWRDWN_EN, 177 178 PMU_EDP_PWRDWN_EN, 179 PMU_GIC_PWRDWN_EN, 180 PMU_SD_PWRDWN_EN, 181 PMU_SDIOAUDIO_PWRDWN_EN, 182 }; 183 184 enum pmu_pwrdn_st { 185 PMU_A53_L0_PWRDWN_ST = 0, 186 PMU_A53_L1_PWRDWN_ST, 187 PMU_A53_L2_PWRDWN_ST, 188 PMU_A53_L3_PWRDWN_ST, 189 190 PMU_A72_B0_PWRDWN_ST, 191 PMU_A72_B1_PWRDWN_ST, 192 PMU_SCU_L_PWRDWN_ST, 193 PMU_SCU_B_PWRDWN_ST, 194 195 PMU_TCPD0_PWRDWN_ST, 196 PMU_TCPD1_PWRDWN_ST, 197 PMU_CCI_PWRDWN_ST, 198 PMU_PERILP_PWRDWN_ST, 199 200 PMU_PERIHP_PWRDWN_ST, 201 PMU_CENTER_PWRDWN_ST, 202 PMU_VIO_PWRDWN_ST, 203 PMU_GPU_PWRDWN_ST, 204 205 PMU_VCODEC_PWRDWN_ST, 206 PMU_VDU_PWRDWN_ST, 207 PMU_RGA_PWRDWN_ST, 208 PMU_IEP_PWRDWN_ST, 209 210 PMU_VO_PWRDWN_ST, 211 PMU_ISP0_PWRDWN_ST = 22, 212 PMU_ISP1_PWRDWN_ST, 213 214 PMU_HDCP_PWRDWN_ST, 215 PMU_GMAC_PWRDWN_ST, 216 PMU_EMMC_PWRDWN_ST, 217 PMU_USB3_PWRDWN_ST, 218 219 PMU_EDP_PWRDWN_ST, 220 PMU_GIC_PWRDWN_ST, 221 PMU_SD_PWRDWN_ST, 222 PMU_SDIOAUDIO_PWRDWN_ST, 223 224 }; 225 226 enum pmu_pll_con { 227 PMU_PLL_PD_CFG = 0, 228 PMU_SFT_PLL_PD = 8, 229 }; 230 231 enum pmu_pwermode_con { 232 PMU_PWR_MODE_EN = 0, 233 PMU_WKUP_RST_EN, 234 PMU_INPUT_CLAMP_EN, 235 PMU_OSC_DIS, 236 237 PMU_ALIVE_USE_LF, 238 PMU_PMU_USE_LF, 239 PMU_POWER_OFF_REQ_CFG, 240 PMU_CHIP_PD_EN, 241 242 PMU_PLL_PD_EN, 243 PMU_CPU0_PD_EN, 244 PMU_L2_FLUSH_EN, 245 PMU_L2_IDLE_EN, 246 247 PMU_SCU_PD_EN, 248 PMU_CCI_PD_EN, 249 PMU_PERILP_PD_EN, 250 PMU_CENTER_PD_EN, 251 252 PMU_SREF0_ENTER_EN, 253 PMU_DDRC0_GATING_EN, 254 PMU_DDRIO0_RET_EN, 255 PMU_DDRIO0_RET_DE_REQ, 256 257 PMU_SREF1_ENTER_EN, 258 PMU_DDRC1_GATING_EN, 259 PMU_DDRIO1_RET_EN, 260 PMU_DDRIO1_RET_DE_REQ, 261 262 PMU_CLK_CENTER_SRC_GATE_EN = 26, 263 PMU_CLK_PERILP_SRC_GATE_EN, 264 265 PMU_CLK_CORE_SRC_GATE_EN, 266 PMU_DDRIO_RET_HW_DE_REQ, 267 PMU_SLP_OUTPUT_CFG, 268 PMU_MAIN_CLUSTER, 269 }; 270 271 enum pmu_sft_con { 272 PMU_WKUP_SFT = 0, 273 PMU_INPUT_CLAMP_CFG, 274 PMU_OSC_DIS_CFG, 275 PMU_PMU_LF_EN_CFG, 276 277 PMU_ALIVE_LF_EN_CFG, 278 PMU_24M_EN_CFG, 279 PMU_DBG_PWRUP_L0_CFG, 280 PMU_WKUP_SFT_M0, 281 282 PMU_DDRCTL0_C_SYSREQ_CFG, 283 PMU_DDR0_IO_RET_CFG, 284 285 PMU_DDRCTL1_C_SYSREQ_CFG = 12, 286 PMU_DDR1_IO_RET_CFG, 287 DBG_PWRUP_B0_CFG = 15, 288 289 DBG_NOPWERDWN_L0_EN, 290 DBG_NOPWERDWN_L1_EN, 291 DBG_NOPWERDWN_L2_EN, 292 DBG_NOPWERDWN_L3_EN, 293 294 DBG_PWRUP_REQ_L_EN = 20, 295 CLUSTER_L_CLK_SRC_GATING_CFG, 296 L2_FLUSH_REQ_CLUSTER_L, 297 ACINACTM_CLUSTER_L_CFG, 298 299 DBG_NO_PWERDWN_B0_EN, 300 DBG_NO_PWERDWN_B1_EN, 301 302 DBG_PWRUP_REQ_B_EN = 28, 303 CLUSTER_B_CLK_SRC_GATING_CFG, 304 L2_FLUSH_REQ_CLUSTER_B, 305 ACINACTM_CLUSTER_B_CFG, 306 }; 307 308 enum pmu_int_con { 309 PMU_PMU_INT_EN = 0, 310 PMU_PWRMD_WKUP_INT_EN, 311 PMU_WKUP_GPIO0_NEG_INT_EN, 312 PMU_WKUP_GPIO0_POS_INT_EN, 313 PMU_WKUP_GPIO1_NEG_INT_EN, 314 PMU_WKUP_GPIO1_POS_INT_EN, 315 }; 316 317 enum pmu_int_st { 318 PMU_PWRMD_WKUP_INT_ST = 1, 319 PMU_WKUP_GPIO0_NEG_INT_ST, 320 PMU_WKUP_GPIO0_POS_INT_ST, 321 PMU_WKUP_GPIO1_NEG_INT_ST, 322 PMU_WKUP_GPIO1_POS_INT_ST, 323 }; 324 325 enum pmu_gpio0_pos_int_con { 326 PMU_GPIO0A_POS_INT_EN = 0, 327 PMU_GPIO0B_POS_INT_EN = 8, 328 PMU_GPIO0C_POS_INT_EN = 16, 329 PMU_GPIO0D_POS_INT_EN = 24, 330 }; 331 332 enum pmu_gpio0_neg_int_con { 333 PMU_GPIO0A_NEG_INT_EN = 0, 334 PMU_GPIO0B_NEG_INT_EN = 8, 335 PMU_GPIO0C_NEG_INT_EN = 16, 336 PMU_GPIO0D_NEG_INT_EN = 24, 337 }; 338 339 enum pmu_gpio1_pos_int_con { 340 PMU_GPIO1A_POS_INT_EN = 0, 341 PMU_GPIO1B_POS_INT_EN = 8, 342 PMU_GPIO1C_POS_INT_EN = 16, 343 PMU_GPIO1D_POS_INT_EN = 24, 344 }; 345 346 enum pmu_gpio1_neg_int_con { 347 PMU_GPIO1A_NEG_INT_EN = 0, 348 PMU_GPIO1B_NEG_INT_EN = 8, 349 PMU_GPIO1C_NEG_INT_EN = 16, 350 PMU_GPIO1D_NEG_INT_EN = 24, 351 }; 352 353 enum pmu_gpio0_pos_int_st { 354 PMU_GPIO0A_POS_INT_ST = 0, 355 PMU_GPIO0B_POS_INT_ST = 8, 356 PMU_GPIO0C_POS_INT_ST = 16, 357 PMU_GPIO0D_POS_INT_ST = 24, 358 }; 359 360 enum pmu_gpio0_neg_int_st { 361 PMU_GPIO0A_NEG_INT_ST = 0, 362 PMU_GPIO0B_NEG_INT_ST = 8, 363 PMU_GPIO0C_NEG_INT_ST = 16, 364 PMU_GPIO0D_NEG_INT_ST = 24, 365 }; 366 367 enum pmu_gpio1_pos_int_st { 368 PMU_GPIO1A_POS_INT_ST = 0, 369 PMU_GPIO1B_POS_INT_ST = 8, 370 PMU_GPIO1C_POS_INT_ST = 16, 371 PMU_GPIO1D_POS_INT_ST = 24, 372 }; 373 374 enum pmu_gpio1_neg_int_st { 375 PMU_GPIO1A_NEG_INT_ST = 0, 376 PMU_GPIO1B_NEG_INT_ST = 8, 377 PMU_GPIO1C_NEG_INT_ST = 16, 378 PMU_GPIO1D_NEG_INT_ST = 24, 379 }; 380 381 /* pmu power down configure register 0x0050 */ 382 enum pmu_pwrdn_inten { 383 PMU_A53_L0_PWR_SWITCH_INT_EN = 0, 384 PMU_A53_L1_PWR_SWITCH_INT_EN, 385 PMU_A53_L2_PWR_SWITCH_INT_EN, 386 PMU_A53_L3_PWR_SWITCH_INT_EN, 387 388 PMU_A72_B0_PWR_SWITCH_INT_EN, 389 PMU_A72_B1_PWR_SWITCH_INT_EN, 390 PMU_SCU_L_PWR_SWITCH_INT_EN, 391 PMU_SCU_B_PWR_SWITCH_INT_EN, 392 393 PMU_TCPD0_PWR_SWITCH_INT_EN, 394 PMU_TCPD1_PWR_SWITCH_INT_EN, 395 PMU_CCI_PWR_SWITCH_INT_EN, 396 PMU_PERILP_PWR_SWITCH_INT_EN, 397 398 PMU_PERIHP_PWR_SWITCH_INT_EN, 399 PMU_CENTER_PWR_SWITCH_INT_EN, 400 PMU_VIO_PWR_SWITCH_INT_EN, 401 PMU_GPU_PWR_SWITCH_INT_EN, 402 403 PMU_VCODEC_PWR_SWITCH_INT_EN, 404 PMU_VDU_PWR_SWITCH_INT_EN, 405 PMU_RGA_PWR_SWITCH_INT_EN, 406 PMU_IEP_PWR_SWITCH_INT_EN, 407 408 PMU_VO_PWR_SWITCH_INT_EN, 409 PMU_ISP0_PWR_SWITCH_INT_EN = 22, 410 PMU_ISP1_PWR_SWITCH_INT_EN, 411 412 PMU_HDCP_PWR_SWITCH_INT_EN, 413 PMU_GMAC_PWR_SWITCH_INT_EN, 414 PMU_EMMC_PWR_SWITCH_INT_EN, 415 PMU_USB3_PWR_SWITCH_INT_EN, 416 417 PMU_EDP_PWR_SWITCH_INT_EN, 418 PMU_GIC_PWR_SWITCH_INT_EN, 419 PMU_SD_PWR_SWITCH_INT_EN, 420 PMU_SDIOAUDIO_PWR_SWITCH_INT_EN, 421 }; 422 423 enum pmu_wkup_status { 424 PMU_WKUP_BY_CLSTER_L_INT = 0, 425 PMU_WKUP_BY_CLSTER_b_INT, 426 PMU_WKUP_BY_GPIO_INT, 427 PMU_WKUP_BY_SDIO_DET, 428 429 PMU_WKUP_BY_SDMMC_DET, 430 PMU_WKUP_BY_TIMER = 6, 431 PMU_WKUP_BY_USBDEV_DET, 432 433 PMU_WKUP_BY_M0_SFT, 434 PMU_WKUP_BY_M0_WDT_INT, 435 PMU_WKUP_BY_TIMEOUT, 436 PMU_WKUP_BY_PWM, 437 438 PMU_WKUP_BY_PCIE = 13, 439 }; 440 441 enum pmu_bus_clr { 442 PMU_CLR_GPU = 0, 443 PMU_CLR_PERILP, 444 PMU_CLR_PERIHP, 445 PMU_CLR_VCODEC, 446 447 PMU_CLR_VDU, 448 PMU_CLR_RGA, 449 PMU_CLR_IEP, 450 PMU_CLR_VOPB, 451 452 PMU_CLR_VOPL, 453 PMU_CLR_ISP0, 454 PMU_CLR_ISP1, 455 PMU_CLR_HDCP, 456 457 PMU_CLR_USB3, 458 PMU_CLR_PERILPM0, 459 PMU_CLR_CENTER, 460 PMU_CLR_CCIM1, 461 462 PMU_CLR_CCIM0, 463 PMU_CLR_VIO, 464 PMU_CLR_MSCH0, 465 PMU_CLR_MSCH1, 466 467 PMU_CLR_ALIVE, 468 PMU_CLR_PMU, 469 PMU_CLR_EDP, 470 PMU_CLR_GMAC, 471 472 PMU_CLR_EMMC, 473 PMU_CLR_CENTER1, 474 PMU_CLR_PMUM0, 475 PMU_CLR_GIC, 476 477 PMU_CLR_SD, 478 PMU_CLR_SDIOAUDIO, 479 }; 480 481 /* PMU bus idle request register */ 482 enum pmu_bus_idle_req { 483 PMU_IDLE_REQ_GPU = 0, 484 PMU_IDLE_REQ_PERILP, 485 PMU_IDLE_REQ_PERIHP, 486 PMU_IDLE_REQ_VCODEC, 487 488 PMU_IDLE_REQ_VDU, 489 PMU_IDLE_REQ_RGA, 490 PMU_IDLE_REQ_IEP, 491 PMU_IDLE_REQ_VOPB, 492 493 PMU_IDLE_REQ_VOPL, 494 PMU_IDLE_REQ_ISP0, 495 PMU_IDLE_REQ_ISP1, 496 PMU_IDLE_REQ_HDCP, 497 498 PMU_IDLE_REQ_USB3, 499 PMU_IDLE_REQ_PERILPM0, 500 PMU_IDLE_REQ_CENTER, 501 PMU_IDLE_REQ_CCIM0, 502 503 PMU_IDLE_REQ_CCIM1, 504 PMU_IDLE_REQ_VIO, 505 PMU_IDLE_REQ_MSCH0, 506 PMU_IDLE_REQ_MSCH1, 507 508 PMU_IDLE_REQ_ALIVE, 509 PMU_IDLE_REQ_PMU, 510 PMU_IDLE_REQ_EDP, 511 PMU_IDLE_REQ_GMAC, 512 513 PMU_IDLE_REQ_EMMC, 514 PMU_IDLE_REQ_CENTER1, 515 PMU_IDLE_REQ_PMUM0, 516 PMU_IDLE_REQ_GIC, 517 518 PMU_IDLE_REQ_SD, 519 PMU_IDLE_REQ_SDIOAUDIO, 520 }; 521 522 /* pmu bus idle status register */ 523 enum pmu_bus_idle_st { 524 PMU_IDLE_ST_GPU = 0, 525 PMU_IDLE_ST_PERILP, 526 PMU_IDLE_ST_PERIHP, 527 PMU_IDLE_ST_VCODEC, 528 529 PMU_IDLE_ST_VDU, 530 PMU_IDLE_ST_RGA, 531 PMU_IDLE_ST_IEP, 532 PMU_IDLE_ST_VOPB, 533 534 PMU_IDLE_ST_VOPL, 535 PMU_IDLE_ST_ISP0, 536 PMU_IDLE_ST_ISP1, 537 PMU_IDLE_ST_HDCP, 538 539 PMU_IDLE_ST_USB3, 540 PMU_IDLE_ST_PERILPM0, 541 PMU_IDLE_ST_CENTER, 542 PMU_IDLE_ST_CCIM0, 543 544 PMU_IDLE_ST_CCIM1, 545 PMU_IDLE_ST_VIO, 546 PMU_IDLE_ST_MSCH0, 547 PMU_IDLE_ST_MSCH1, 548 549 PMU_IDLE_ST_ALIVE, 550 PMU_IDLE_ST_PMU, 551 PMU_IDLE_ST_EDP, 552 PMU_IDLE_ST_GMAC, 553 554 PMU_IDLE_ST_EMMC, 555 PMU_IDLE_ST_CENTER1, 556 PMU_IDLE_ST_PMUM0, 557 PMU_IDLE_ST_GIC, 558 559 PMU_IDLE_ST_SD, 560 PMU_IDLE_ST_SDIOAUDIO, 561 }; 562 563 enum pmu_bus_idle_ack { 564 PMU_IDLE_ACK_GPU = 0, 565 PMU_IDLE_ACK_PERILP, 566 PMU_IDLE_ACK_PERIHP, 567 PMU_IDLE_ACK_VCODEC, 568 569 PMU_IDLE_ACK_VDU, 570 PMU_IDLE_ACK_RGA, 571 PMU_IDLE_ACK_IEP, 572 PMU_IDLE_ACK_VOPB, 573 574 PMU_IDLE_ACK_VOPL, 575 PMU_IDLE_ACK_ISP0, 576 PMU_IDLE_ACK_ISP1, 577 PMU_IDLE_ACK_HDCP, 578 579 PMU_IDLE_ACK_USB3, 580 PMU_IDLE_ACK_PERILPM0, 581 PMU_IDLE_ACK_CENTER, 582 PMU_IDLE_ACK_CCIM0, 583 584 PMU_IDLE_ACK_CCIM1, 585 PMU_IDLE_ACK_VIO, 586 PMU_IDLE_ACK_MSCH0, 587 PMU_IDLE_ACK_MSCH1, 588 589 PMU_IDLE_ACK_ALIVE, 590 PMU_IDLE_ACK_PMU, 591 PMU_IDLE_ACK_EDP, 592 PMU_IDLE_ACK_GMAC, 593 594 PMU_IDLE_ACK_EMMC, 595 PMU_IDLE_ACK_CENTER1, 596 PMU_IDLE_ACK_PMUM0, 597 PMU_IDLE_ACK_GIC, 598 599 PMU_IDLE_ACK_SD, 600 PMU_IDLE_ACK_SDIOAUDIO, 601 }; 602 603 enum pmu_cci500_con { 604 PMU_PREQ_CCI500_CFG_SW = 0, 605 PMU_CLR_PREQ_CCI500_HW, 606 PMU_PSTATE_CCI500_0, 607 PMU_PSTATE_CCI500_1, 608 609 PMU_PSTATE_CCI500_2, 610 PMU_QREQ_CCI500_CFG_SW, 611 PMU_CLR_QREQ_CCI500_HW, 612 PMU_QGATING_CCI500_CFG, 613 614 PMU_PREQ_CCI500_CFG_SW_WMSK = 16, 615 PMU_CLR_PREQ_CCI500_HW_WMSK, 616 PMU_PSTATE_CCI500_0_WMSK, 617 PMU_PSTATE_CCI500_1_WMSK, 618 619 PMU_PSTATE_CCI500_2_WMSK, 620 PMU_QREQ_CCI500_CFG_SW_WMSK, 621 PMU_CLR_QREQ_CCI500_HW_WMSK, 622 PMU_QGATING_CCI500_CFG_WMSK, 623 }; 624 625 enum pmu_adb400_con { 626 PMU_PWRDWN_REQ_CXCS_SW = 0, 627 PMU_PWRDWN_REQ_CORE_L_SW, 628 PMU_PWRDWN_REQ_CORE_L_2GIC_SW, 629 PMU_PWRDWN_REQ_GIC2_CORE_L_SW, 630 631 PMU_PWRDWN_REQ_CORE_B_SW, 632 PMU_PWRDWN_REQ_CORE_B_2GIC_SW, 633 PMU_PWRDWN_REQ_GIC2_CORE_B_SW, 634 635 PMU_CLR_CXCS_HW = 8, 636 PMU_CLR_CORE_L_HW, 637 PMU_CLR_CORE_L_2GIC_HW, 638 PMU_CLR_GIC2_CORE_L_HW, 639 640 PMU_CLR_CORE_B_HW, 641 PMU_CLR_CORE_B_2GIC_HW, 642 PMU_CLR_GIC2_CORE_B_HW, 643 644 PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16, 645 PMU_PWRDWN_REQ_CORE_L_SW_WMSK, 646 PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK, 647 PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK, 648 649 PMU_PWRDWN_REQ_CORE_B_SW_WMSK, 650 PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK, 651 PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK, 652 653 PMU_CLR_CXCS_HW_WMSK = 24, 654 PMU_CLR_CORE_L_HW_WMSK, 655 PMU_CLR_CORE_L_2GIC_HW_WMSK, 656 PMU_CLR_GIC2_CORE_L_HW_WMSK, 657 658 PMU_CLR_CORE_B_HW_WMSK, 659 PMU_CLR_CORE_B_2GIC_HW_WMSK, 660 PMU_CLR_GIC2_CORE_B_HW_WMSK, 661 }; 662 663 enum pmu_adb400_st { 664 PMU_PWRDWN_REQ_CXCS_SW_ST = 0, 665 PMU_PWRDWN_REQ_CORE_L_SW_ST, 666 PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST, 667 PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST, 668 669 PMU_PWRDWN_REQ_CORE_B_SW_ST, 670 PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST, 671 PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST, 672 673 PMU_CLR_CXCS_HW_ST = 8, 674 PMU_CLR_CORE_L_HW_ST, 675 PMU_CLR_CORE_L_2GIC_HW_ST, 676 PMU_CLR_GIC2_CORE_L_HW_ST, 677 678 PMU_CLR_CORE_B_HW_ST, 679 PMU_CLR_CORE_B_2GIC_HW_ST, 680 PMU_CLR_GIC2_CORE_B_HW_ST, 681 }; 682 683 enum pmu_pwrdn_con1 { 684 PMU_VD_SCU_L_PWRDN_EN = 0, 685 PMU_VD_SCU_B_PWRDN_EN, 686 PMU_VD_CENTER_PWRDN_EN, 687 }; 688 689 enum pmu_core_pwr_st { 690 L2_FLUSHDONE_CLUSTER_L = 0, 691 STANDBY_BY_WFIL2_CLUSTER_L, 692 693 L2_FLUSHDONE_CLUSTER_B = 10, 694 STANDBY_BY_WFIL2_CLUSTER_B, 695 }; 696 697 #endif /* __PMU_BITS_H__ */ 698
