1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PMU_REGS_H__ 8 #define __PMU_REGS_H__ 9 10 #define PMU_WKUP_CFG0 0x00 11 #define PMU_WKUP_CFG1 0x04 12 #define PMU_WKUP_CFG2 0x08 13 #define PMU_WKUP_CFG3 0x0c 14 #define PMU_WKUP_CFG4 0x10 15 #define PMU_PWRDN_CON 0x14 16 #define PMU_PWRDN_ST 0x18 17 #define PMU_PLL_CON 0x1c 18 #define PMU_PWRMODE_CON 0x20 19 #define PMU_SFT_CON 0x24 20 #define PMU_INT_CON 0x28 21 #define PMU_INT_ST 0x2c 22 #define PMU_GPIO0_POS_INT_CON 0x30 23 #define PMU_GPIO0_NEG_INT_CON 0x34 24 #define PMU_GPIO1_POS_INT_CON 0x38 25 #define PMU_GPIO1_NEG_INT_CON 0x3c 26 #define PMU_GPIO0_POS_INT_ST 0x40 27 #define PMU_GPIO0_NEG_INT_ST 0x44 28 #define PMU_GPIO1_POS_INT_ST 0x48 29 #define PMU_GPIO1_NEG_INT_ST 0x4c 30 #define PMU_PWRDN_INTEN 0x50 31 #define PMU_PWRDN_STATUS 0x54 32 #define PMU_WAKEUP_STATUS 0x58 33 #define PMU_BUS_CLR 0x5c 34 #define PMU_BUS_IDLE_REQ 0x60 35 #define PMU_BUS_IDLE_ST 0x64 36 #define PMU_BUS_IDLE_ACK 0x68 37 #define PMU_CCI500_CON 0x6c 38 #define PMU_ADB400_CON 0x70 39 #define PMU_ADB400_ST 0x74 40 #define PMU_POWER_ST 0x78 41 #define PMU_CORE_PWR_ST 0x7c 42 #define PMU_OSC_CNT 0x80 43 #define PMU_PLLLOCK_CNT 0x84 44 #define PMU_PLLRST_CNT 0x88 45 #define PMU_STABLE_CNT 0x8c 46 #define PMU_DDRIO_PWRON_CNT 0x90 47 #define PMU_WAKEUP_RST_CLR_CNT 0x94 48 #define PMU_DDR_SREF_ST 0x98 49 #define PMU_SCU_L_PWRDN_CNT 0x9c 50 #define PMU_SCU_L_PWRUP_CNT 0xa0 51 #define PMU_SCU_B_PWRDN_CNT 0xa4 52 #define PMU_SCU_B_PWRUP_CNT 0xa8 53 #define PMU_GPU_PWRDN_CNT 0xac 54 #define PMU_GPU_PWRUP_CNT 0xb0 55 #define PMU_CENTER_PWRDN_CNT 0xb4 56 #define PMU_CENTER_PWRUP_CNT 0xb8 57 #define PMU_TIMEOUT_CNT 0xbc 58 #define PMU_CPU0APM_CON 0xc0 59 #define PMU_CPU1APM_CON 0xc4 60 #define PMU_CPU2APM_CON 0xc8 61 #define PMU_CPU3APM_CON 0xcc 62 #define PMU_CPU0BPM_CON 0xd0 63 #define PMU_CPU1BPM_CON 0xd4 64 #define PMU_NOC_AUTO_ENA 0xd8 65 #define PMU_PWRDN_CON1 0xdc 66 67 #define PMUGRF_GPIO0A_IOMUX 0x00 68 #define PMUGRF_GPIO1A_IOMUX 0x10 69 #define PMUGRF_GPIO1C_IOMUX 0x18 70 71 #define PMUGRF_GPIO0A6_IOMUX_SHIFT 12 72 #define PMUGRF_GPIO0A6_IOMUX_PWM 0x1 73 #define PMUGRF_GPIO1C3_IOMUX_SHIFT 6 74 #define PMUGRF_GPIO1C3_IOMUX_PWM 0x1 75 76 #define CPU_AXI_QOS_ID_COREID 0x00 77 #define CPU_AXI_QOS_REVISIONID 0x04 78 #define CPU_AXI_QOS_PRIORITY 0x08 79 #define CPU_AXI_QOS_MODE 0x0c 80 #define CPU_AXI_QOS_BANDWIDTH 0x10 81 #define CPU_AXI_QOS_SATURATION 0x14 82 #define CPU_AXI_QOS_EXTCONTROL 0x18 83 #define CPU_AXI_QOS_NUM_REGS 0x07 84 85 #define CPU_AXI_CCI_M0_QOS_BASE 0xffa50000 86 #define CPU_AXI_CCI_M1_QOS_BASE 0xffad8000 87 #define CPU_AXI_DMAC0_QOS_BASE 0xffa64200 88 #define CPU_AXI_DMAC1_QOS_BASE 0xffa64280 89 #define CPU_AXI_DCF_QOS_BASE 0xffa64180 90 #define CPU_AXI_CRYPTO0_QOS_BASE 0xffa64100 91 #define CPU_AXI_CRYPTO1_QOS_BASE 0xffa64080 92 #define CPU_AXI_PMU_CM0_QOS_BASE 0xffa68000 93 #define CPU_AXI_PERI_CM1_QOS_BASE 0xffa64300 94 #define CPU_AXI_GIC_QOS_BASE 0xffa78000 95 #define CPU_AXI_SDIO_QOS_BASE 0xffa76000 96 #define CPU_AXI_SDMMC_QOS_BASE 0xffa74000 97 #define CPU_AXI_EMMC_QOS_BASE 0xffa58000 98 #define CPU_AXI_GMAC_QOS_BASE 0xffa5c000 99 #define CPU_AXI_USB_OTG0_QOS_BASE 0xffa70000 100 #define CPU_AXI_USB_OTG1_QOS_BASE 0xffa70080 101 #define CPU_AXI_USB_HOST0_QOS_BASE 0xffa60100 102 #define CPU_AXI_USB_HOST1_QOS_BASE 0xffa60180 103 #define CPU_AXI_GPU_QOS_BASE 0xffae0000 104 #define CPU_AXI_VIDEO_M0_QOS_BASE 0xffab8000 105 #define CPU_AXI_VIDEO_M1_R_QOS_BASE 0xffac0000 106 #define CPU_AXI_VIDEO_M1_W_QOS_BASE 0xffac0080 107 #define CPU_AXI_RGA_R_QOS_BASE 0xffab0000 108 #define CPU_AXI_RGA_W_QOS_BASE 0xffab0080 109 #define CPU_AXI_IEP_QOS_BASE 0xffa98000 110 #define CPU_AXI_VOP_BIG_R_QOS_BASE 0xffac8000 111 #define CPU_AXI_VOP_BIG_W_QOS_BASE 0xffac8080 112 #define CPU_AXI_VOP_LITTLE_QOS_BASE 0xffad0000 113 #define CPU_AXI_ISP0_M0_QOS_BASE 0xffaa0000 114 #define CPU_AXI_ISP0_M1_QOS_BASE 0xffaa0080 115 #define CPU_AXI_ISP1_M0_QOS_BASE 0xffaa8000 116 #define CPU_AXI_ISP1_M1_QOS_BASE 0xffaa8080 117 #define CPU_AXI_HDCP_QOS_BASE 0xffa90000 118 #define CPU_AXI_PERIHP_NSP_QOS_BASE 0xffad8080 119 #define CPU_AXI_PERILP_NSP_QOS_BASE 0xffad8180 120 #define CPU_AXI_PERILPSLV_NSP_QOS_BASE 0xffad8100 121 122 #define GRF_GPIO2A_IOMUX 0xe000 123 #define GRF_GPIO2B_IOMUX 0xe004 124 #define GRF_GPIO2C_IOMUX 0xe008 125 #define GRF_GPIO2D_IOMUX 0xe00c 126 #define GRF_GPIO3A_IOMUX 0xe010 127 #define GRF_GPIO3B_IOMUX 0xe014 128 #define GRF_GPIO3C_IOMUX 0xe018 129 #define GRF_GPIO3D_IOMUX 0xe01c 130 #define GRF_GPIO4A_IOMUX 0xe020 131 #define GRF_GPIO4B_IOMUX 0xe024 132 #define GRF_GPIO4C_IOMUX 0xe028 133 #define GRF_GPIO4D_IOMUX 0xe02c 134 135 #define GRF_GPIO2A_P 0xe040 136 #define GRF_GPIO2B_P 0xe044 137 #define GRF_GPIO2C_P 0xe048 138 #define GRF_GPIO2D_P 0xe04C 139 #define GRF_GPIO3A_P 0xe050 140 #define GRF_GPIO3B_P 0xe054 141 #define GRF_GPIO3C_P 0xe058 142 #define GRF_GPIO3D_P 0xe05C 143 #define GRF_GPIO4A_P 0xe060 144 #define GRF_GPIO4B_P 0xe064 145 #define GRF_GPIO4C_P 0xe068 146 #define GRF_GPIO4D_P 0xe06C 147 148 #endif /* __PMU_REGS_H__ */ 149
