1 /** @file 2 3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 4 Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR> 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef __AARCH64_H__ 17 #define __AARCH64_H__ 18 19 #include <Chipset/AArch64Mmu.h> 20 #include <Chipset/ArmArchTimer.h> 21 22 // ARM Interrupt ID in Exception Table 23 #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ 24 25 // CPACR - Coprocessor Access Control Register definitions 26 #define CPACR_TTA_EN (1UL << 28) 27 #define CPACR_FPEN_EL1 (1UL << 20) 28 #define CPACR_FPEN_FULL (3UL << 20) 29 #define CPACR_CP_FULL_ACCESS 0x300000 30 31 // Coprocessor Trap Register (CPTR) 32 #define AARCH64_CPTR_TFP (1 << 10) 33 34 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions 35 #define AARCH64_PFR0_FP (0xF << 16) 36 #define AARCH64_PFR0_GIC (0xF << 24) 37 38 // SCR - Secure Configuration Register definitions 39 #define SCR_NS (1 << 0) 40 #define SCR_IRQ (1 << 1) 41 #define SCR_FIQ (1 << 2) 42 #define SCR_EA (1 << 3) 43 #define SCR_FW (1 << 4) 44 #define SCR_AW (1 << 5) 45 46 // MIDR - Main ID Register definitions 47 #define ARM_CPU_TYPE_SHIFT 4 48 #define ARM_CPU_TYPE_MASK 0xFFF 49 #define ARM_CPU_TYPE_AEMv8 0xD0F 50 #define ARM_CPU_TYPE_A53 0xD03 51 #define ARM_CPU_TYPE_A57 0xD07 52 #define ARM_CPU_TYPE_A72 0xD08 53 #define ARM_CPU_TYPE_A15 0xC0F 54 #define ARM_CPU_TYPE_A9 0xC09 55 #define ARM_CPU_TYPE_A7 0xC07 56 #define ARM_CPU_TYPE_A5 0xC05 57 58 #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) ) 59 #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF)) 60 61 // Hypervisor Configuration Register 62 #define ARM_HCR_FMO BIT3 63 #define ARM_HCR_IMO BIT4 64 #define ARM_HCR_AMO BIT5 65 #define ARM_HCR_TSC BIT19 66 #define ARM_HCR_TGE BIT27 67 68 // Exception Syndrome Register 69 #define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr)) 70 #define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr)) 71 72 #define AARCH64_ESR_EC_SMC32 (0x13 << 26) 73 #define AARCH64_ESR_EC_SMC64 (0x17 << 26) 74 75 // AArch64 Exception Level 76 #define AARCH64_EL3 0xC 77 #define AARCH64_EL2 0x8 78 #define AARCH64_EL1 0x4 79 80 // Saved Program Status Register definitions 81 #define SPSR_A BIT8 82 #define SPSR_I BIT7 83 #define SPSR_F BIT6 84 85 #define SPSR_AARCH32 BIT4 86 87 #define SPSR_AARCH32_MODE_USER 0x0 88 #define SPSR_AARCH32_MODE_FIQ 0x1 89 #define SPSR_AARCH32_MODE_IRQ 0x2 90 #define SPSR_AARCH32_MODE_SVC 0x3 91 #define SPSR_AARCH32_MODE_ABORT 0x7 92 #define SPSR_AARCH32_MODE_UNDEF 0xB 93 #define SPSR_AARCH32_MODE_SYS 0xF 94 95 // Counter-timer Hypervisor Control register definitions 96 #define CNTHCTL_EL2_EL1PCTEN BIT0 97 #define CNTHCTL_EL2_EL1PCEN BIT1 98 99 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1) 100 101 // Vector table offset definitions 102 #define ARM_VECTOR_CUR_SP0_SYNC 0x000 103 #define ARM_VECTOR_CUR_SP0_IRQ 0x080 104 #define ARM_VECTOR_CUR_SP0_FIQ 0x100 105 #define ARM_VECTOR_CUR_SP0_SERR 0x180 106 107 #define ARM_VECTOR_CUR_SPx_SYNC 0x200 108 #define ARM_VECTOR_CUR_SPx_IRQ 0x280 109 #define ARM_VECTOR_CUR_SPx_FIQ 0x300 110 #define ARM_VECTOR_CUR_SPx_SERR 0x380 111 112 #define ARM_VECTOR_LOW_A64_SYNC 0x400 113 #define ARM_VECTOR_LOW_A64_IRQ 0x480 114 #define ARM_VECTOR_LOW_A64_FIQ 0x500 115 #define ARM_VECTOR_LOW_A64_SERR 0x580 116 117 #define ARM_VECTOR_LOW_A32_SYNC 0x600 118 #define ARM_VECTOR_LOW_A32_IRQ 0x680 119 #define ARM_VECTOR_LOW_A32_FIQ 0x700 120 #define ARM_VECTOR_LOW_A32_SERR 0x780 121 122 #define VECTOR_BASE(tbl) \ 123 .section .text.##tbl##,"ax"; \ 124 .align 11; \ 125 .org 0x0; \ 126 GCC_ASM_EXPORT(tbl); \ 127 ASM_PFX(tbl): \ 128 129 #define VECTOR_ENTRY(tbl, off) \ 130 .org off 131 132 #define VECTOR_END(tbl) \ 133 .org 0x800; \ 134 .previous 135 136 VOID 137 EFIAPI 138 ArmEnableSWPInstruction ( 139 VOID 140 ); 141 142 UINTN 143 EFIAPI 144 ArmReadCbar ( 145 VOID 146 ); 147 148 UINTN 149 EFIAPI 150 ArmReadTpidrurw ( 151 VOID 152 ); 153 154 VOID 155 EFIAPI 156 ArmWriteTpidrurw ( 157 UINTN Value 158 ); 159 160 UINTN 161 EFIAPI 162 ArmGetTCR ( 163 VOID 164 ); 165 166 VOID 167 EFIAPI 168 ArmSetTCR ( 169 UINTN Value 170 ); 171 172 UINTN 173 EFIAPI 174 ArmGetMAIR ( 175 VOID 176 ); 177 178 VOID 179 EFIAPI 180 ArmSetMAIR ( 181 UINTN Value 182 ); 183 184 VOID 185 EFIAPI 186 ArmDisableAlignmentCheck ( 187 VOID 188 ); 189 190 VOID 191 EFIAPI 192 ArmEnableAlignmentCheck ( 193 VOID 194 ); 195 196 VOID 197 EFIAPI 198 ArmDisableAllExceptions ( 199 VOID 200 ); 201 202 VOID 203 ArmWriteHcr ( 204 IN UINTN Hcr 205 ); 206 207 UINTN 208 ArmReadHcr ( 209 VOID 210 ); 211 212 UINTN 213 ArmReadCurrentEL ( 214 VOID 215 ); 216 217 UINT64 218 PageAttributeToGcdAttribute ( 219 IN UINT64 PageAttributes 220 ); 221 222 UINTN 223 ArmWriteCptr ( 224 IN UINT64 Cptr 225 ); 226 227 #endif // __AARCH64_H__ 228
