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      1 /** @file
      2 *
      3 *  Copyright (c) 2014, ARM Limited. All rights reserved.
      4 *
      5 *  This program and the accompanying materials are licensed and made available
      6 *  under the terms and conditions of the BSD License which accompanies this
      7 *  distribution.  The full text of the license may be found at
      8 *  http://opensource.org/licenses/bsd-license.php
      9 *
     10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     12 *
     13 **/
     14 
     15 #include <Library/ArmLib.h>
     16 #include <Library/ArmGicLib.h>
     17 
     18 STATIC ARM_GIC_ARCH_REVISION        mGicArchRevision;
     19 
     20 RETURN_STATUS
     21 EFIAPI
     22 ArmGicArchLibInitialize (
     23   VOID
     24   )
     25 {
     26   UINT32    IccSre;
     27 
     28   // Ideally we would like to use the GICC IIDR Architecture version here, but
     29   // this does not seem to be very reliable as the implementation could easily
     30   // get it wrong. It is more reliable to check if the GICv3 System Register
     31   // feature is implemented on the CPU. This is also convenient as our GICv3
     32   // driver requires SRE. If only Memory mapped access is available we try to
     33   // drive the GIC as a v2.
     34   if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
     35     // Make sure System Register access is enabled (SRE). This depends on the
     36     // higher privilege level giving us permission, otherwise we will either
     37     // cause an exception here, or the write doesn't stick in which case we need
     38     // to fall back to the GICv2 MMIO interface.
     39     // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
     40     // at the same exception level.
     41     // It is the OS responsibility to set this bit.
     42     IccSre = ArmGicV3GetControlSystemRegisterEnable ();
     43     if (!(IccSre & ICC_SRE_EL2_SRE)) {
     44       ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
     45       IccSre = ArmGicV3GetControlSystemRegisterEnable ();
     46     }
     47     if (IccSre & ICC_SRE_EL2_SRE) {
     48       mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
     49       goto Done;
     50     }
     51   }
     52 
     53   mGicArchRevision = ARM_GIC_ARCH_REVISION_2;
     54 
     55 Done:
     56   return RETURN_SUCCESS;
     57 }
     58 
     59 ARM_GIC_ARCH_REVISION
     60 EFIAPI
     61 ArmGicGetSupportedArchRevision (
     62   VOID
     63   )
     64 {
     65   return mGicArchRevision;
     66 }
     67