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      1 /** @file
      2 *
      3 *  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
      4 *
      5 *  This program and the accompanying materials
      6 *  are licensed and made available under the terms and conditions of the BSD License
      7 *  which accompanies this distribution.  The full text of the license may be found at
      8 *  http://opensource.org/licenses/bsd-license.php
      9 *
     10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     12 *
     13 **/
     14 
     15 #include <Uefi.h>
     16 #include <Chipset/AArch64.h>
     17 #include <Library/BaseMemoryLib.h>
     18 #include <Library/ArmLib.h>
     19 #include <Library/BaseLib.h>
     20 #include <Library/DebugLib.h>
     21 #include "AArch64Lib.h"
     22 #include "ArmLibPrivate.h"
     23 #include <Library/ArmArchTimer.h>
     24 
     25 VOID
     26 EFIAPI
     27 ArmArchTimerReadReg (
     28     IN   ARM_ARCH_TIMER_REGS   Reg,
     29     OUT  VOID                  *DstBuf
     30     )
     31 {
     32   // Check if the Generic/Architecture timer is implemented
     33   if (ArmIsArchTimerImplemented ()) {
     34 
     35     switch (Reg) {
     36 
     37     case CntFrq:
     38       *((UINTN *)DstBuf) = ArmReadCntFrq ();
     39       break;
     40 
     41     case CntPct:
     42       *((UINT64 *)DstBuf) = ArmReadCntPct ();
     43       break;
     44 
     45     case CntkCtl:
     46       *((UINTN *)DstBuf) = ArmReadCntkCtl();
     47       break;
     48 
     49     case CntpTval:
     50       *((UINTN *)DstBuf) = ArmReadCntpTval ();
     51       break;
     52 
     53     case CntpCtl:
     54       *((UINTN *)DstBuf) = ArmReadCntpCtl ();
     55       break;
     56 
     57     case CntvTval:
     58       *((UINTN *)DstBuf) = ArmReadCntvTval ();
     59       break;
     60 
     61     case CntvCtl:
     62       *((UINTN *)DstBuf) = ArmReadCntvCtl ();
     63       break;
     64 
     65     case CntvCt:
     66       *((UINT64 *)DstBuf) = ArmReadCntvCt ();
     67       break;
     68 
     69     case CntpCval:
     70       *((UINT64 *)DstBuf) = ArmReadCntpCval ();
     71       break;
     72 
     73     case CntvCval:
     74       *((UINT64 *)DstBuf) = ArmReadCntvCval ();
     75       break;
     76 
     77     case CntvOff:
     78       *((UINT64 *)DstBuf) = ArmReadCntvOff ();
     79       break;
     80 
     81     case CnthCtl:
     82     case CnthpTval:
     83     case CnthpCtl:
     84     case CnthpCval:
     85     DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
     86       break;
     87 
     88     default:
     89       DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
     90     }
     91   } else {
     92     DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
     93     ASSERT (0);
     94   }
     95 }
     96 
     97 VOID
     98 EFIAPI
     99 ArmArchTimerWriteReg (
    100     IN   ARM_ARCH_TIMER_REGS   Reg,
    101     IN   VOID                  *SrcBuf
    102     )
    103 {
    104   // Check if the Generic/Architecture timer is implemented
    105   if (ArmIsArchTimerImplemented ()) {
    106 
    107     switch (Reg) {
    108 
    109     case CntFrq:
    110       ArmWriteCntFrq (*((UINTN *)SrcBuf));
    111       break;
    112 
    113     case CntPct:
    114       DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
    115       break;
    116 
    117     case CntkCtl:
    118       ArmWriteCntkCtl (*((UINTN *)SrcBuf));
    119       break;
    120 
    121     case CntpTval:
    122       ArmWriteCntpTval (*((UINTN *)SrcBuf));
    123       break;
    124 
    125     case CntpCtl:
    126       ArmWriteCntpCtl (*((UINTN *)SrcBuf));
    127       break;
    128 
    129     case CntvTval:
    130       ArmWriteCntvTval (*((UINTN *)SrcBuf));
    131       break;
    132 
    133     case CntvCtl:
    134       ArmWriteCntvCtl (*((UINTN *)SrcBuf));
    135       break;
    136 
    137     case CntvCt:
    138       DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
    139       break;
    140 
    141     case CntpCval:
    142       ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
    143       break;
    144 
    145     case CntvCval:
    146       ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
    147       break;
    148 
    149     case CntvOff:
    150       ArmWriteCntvOff (*((UINT64 *)SrcBuf));
    151       break;
    152 
    153     case CnthCtl:
    154     case CnthpTval:
    155     case CnthpCtl:
    156     case CnthpCval:
    157       DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
    158       break;
    159 
    160     default:
    161       DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
    162     }
    163   } else {
    164     DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
    165     ASSERT (0);
    166   }
    167 }
    168