1 /** @file 2 * Header containing the structure specific to the Xpress-RICH3 PCIe Root Complex 3 * 4 * Copyright (c) 2011-2015, ARM Ltd. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef __PCIHOSTBRIDGE_H 17 #define __PCIHOSTBRIDGE_H 18 19 #include <PiDxe.h> 20 21 #include "XPressRich3.h" 22 23 #include <IndustryStandard/Pci.h> 24 #include <IndustryStandard/Acpi.h> 25 26 #include <Library/BaseLib.h> 27 #include <Library/BaseMemoryLib.h> 28 #include <Library/DebugLib.h> 29 #include <Library/DxeServicesTableLib.h> 30 #include <Library/IoLib.h> 31 #include <Library/MemoryAllocationLib.h> 32 #include <Library/PcdLib.h> 33 #include <Library/UefiBootServicesTableLib.h> 34 35 #include <Protocol/PciHostBridgeResourceAllocation.h> 36 #include <Protocol/PciRootBridgeIo.h> 37 #include <Protocol/PciIo.h> 38 #include <Protocol/DevicePath.h> 39 #include <Protocol/CpuIo2.h> 40 #include <Protocol/Metronome.h> 41 42 #define PCI_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_PCI: " txt "\n")) 43 44 #define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); } 45 #define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); } 46 47 #define PCIE_CONTROL_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Value); } 48 #define PCIE_CONTROL_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Val); } 49 50 /** 51 * PCI Root Bridge Device Path (ACPI Device Node + End Node) 52 */ 53 typedef struct { 54 ACPI_HID_DEVICE_PATH Acpi; 55 EFI_DEVICE_PATH_PROTOCOL End; 56 } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; 57 58 typedef enum { 59 ResTypeIo = 0, 60 ResTypeMem32, 61 ResTypePMem32, 62 ResTypeMem64, 63 ResTypePMem64, 64 ResTypeMax 65 } PCI_RESOURCE_TYPE; 66 67 #define ACPI_SPECFLAG_PREFETCHABLE 0x06 68 #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL 69 #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL 70 71 typedef struct { 72 UINT64 Base; 73 UINT64 Length; 74 UINT64 Alignment; 75 } PCI_RESOURCE_ALLOC; 76 77 typedef struct _PCI_HOST_BRIDGE_INSTANCE PCI_HOST_BRIDGE_INSTANCE; 78 79 /** 80 * PCI Root Bridge Instance structure 81 **/ 82 typedef struct { 83 UINTN Signature; 84 EFI_HANDLE Handle; 85 PCI_HOST_BRIDGE_INSTANCE *HostBridge; 86 // 87 // Set Type of memory allocation (could be EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM 88 // and EFI_PCI_HOST_BRIDGE_MEM64_DECODE). 89 // 90 UINT64 MemAllocAttributes; 91 PCI_RESOURCE_ALLOC ResAlloc[ResTypeMax]; 92 UINTN BusStart; 93 UINTN BusLength; 94 UINT64 Supports; 95 UINT64 Attributes; 96 EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath; 97 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; 98 } PCI_ROOT_BRIDGE_INSTANCE; 99 100 /** 101 * PCI Host Bridge Instance structure 102 **/ 103 struct _PCI_HOST_BRIDGE_INSTANCE { 104 UINTN Signature; 105 EFI_HANDLE Handle; 106 EFI_HANDLE ImageHandle; 107 PCI_ROOT_BRIDGE_INSTANCE *RootBridge; 108 // 109 // The enumeration cannot be restarted after the process goes into the non initial 110 // enumeration phase. 111 // 112 BOOLEAN CanRestarted; 113 EFI_CPU_IO2_PROTOCOL *CpuIo; 114 EFI_METRONOME_ARCH_PROTOCOL *Metronome; 115 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc; 116 }; 117 118 #define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('e', 'h', 's', 't') 119 #define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('e', '2', 'p', 'b') 120 #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE) 121 #define INSTANCE_FROM_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE) 122 123 /** 124 * PCI Host Bridge Resource Allocator Functions 125 **/ 126 EFI_STATUS PciHbRaNotifyPhase ( 127 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 128 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase 129 ); 130 131 EFI_STATUS PciHbRaGetNextRootBridge ( 132 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 133 IN OUT EFI_HANDLE *RootBridgeHandle 134 ); 135 136 EFI_STATUS PciHbRaGetAllocAttributes ( 137 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 138 IN EFI_HANDLE RootBridgeHandle, 139 OUT UINT64 *Attributes 140 ); 141 142 EFI_STATUS PciHbRaStartBusEnumeration ( 143 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 144 IN EFI_HANDLE RootBridgeHandle, 145 OUT VOID **Configuration 146 ); 147 148 EFI_STATUS PciHbRaSetBusNumbers ( 149 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 150 IN EFI_HANDLE RootBridgeHandle, 151 IN VOID *Configuration 152 ); 153 154 EFI_STATUS PciHbRaSubmitResources ( 155 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 156 IN EFI_HANDLE RootBridgeHandle, 157 IN VOID *Configuration 158 ); 159 160 EFI_STATUS PciHbRaGetProposedResources ( 161 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 162 IN EFI_HANDLE RootBridgeHandle, 163 OUT VOID **Configuration 164 ); 165 166 EFI_STATUS PciHbRaPreprocessController ( 167 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 168 IN EFI_HANDLE RootBridgeHandle, 169 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, 170 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase 171 ); 172 173 174 /** 175 * PCI Root Bridge 176 **/ 177 EFI_STATUS PciRbPollMem ( 178 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 179 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 180 IN UINT64 Address, 181 IN UINT64 Mask, 182 IN UINT64 Value, 183 IN UINT64 Delay, 184 OUT UINT64 *Result 185 ); 186 187 EFI_STATUS PciRbPollIo ( 188 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 189 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 190 IN UINT64 Address, 191 IN UINT64 Mask, 192 IN UINT64 Value, 193 IN UINT64 Delay, 194 OUT UINT64 *Result 195 ); 196 197 EFI_STATUS PciRbMemRead ( 198 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 199 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 200 IN UINT64 Address, 201 IN UINTN Count, 202 IN OUT VOID *Buffer 203 ); 204 205 EFI_STATUS PciRbMemWrite ( 206 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 207 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 208 IN UINT64 Address, 209 IN UINTN Count, 210 IN OUT VOID *Buffer 211 ); 212 213 EFI_STATUS PciRbIoRead ( 214 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 215 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 216 IN UINT64 Address, 217 IN UINTN Count, 218 IN OUT VOID *Buffer 219 ); 220 221 EFI_STATUS PciRbIoWrite ( 222 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 223 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 224 IN UINT64 Address, 225 IN UINTN Count, 226 IN OUT VOID *Buffer 227 ); 228 229 EFI_STATUS PciRbPciRead ( 230 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 231 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 232 IN UINT64 Address, 233 IN UINTN Count, 234 IN OUT VOID *Buffer 235 ); 236 237 EFI_STATUS PciRbPciWrite ( 238 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 239 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 240 IN UINT64 Address, 241 IN UINTN Count, 242 IN OUT VOID *Buffer 243 ); 244 245 EFI_STATUS PciRbCopyMem ( 246 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 247 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 248 IN UINT64 DestAddress, 249 IN UINT64 SrcAddress, 250 IN UINTN Count 251 ); 252 253 EFI_STATUS PciRbMap ( 254 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 255 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, 256 IN VOID *HostAddress, 257 IN OUT UINTN *NumberOfBytes, 258 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, 259 OUT VOID **Mapping 260 ); 261 262 EFI_STATUS PciRbUnMap ( 263 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 264 IN VOID *Mapping 265 ); 266 267 EFI_STATUS PciRbAllocateBuffer ( 268 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 269 IN EFI_ALLOCATE_TYPE Type, 270 IN EFI_MEMORY_TYPE MemoryType, 271 IN UINTN Pages, 272 IN OUT VOID **HostAddress, 273 IN UINT64 Attributes 274 ); 275 276 EFI_STATUS PciRbFreeBuffer ( 277 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 278 IN UINTN Pages, 279 IN VOID *HostAddress 280 ); 281 282 EFI_STATUS PciRbFlush ( 283 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This 284 ); 285 286 EFI_STATUS PciRbSetAttributes ( 287 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 288 IN UINT64 Attributes, 289 IN OUT UINT64 *ResourceBase, 290 IN OUT UINT64 *ResourceLength 291 ); 292 293 EFI_STATUS PciRbGetAttributes ( 294 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 295 OUT UINT64 *Supports, 296 OUT UINT64 *Attributes 297 ); 298 299 EFI_STATUS PciRbConfiguration ( 300 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 301 OUT VOID **Resources 302 ); 303 304 /** 305 * PCI Root Bridge Functions 306 **/ 307 EFI_STATUS 308 PciRbConstructor ( 309 IN PCI_HOST_BRIDGE_INSTANCE *HostBridge, 310 IN UINT32 PciAcpiUid, 311 IN UINT64 MemAllocAttributes 312 ); 313 314 EFI_STATUS 315 PciRbDestructor ( 316 IN PCI_ROOT_BRIDGE_INSTANCE* RootBridge 317 ); 318 319 EFI_STATUS 320 HWPciRbInit ( 321 IN EFI_CPU_IO2_PROTOCOL *CpuIo 322 ); 323 324 #endif 325
