1 /** @file PL111Lcd.h 2 3 Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> 4 This program and the accompanying materials 5 are licensed and made available under the terms and conditions of the BSD License 6 which accompanies this distribution. The full text of the license may be found at 7 http://opensource.org/licenses/bsd-license.php 8 9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 12 **/ 13 14 #ifndef _PL111LCD_H__ 15 #define _PL111LCD_H__ 16 17 /********************************************************************** 18 * 19 * This header file contains all the bits of the PL111 that are 20 * platform independent. 21 * 22 **********************************************************************/ 23 24 // Controller Register Offsets 25 #define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000) 26 #define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004) 27 #define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008) 28 #define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C) 29 #define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010) 30 #define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014) 31 #define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018) 32 #define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C) 33 #define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020) 34 #define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024) 35 #define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028) 36 #define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C) 37 #define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030) 38 #define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200) 39 40 // Identification Register Offsets 41 #define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0) 42 #define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4) 43 #define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8) 44 #define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC) 45 #define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0) 46 #define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4) 47 #define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8) 48 #define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC) 49 50 #define PL111_CLCD_PERIPH_ID_0 0x11 51 #define PL111_CLCD_PERIPH_ID_1 0x11 52 #define PL111_CLCD_PERIPH_ID_2 0x04 53 #define PL111_CLCD_PERIPH_ID_3 0x00 54 #define PL111_CLCD_P_CELL_ID_0 0x0D 55 #define PL111_CLCD_P_CELL_ID_1 0xF0 56 #define PL111_CLCD_P_CELL_ID_2 0x05 57 #define PL111_CLCD_P_CELL_ID_3 0xB1 58 59 /**********************************************************************/ 60 61 // Register components (register bits) 62 63 // This should make life easier to program specific settings in the different registers 64 // by simplifying the setting up of the individual bits of each register 65 // and then assembling the final register value. 66 67 /**********************************************************************/ 68 69 // Register: PL111_REG_LCD_TIMING_0 70 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2)) 71 72 // Register: PL111_REG_LCD_TIMING_1 73 #define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) 74 75 // Register: PL111_REG_LCD_TIMING_2 76 #define PL111_BIT_SHIFT_PCD_HI 27 77 #define PL111_BIT_SHIFT_BCD 26 78 #define PL111_BIT_SHIFT_CPL 16 79 #define PL111_BIT_SHIFT_IOE 14 80 #define PL111_BIT_SHIFT_IPC 13 81 #define PL111_BIT_SHIFT_IHS 12 82 #define PL111_BIT_SHIFT_IVS 11 83 #define PL111_BIT_SHIFT_ACB 6 84 #define PL111_BIT_SHIFT_CLKSEL 5 85 #define PL111_BIT_SHIFT_PCD_LO 0 86 87 #define PL111_BCD (1 << 26) 88 #define PL111_IPC (1 << 13) 89 #define PL111_IHS (1 << 12) 90 #define PL111_IVS (1 << 11) 91 92 #define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) 93 94 // Register: PL111_REG_LCD_TIMING_3 95 #define PL111_BIT_SHIFT_LEE 16 96 #define PL111_BIT_SHIFT_LED 0 97 98 #define PL111_CTRL_WATERMARK (1 << 16) 99 #define PL111_CTRL_LCD_V_COMP (1 << 12) 100 #define PL111_CTRL_LCD_PWR (1 << 11) 101 #define PL111_CTRL_BEPO (1 << 10) 102 #define PL111_CTRL_BEBO (1 << 9) 103 #define PL111_CTRL_BGR (1 << 8) 104 #define PL111_CTRL_LCD_DUAL (1 << 7) 105 #define PL111_CTRL_LCD_MONO_8 (1 << 6) 106 #define PL111_CTRL_LCD_TFT (1 << 5) 107 #define PL111_CTRL_LCD_BW (1 << 4) 108 #define PL111_CTRL_LCD_1BPP (0 << 1) 109 #define PL111_CTRL_LCD_2BPP (1 << 1) 110 #define PL111_CTRL_LCD_4BPP (2 << 1) 111 #define PL111_CTRL_LCD_8BPP (3 << 1) 112 #define PL111_CTRL_LCD_16BPP (4 << 1) 113 #define PL111_CTRL_LCD_24BPP (5 << 1) 114 #define PL111_CTRL_LCD_16BPP_565 (6 << 1) 115 #define PL111_CTRL_LCD_12BPP_444 (7 << 1) 116 #define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) 117 #define PL111_CTRL_LCD_EN 1 118 119 /**********************************************************************/ 120 121 // Register: PL111_REG_LCD_TIMING_0 122 #define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) 123 #define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) 124 #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) 125 #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) 126 127 // Register: PL111_REG_LCD_TIMING_1 128 #define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) 129 #define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) 130 #define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) 131 #define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) 132 133 // Register: PL111_REG_LCD_TIMING_2 134 #define PL111_BIT_MASK_PCD_HI 0xF8000000 135 #define PL111_BIT_MASK_BCD 0x04000000 136 #define PL111_BIT_MASK_CPL 0x03FF0000 137 #define PL111_BIT_MASK_IOE 0x00004000 138 #define PL111_BIT_MASK_IPC 0x00002000 139 #define PL111_BIT_MASK_IHS 0x00001000 140 #define PL111_BIT_MASK_IVS 0x00000800 141 #define PL111_BIT_MASK_ACB 0x000007C0 142 #define PL111_BIT_MASK_CLKSEL 0x00000020 143 #define PL111_BIT_MASK_PCD_LO 0x0000001F 144 145 // Register: PL111_REG_LCD_TIMING_3 146 #define PL111_BIT_MASK_LEE 0x00010000 147 #define PL111_BIT_MASK_LED 0x0000007F 148 149 #endif /* _PL111LCD_H__ */ 150
