1 /** @file 2 * 3 * Copyright (c) 2011, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 16 #ifndef _SP804_TIMER_H__ 17 #define _SP804_TIMER_H__ 18 19 // SP804 Timer constants 20 // Note: The SP804 Timer module comprises two timers, Timer_0 and Timer_1 21 // These timers are identical and all their registers have an offset of 0x20 22 // i.e. SP804_TIMER_0_LOAD_REG = 0x00 and SP804_TIMER_1_LOAD_REG = 0x20 23 // Therefore, define all registers only once and adjust the base addresses by 0x20 24 #define SP804_TIMER_LOAD_REG 0x00 25 #define SP804_TIMER_CURRENT_REG 0x04 26 #define SP804_TIMER_CONTROL_REG 0x08 27 #define SP804_TIMER_INT_CLR_REG 0x0C 28 #define SP804_TIMER_RAW_INT_STS_REG 0x10 29 #define SP804_TIMER_MSK_INT_STS_REG 0x14 30 #define SP804_TIMER_BG_LOAD_REG 0x18 31 32 // Timer control register bit definitions 33 #define SP804_TIMER_CTRL_ONESHOT BIT0 34 #define SP804_TIMER_CTRL_32BIT BIT1 35 #define SP804_TIMER_CTRL_PRESCALE_MASK (BIT3|BIT2) 36 #define SP804_PRESCALE_DIV_1 0 37 #define SP804_PRESCALE_DIV_16 BIT2 38 #define SP804_PRESCALE_DIV_256 BIT3 39 #define SP804_TIMER_CTRL_INT_ENABLE BIT5 40 #define SP804_TIMER_CTRL_PERIODIC BIT6 41 #define SP804_TIMER_CTRL_ENABLE BIT7 42 43 // Other SP804 Timer definitions 44 #define SP804_MAX_TICKS 0xFFFFFFFF 45 46 // SP810 System Controller constants 47 #define SP810_SYS_CTRL_REG 0x00 48 #define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK 49 #define SP810_SYS_CTRL_TIMER0_EN BIT16 50 #define SP810_SYS_CTRL_TIMER1_TIMCLK BIT17 // 0=REFCLK, 1=TIMCLK 51 #define SP810_SYS_CTRL_TIMER1_EN BIT18 52 #define SP810_SYS_CTRL_TIMER2_TIMCLK BIT19 // 0=REFCLK, 1=TIMCLK 53 #define SP810_SYS_CTRL_TIMER2_EN BIT20 54 #define SP810_SYS_CTRL_TIMER3_TIMCLK BIT21 // 0=REFCLK, 1=TIMCLK 55 #define SP810_SYS_CTRL_TIMER3_EN BIT22 56 57 #endif 58
