1 /*++ 2 3 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR> 4 This program and the accompanying materials 5 are licensed and made available under the terms and conditions of the BSD License 6 which accompanies this distribution. The full text of the license may be found at 7 http://opensource.org/licenses/bsd-license.php 8 9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 12 13 Module Name: 14 15 PciLib.c 16 17 Abstract: 18 19 PCI Library using Port CF8/CFC access. 20 21 --*/ 22 23 #include "EdkIIGlueBase.h" 24 25 /** 26 Reads an 8-bit PCI configuration register. 27 28 Reads and returns the 8-bit PCI configuration register specified by Address. 29 This function must guarantee that all PCI read and write operations are 30 serialized. 31 32 If Address > 0x0FFFFFFF, then ASSERT(). 33 34 @param Address Address that encodes the PCI Bus, Device, Function and 35 Register. 36 37 @return The read value from the PCI configuration register. 38 39 **/ 40 UINT8 41 EFIAPI 42 PciRead8 ( 43 IN UINTN Address 44 ) 45 { 46 return PciCf8Read8 (Address); 47 } 48 49 /** 50 Writes an 8-bit PCI configuration register. 51 52 Writes the 8-bit PCI configuration register specified by Address with the 53 value specified by Value. Value is returned. This function must guarantee 54 that all PCI read and write operations are serialized. 55 56 If Address > 0x0FFFFFFF, then ASSERT(). 57 58 @param Address Address that encodes the PCI Bus, Device, Function and 59 Register. 60 @param Value The value to write. 61 62 @return The value written to the PCI configuration register. 63 64 **/ 65 UINT8 66 EFIAPI 67 PciWrite8 ( 68 IN UINTN Address, 69 IN UINT8 Data 70 ) 71 { 72 return PciCf8Write8 (Address, Data); 73 } 74 75 /** 76 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with 77 an 8-bit value. 78 79 Reads the 8-bit PCI configuration register specified by Address, performs a 80 bitwise inclusive OR between the read result and the value specified by 81 OrData, and writes the result to the 8-bit PCI configuration register 82 specified by Address. The value written to the PCI configuration register is 83 returned. This function must guarantee that all PCI read and write operations 84 are serialized. 85 86 If Address > 0x0FFFFFFF, then ASSERT(). 87 88 @param Address Address that encodes the PCI Bus, Device, Function and 89 Register. 90 @param OrData The value to OR with the PCI configuration register. 91 92 @return The value written back to the PCI configuration register. 93 94 **/ 95 UINT8 96 EFIAPI 97 PciOr8 ( 98 IN UINTN Address, 99 IN UINT8 OrData 100 ) 101 { 102 return PciCf8Or8 (Address, OrData); 103 } 104 105 /** 106 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 107 value. 108 109 Reads the 8-bit PCI configuration register specified by Address, performs a 110 bitwise AND between the read result and the value specified by AndData, and 111 writes the result to the 8-bit PCI configuration register specified by 112 Address. The value written to the PCI configuration register is returned. 113 This function must guarantee that all PCI read and write operations are 114 serialized. 115 116 If Address > 0x0FFFFFFF, then ASSERT(). 117 118 @param Address Address that encodes the PCI Bus, Device, Function and 119 Register. 120 @param AndData The value to AND with the PCI configuration register. 121 122 @return The value written back to the PCI configuration register. 123 124 **/ 125 UINT8 126 EFIAPI 127 PciAnd8 ( 128 IN UINTN Address, 129 IN UINT8 AndData 130 ) 131 { 132 return PciCf8And8 (Address, AndData); 133 } 134 135 /** 136 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 137 value, followed a bitwise inclusive OR with another 8-bit value. 138 139 Reads the 8-bit PCI configuration register specified by Address, performs a 140 bitwise AND between the read result and the value specified by AndData, 141 performs a bitwise inclusive OR between the result of the AND operation and 142 the value specified by OrData, and writes the result to the 8-bit PCI 143 configuration register specified by Address. The value written to the PCI 144 configuration register is returned. This function must guarantee that all PCI 145 read and write operations are serialized. 146 147 If Address > 0x0FFFFFFF, then ASSERT(). 148 149 @param Address Address that encodes the PCI Bus, Device, Function and 150 Register. 151 @param AndData The value to AND with the PCI configuration register. 152 @param OrData The value to OR with the result of the AND operation. 153 154 @return The value written back to the PCI configuration register. 155 156 **/ 157 UINT8 158 EFIAPI 159 PciAndThenOr8 ( 160 IN UINTN Address, 161 IN UINT8 AndData, 162 IN UINT8 OrData 163 ) 164 { 165 return PciCf8AndThenOr8 (Address, AndData, OrData); 166 } 167 168 /** 169 Reads a bit field of a PCI configuration register. 170 171 Reads the bit field in an 8-bit PCI configuration register. The bit field is 172 specified by the StartBit and the EndBit. The value of the bit field is 173 returned. 174 175 If Address > 0x0FFFFFFF, then ASSERT(). 176 If StartBit is greater than 7, then ASSERT(). 177 If EndBit is greater than 7, then ASSERT(). 178 If EndBit is less than StartBit, then ASSERT(). 179 180 @param Address PCI configuration register to read. 181 @param StartBit The ordinal of the least significant bit in the bit field. 182 Range 0..7. 183 @param EndBit The ordinal of the most significant bit in the bit field. 184 Range 0..7. 185 186 @return The value of the bit field read from the PCI configuration register. 187 188 **/ 189 UINT8 190 EFIAPI 191 PciBitFieldRead8 ( 192 IN UINTN Address, 193 IN UINTN StartBit, 194 IN UINTN EndBit 195 ) 196 { 197 return PciCf8BitFieldRead8 (Address, StartBit, EndBit); 198 } 199 200 /** 201 Writes a bit field to a PCI configuration register. 202 203 Writes Value to the bit field of the PCI configuration register. The bit 204 field is specified by the StartBit and the EndBit. All other bits in the 205 destination PCI configuration register are preserved. The new value of the 206 8-bit register is returned. 207 208 If Address > 0x0FFFFFFF, then ASSERT(). 209 If StartBit is greater than 7, then ASSERT(). 210 If EndBit is greater than 7, then ASSERT(). 211 If EndBit is less than StartBit, then ASSERT(). 212 213 @param Address PCI configuration register to write. 214 @param StartBit The ordinal of the least significant bit in the bit field. 215 Range 0..7. 216 @param EndBit The ordinal of the most significant bit in the bit field. 217 Range 0..7. 218 @param Value New value of the bit field. 219 220 @return The value written back to the PCI configuration register. 221 222 **/ 223 UINT8 224 EFIAPI 225 PciBitFieldWrite8 ( 226 IN UINTN Address, 227 IN UINTN StartBit, 228 IN UINTN EndBit, 229 IN UINT8 Value 230 ) 231 { 232 return PciCf8BitFieldWrite8 (Address, StartBit, EndBit, Value); 233 } 234 235 /** 236 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and 237 writes the result back to the bit field in the 8-bit port. 238 239 Reads the 8-bit PCI configuration register specified by Address, performs a 240 bitwise inclusive OR between the read result and the value specified by 241 OrData, and writes the result to the 8-bit PCI configuration register 242 specified by Address. The value written to the PCI configuration register is 243 returned. This function must guarantee that all PCI read and write operations 244 are serialized. Extra left bits in OrData are stripped. 245 246 If Address > 0x0FFFFFFF, then ASSERT(). 247 If StartBit is greater than 7, then ASSERT(). 248 If EndBit is greater than 7, then ASSERT(). 249 If EndBit is less than StartBit, then ASSERT(). 250 251 @param Address PCI configuration register to write. 252 @param StartBit The ordinal of the least significant bit in the bit field. 253 Range 0..7. 254 @param EndBit The ordinal of the most significant bit in the bit field. 255 Range 0..7. 256 @param OrData The value to OR with the PCI configuration register. 257 258 @return The value written back to the PCI configuration register. 259 260 **/ 261 UINT8 262 EFIAPI 263 PciBitFieldOr8 ( 264 IN UINTN Address, 265 IN UINTN StartBit, 266 IN UINTN EndBit, 267 IN UINT8 OrData 268 ) 269 { 270 return PciCf8BitFieldOr8 (Address, StartBit, EndBit, OrData); 271 } 272 273 /** 274 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise 275 AND, and writes the result back to the bit field in the 8-bit register. 276 277 Reads the 8-bit PCI configuration register specified by Address, performs a 278 bitwise AND between the read result and the value specified by AndData, and 279 writes the result to the 8-bit PCI configuration register specified by 280 Address. The value written to the PCI configuration register is returned. 281 This function must guarantee that all PCI read and write operations are 282 serialized. Extra left bits in AndData are stripped. 283 284 If Address > 0x0FFFFFFF, then ASSERT(). 285 If StartBit is greater than 7, then ASSERT(). 286 If EndBit is greater than 7, then ASSERT(). 287 If EndBit is less than StartBit, then ASSERT(). 288 289 @param Address PCI configuration register to write. 290 @param StartBit The ordinal of the least significant bit in the bit field. 291 Range 0..7. 292 @param EndBit The ordinal of the most significant bit in the bit field. 293 Range 0..7. 294 @param AndData The value to AND with the PCI configuration register. 295 296 @return The value written back to the PCI configuration register. 297 298 **/ 299 UINT8 300 EFIAPI 301 PciBitFieldAnd8 ( 302 IN UINTN Address, 303 IN UINTN StartBit, 304 IN UINTN EndBit, 305 IN UINT8 AndData 306 ) 307 { 308 return PciCf8BitFieldAnd8 (Address, StartBit, EndBit, AndData); 309 } 310 311 /** 312 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a 313 bitwise inclusive OR, and writes the result back to the bit field in the 314 8-bit port. 315 316 Reads the 8-bit PCI configuration register specified by Address, performs a 317 bitwise AND followed by a bitwise inclusive OR between the read result and 318 the value specified by AndData, and writes the result to the 8-bit PCI 319 configuration register specified by Address. The value written to the PCI 320 configuration register is returned. This function must guarantee that all PCI 321 read and write operations are serialized. Extra left bits in both AndData and 322 OrData are stripped. 323 324 If Address > 0x0FFFFFFF, then ASSERT(). 325 If StartBit is greater than 7, then ASSERT(). 326 If EndBit is greater than 7, then ASSERT(). 327 If EndBit is less than StartBit, then ASSERT(). 328 329 @param Address PCI configuration register to write. 330 @param StartBit The ordinal of the least significant bit in the bit field. 331 Range 0..7. 332 @param EndBit The ordinal of the most significant bit in the bit field. 333 Range 0..7. 334 @param AndData The value to AND with the PCI configuration register. 335 @param OrData The value to OR with the result of the AND operation. 336 337 @return The value written back to the PCI configuration register. 338 339 **/ 340 UINT8 341 EFIAPI 342 PciBitFieldAndThenOr8 ( 343 IN UINTN Address, 344 IN UINTN StartBit, 345 IN UINTN EndBit, 346 IN UINT8 AndData, 347 IN UINT8 OrData 348 ) 349 { 350 return PciCf8BitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData); 351 } 352 353 /** 354 Reads a 16-bit PCI configuration register. 355 356 Reads and returns the 16-bit PCI configuration register specified by Address. 357 This function must guarantee that all PCI read and write operations are 358 serialized. 359 360 If Address > 0x0FFFFFFF, then ASSERT(). 361 362 @param Address Address that encodes the PCI Bus, Device, Function and 363 Register. 364 365 @return The read value from the PCI configuration register. 366 367 **/ 368 UINT16 369 EFIAPI 370 PciRead16 ( 371 IN UINTN Address 372 ) 373 { 374 return PciCf8Read16 (Address); 375 } 376 377 /** 378 Writes a 16-bit PCI configuration register. 379 380 Writes the 16-bit PCI configuration register specified by Address with the 381 value specified by Value. Value is returned. This function must guarantee 382 that all PCI read and write operations are serialized. 383 384 If Address > 0x0FFFFFFF, then ASSERT(). 385 386 @param Address Address that encodes the PCI Bus, Device, Function and 387 Register. 388 @param Value The value to write. 389 390 @return The value written to the PCI configuration register. 391 392 **/ 393 UINT16 394 EFIAPI 395 PciWrite16 ( 396 IN UINTN Address, 397 IN UINT16 Data 398 ) 399 { 400 return PciCf8Write16 (Address, Data); 401 } 402 403 /** 404 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with 405 a 16-bit value. 406 407 Reads the 16-bit PCI configuration register specified by Address, performs a 408 bitwise inclusive OR between the read result and the value specified by 409 OrData, and writes the result to the 16-bit PCI configuration register 410 specified by Address. The value written to the PCI configuration register is 411 returned. This function must guarantee that all PCI read and write operations 412 are serialized. 413 414 If Address > 0x0FFFFFFF, then ASSERT(). 415 416 @param Address Address that encodes the PCI Bus, Device, Function and 417 Register. 418 @param OrData The value to OR with the PCI configuration register. 419 420 @return The value written back to the PCI configuration register. 421 422 **/ 423 UINT16 424 EFIAPI 425 PciOr16 ( 426 IN UINTN Address, 427 IN UINT16 OrData 428 ) 429 { 430 return PciCf8Or16 (Address, OrData); 431 } 432 433 /** 434 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 435 value. 436 437 Reads the 16-bit PCI configuration register specified by Address, performs a 438 bitwise AND between the read result and the value specified by AndData, and 439 writes the result to the 16-bit PCI configuration register specified by 440 Address. The value written to the PCI configuration register is returned. 441 This function must guarantee that all PCI read and write operations are 442 serialized. 443 444 If Address > 0x0FFFFFFF, then ASSERT(). 445 446 @param Address Address that encodes the PCI Bus, Device, Function and 447 Register. 448 @param AndData The value to AND with the PCI configuration register. 449 450 @return The value written back to the PCI configuration register. 451 452 **/ 453 UINT16 454 EFIAPI 455 PciAnd16 ( 456 IN UINTN Address, 457 IN UINT16 AndData 458 ) 459 { 460 return PciCf8And16 (Address, AndData); 461 } 462 463 /** 464 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 465 value, followed a bitwise inclusive OR with another 16-bit value. 466 467 Reads the 16-bit PCI configuration register specified by Address, performs a 468 bitwise AND between the read result and the value specified by AndData, 469 performs a bitwise inclusive OR between the result of the AND operation and 470 the value specified by OrData, and writes the result to the 16-bit PCI 471 configuration register specified by Address. The value written to the PCI 472 configuration register is returned. This function must guarantee that all PCI 473 read and write operations are serialized. 474 475 If Address > 0x0FFFFFFF, then ASSERT(). 476 477 @param Address Address that encodes the PCI Bus, Device, Function and 478 Register. 479 @param AndData The value to AND with the PCI configuration register. 480 @param OrData The value to OR with the result of the AND operation. 481 482 @return The value written back to the PCI configuration register. 483 484 **/ 485 UINT16 486 EFIAPI 487 PciAndThenOr16 ( 488 IN UINTN Address, 489 IN UINT16 AndData, 490 IN UINT16 OrData 491 ) 492 { 493 return PciCf8AndThenOr16 (Address, AndData, OrData); 494 } 495 496 /** 497 Reads a bit field of a PCI configuration register. 498 499 Reads the bit field in a 16-bit PCI configuration register. The bit field is 500 specified by the StartBit and the EndBit. The value of the bit field is 501 returned. 502 503 If Address > 0x0FFFFFFF, then ASSERT(). 504 If StartBit is greater than 15, then ASSERT(). 505 If EndBit is greater than 15, then ASSERT(). 506 If EndBit is less than StartBit, then ASSERT(). 507 508 @param Address PCI configuration register to read. 509 @param StartBit The ordinal of the least significant bit in the bit field. 510 Range 0..15. 511 @param EndBit The ordinal of the most significant bit in the bit field. 512 Range 0..15. 513 514 @return The value of the bit field read from the PCI configuration register. 515 516 **/ 517 UINT16 518 EFIAPI 519 PciBitFieldRead16 ( 520 IN UINTN Address, 521 IN UINTN StartBit, 522 IN UINTN EndBit 523 ) 524 { 525 return PciCf8BitFieldRead16 (Address, StartBit, EndBit); 526 } 527 528 /** 529 Writes a bit field to a PCI configuration register. 530 531 Writes Value to the bit field of the PCI configuration register. The bit 532 field is specified by the StartBit and the EndBit. All other bits in the 533 destination PCI configuration register are preserved. The new value of the 534 16-bit register is returned. 535 536 If Address > 0x0FFFFFFF, then ASSERT(). 537 If StartBit is greater than 15, then ASSERT(). 538 If EndBit is greater than 15, then ASSERT(). 539 If EndBit is less than StartBit, then ASSERT(). 540 541 @param Address PCI configuration register to write. 542 @param StartBit The ordinal of the least significant bit in the bit field. 543 Range 0..15. 544 @param EndBit The ordinal of the most significant bit in the bit field. 545 Range 0..15. 546 @param Value New value of the bit field. 547 548 @return The value written back to the PCI configuration register. 549 550 **/ 551 UINT16 552 EFIAPI 553 PciBitFieldWrite16 ( 554 IN UINTN Address, 555 IN UINTN StartBit, 556 IN UINTN EndBit, 557 IN UINT16 Value 558 ) 559 { 560 return PciCf8BitFieldWrite16 (Address, StartBit, EndBit, Value); 561 } 562 563 /** 564 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and 565 writes the result back to the bit field in the 16-bit port. 566 567 Reads the 16-bit PCI configuration register specified by Address, performs a 568 bitwise inclusive OR between the read result and the value specified by 569 OrData, and writes the result to the 16-bit PCI configuration register 570 specified by Address. The value written to the PCI configuration register is 571 returned. This function must guarantee that all PCI read and write operations 572 are serialized. Extra left bits in OrData are stripped. 573 574 If Address > 0x0FFFFFFF, then ASSERT(). 575 If StartBit is greater than 15, then ASSERT(). 576 If EndBit is greater than 15, then ASSERT(). 577 If EndBit is less than StartBit, then ASSERT(). 578 579 @param Address PCI configuration register to write. 580 @param StartBit The ordinal of the least significant bit in the bit field. 581 Range 0..15. 582 @param EndBit The ordinal of the most significant bit in the bit field. 583 Range 0..15. 584 @param OrData The value to OR with the PCI configuration register. 585 586 @return The value written back to the PCI configuration register. 587 588 **/ 589 UINT16 590 EFIAPI 591 PciBitFieldOr16 ( 592 IN UINTN Address, 593 IN UINTN StartBit, 594 IN UINTN EndBit, 595 IN UINT16 OrData 596 ) 597 { 598 return PciCf8BitFieldOr16 (Address, StartBit, EndBit, OrData); 599 } 600 601 /** 602 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise 603 AND, and writes the result back to the bit field in the 16-bit register. 604 605 Reads the 16-bit PCI configuration register specified by Address, performs a 606 bitwise AND between the read result and the value specified by AndData, and 607 writes the result to the 16-bit PCI configuration register specified by 608 Address. The value written to the PCI configuration register is returned. 609 This function must guarantee that all PCI read and write operations are 610 serialized. Extra left bits in AndData are stripped. 611 612 If Address > 0x0FFFFFFF, then ASSERT(). 613 If StartBit is greater than 15, then ASSERT(). 614 If EndBit is greater than 15, then ASSERT(). 615 If EndBit is less than StartBit, then ASSERT(). 616 617 @param Address PCI configuration register to write. 618 @param StartBit The ordinal of the least significant bit in the bit field. 619 Range 0..15. 620 @param EndBit The ordinal of the most significant bit in the bit field. 621 Range 0..15. 622 @param AndData The value to AND with the PCI configuration register. 623 624 @return The value written back to the PCI configuration register. 625 626 **/ 627 UINT16 628 EFIAPI 629 PciBitFieldAnd16 ( 630 IN UINTN Address, 631 IN UINTN StartBit, 632 IN UINTN EndBit, 633 IN UINT16 AndData 634 ) 635 { 636 return PciCf8BitFieldAnd16 (Address, StartBit, EndBit, AndData); 637 } 638 639 /** 640 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a 641 bitwise inclusive OR, and writes the result back to the bit field in the 642 16-bit port. 643 644 Reads the 16-bit PCI configuration register specified by Address, performs a 645 bitwise AND followed by a bitwise inclusive OR between the read result and 646 the value specified by AndData, and writes the result to the 16-bit PCI 647 configuration register specified by Address. The value written to the PCI 648 configuration register is returned. This function must guarantee that all PCI 649 read and write operations are serialized. Extra left bits in both AndData and 650 OrData are stripped. 651 652 If Address > 0x0FFFFFFF, then ASSERT(). 653 If StartBit is greater than 15, then ASSERT(). 654 If EndBit is greater than 15, then ASSERT(). 655 If EndBit is less than StartBit, then ASSERT(). 656 657 @param Address PCI configuration register to write. 658 @param StartBit The ordinal of the least significant bit in the bit field. 659 Range 0..15. 660 @param EndBit The ordinal of the most significant bit in the bit field. 661 Range 0..15. 662 @param AndData The value to AND with the PCI configuration register. 663 @param OrData The value to OR with the result of the AND operation. 664 665 @return The value written back to the PCI configuration register. 666 667 **/ 668 UINT16 669 EFIAPI 670 PciBitFieldAndThenOr16 ( 671 IN UINTN Address, 672 IN UINTN StartBit, 673 IN UINTN EndBit, 674 IN UINT16 AndData, 675 IN UINT16 OrData 676 ) 677 { 678 return PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData); 679 } 680 681 /** 682 Reads a 32-bit PCI configuration register. 683 684 Reads and returns the 32-bit PCI configuration register specified by Address. 685 This function must guarantee that all PCI read and write operations are 686 serialized. 687 688 If Address > 0x0FFFFFFF, then ASSERT(). 689 690 @param Address Address that encodes the PCI Bus, Device, Function and 691 Register. 692 693 @return The read value from the PCI configuration register. 694 695 **/ 696 UINT32 697 EFIAPI 698 PciRead32 ( 699 IN UINTN Address 700 ) 701 { 702 return PciCf8Read32 (Address); 703 } 704 705 /** 706 Writes a 32-bit PCI configuration register. 707 708 Writes the 32-bit PCI configuration register specified by Address with the 709 value specified by Value. Value is returned. This function must guarantee 710 that all PCI read and write operations are serialized. 711 712 If Address > 0x0FFFFFFF, then ASSERT(). 713 714 @param Address Address that encodes the PCI Bus, Device, Function and 715 Register. 716 @param Value The value to write. 717 718 @return The value written to the PCI configuration register. 719 720 **/ 721 UINT32 722 EFIAPI 723 PciWrite32 ( 724 IN UINTN Address, 725 IN UINT32 Data 726 ) 727 { 728 return PciCf8Write32 (Address, Data); 729 } 730 731 /** 732 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with 733 a 32-bit value. 734 735 Reads the 32-bit PCI configuration register specified by Address, performs a 736 bitwise inclusive OR between the read result and the value specified by 737 OrData, and writes the result to the 32-bit PCI configuration register 738 specified by Address. The value written to the PCI configuration register is 739 returned. This function must guarantee that all PCI read and write operations 740 are serialized. 741 742 If Address > 0x0FFFFFFF, then ASSERT(). 743 744 @param Address Address that encodes the PCI Bus, Device, Function and 745 Register. 746 @param OrData The value to OR with the PCI configuration register. 747 748 @return The value written back to the PCI configuration register. 749 750 **/ 751 UINT32 752 EFIAPI 753 PciOr32 ( 754 IN UINTN Address, 755 IN UINT32 OrData 756 ) 757 { 758 return PciCf8Or32 (Address, OrData); 759 } 760 761 /** 762 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 763 value. 764 765 Reads the 32-bit PCI configuration register specified by Address, performs a 766 bitwise AND between the read result and the value specified by AndData, and 767 writes the result to the 32-bit PCI configuration register specified by 768 Address. The value written to the PCI configuration register is returned. 769 This function must guarantee that all PCI read and write operations are 770 serialized. 771 772 If Address > 0x0FFFFFFF, then ASSERT(). 773 774 @param Address Address that encodes the PCI Bus, Device, Function and 775 Register. 776 @param AndData The value to AND with the PCI configuration register. 777 778 @return The value written back to the PCI configuration register. 779 780 **/ 781 UINT32 782 EFIAPI 783 PciAnd32 ( 784 IN UINTN Address, 785 IN UINT32 AndData 786 ) 787 { 788 return PciCf8And32 (Address, AndData); 789 } 790 791 /** 792 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 793 value, followed a bitwise inclusive OR with another 32-bit value. 794 795 Reads the 32-bit PCI configuration register specified by Address, performs a 796 bitwise AND between the read result and the value specified by AndData, 797 performs a bitwise inclusive OR between the result of the AND operation and 798 the value specified by OrData, and writes the result to the 32-bit PCI 799 configuration register specified by Address. The value written to the PCI 800 configuration register is returned. This function must guarantee that all PCI 801 read and write operations are serialized. 802 803 If Address > 0x0FFFFFFF, then ASSERT(). 804 805 @param Address Address that encodes the PCI Bus, Device, Function and 806 Register. 807 @param AndData The value to AND with the PCI configuration register. 808 @param OrData The value to OR with the result of the AND operation. 809 810 @return The value written back to the PCI configuration register. 811 812 **/ 813 UINT32 814 EFIAPI 815 PciAndThenOr32 ( 816 IN UINTN Address, 817 IN UINT32 AndData, 818 IN UINT32 OrData 819 ) 820 { 821 return PciCf8AndThenOr32 (Address, AndData, OrData); 822 } 823 824 /** 825 Reads a bit field of a PCI configuration register. 826 827 Reads the bit field in a 32-bit PCI configuration register. The bit field is 828 specified by the StartBit and the EndBit. The value of the bit field is 829 returned. 830 831 If Address > 0x0FFFFFFF, then ASSERT(). 832 If StartBit is greater than 31, then ASSERT(). 833 If EndBit is greater than 31, then ASSERT(). 834 If EndBit is less than StartBit, then ASSERT(). 835 836 @param Address PCI configuration register to read. 837 @param StartBit The ordinal of the least significant bit in the bit field. 838 Range 0..31. 839 @param EndBit The ordinal of the most significant bit in the bit field. 840 Range 0..31. 841 842 @return The value of the bit field read from the PCI configuration register. 843 844 **/ 845 UINT32 846 EFIAPI 847 PciBitFieldRead32 ( 848 IN UINTN Address, 849 IN UINTN StartBit, 850 IN UINTN EndBit 851 ) 852 { 853 return PciCf8BitFieldRead32 (Address, StartBit, EndBit); 854 } 855 856 /** 857 Writes a bit field to a PCI configuration register. 858 859 Writes Value to the bit field of the PCI configuration register. The bit 860 field is specified by the StartBit and the EndBit. All other bits in the 861 destination PCI configuration register are preserved. The new value of the 862 32-bit register is returned. 863 864 If Address > 0x0FFFFFFF, then ASSERT(). 865 If StartBit is greater than 31, then ASSERT(). 866 If EndBit is greater than 31, then ASSERT(). 867 If EndBit is less than StartBit, then ASSERT(). 868 869 @param Address PCI configuration register to write. 870 @param StartBit The ordinal of the least significant bit in the bit field. 871 Range 0..31. 872 @param EndBit The ordinal of the most significant bit in the bit field. 873 Range 0..31. 874 @param Value New value of the bit field. 875 876 @return The value written back to the PCI configuration register. 877 878 **/ 879 UINT32 880 EFIAPI 881 PciBitFieldWrite32 ( 882 IN UINTN Address, 883 IN UINTN StartBit, 884 IN UINTN EndBit, 885 IN UINT32 Value 886 ) 887 { 888 return PciCf8BitFieldWrite32 (Address, StartBit, EndBit, Value); 889 } 890 891 /** 892 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and 893 writes the result back to the bit field in the 32-bit port. 894 895 Reads the 32-bit PCI configuration register specified by Address, performs a 896 bitwise inclusive OR between the read result and the value specified by 897 OrData, and writes the result to the 32-bit PCI configuration register 898 specified by Address. The value written to the PCI configuration register is 899 returned. This function must guarantee that all PCI read and write operations 900 are serialized. Extra left bits in OrData are stripped. 901 902 If Address > 0x0FFFFFFF, then ASSERT(). 903 If StartBit is greater than 31, then ASSERT(). 904 If EndBit is greater than 31, then ASSERT(). 905 If EndBit is less than StartBit, then ASSERT(). 906 907 @param Address PCI configuration register to write. 908 @param StartBit The ordinal of the least significant bit in the bit field. 909 Range 0..31. 910 @param EndBit The ordinal of the most significant bit in the bit field. 911 Range 0..31. 912 @param OrData The value to OR with the PCI configuration register. 913 914 @return The value written back to the PCI configuration register. 915 916 **/ 917 UINT32 918 EFIAPI 919 PciBitFieldOr32 ( 920 IN UINTN Address, 921 IN UINTN StartBit, 922 IN UINTN EndBit, 923 IN UINT32 OrData 924 ) 925 { 926 return PciCf8BitFieldOr32 (Address, StartBit, EndBit, OrData); 927 } 928 929 /** 930 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise 931 AND, and writes the result back to the bit field in the 32-bit register. 932 933 Reads the 32-bit PCI configuration register specified by Address, performs a 934 bitwise AND between the read result and the value specified by AndData, and 935 writes the result to the 32-bit PCI configuration register specified by 936 Address. The value written to the PCI configuration register is returned. 937 This function must guarantee that all PCI read and write operations are 938 serialized. Extra left bits in AndData are stripped. 939 940 If Address > 0x0FFFFFFF, then ASSERT(). 941 If StartBit is greater than 31, then ASSERT(). 942 If EndBit is greater than 31, then ASSERT(). 943 If EndBit is less than StartBit, then ASSERT(). 944 945 @param Address PCI configuration register to write. 946 @param StartBit The ordinal of the least significant bit in the bit field. 947 Range 0..31. 948 @param EndBit The ordinal of the most significant bit in the bit field. 949 Range 0..31. 950 @param AndData The value to AND with the PCI configuration register. 951 952 @return The value written back to the PCI configuration register. 953 954 **/ 955 UINT32 956 EFIAPI 957 PciBitFieldAnd32 ( 958 IN UINTN Address, 959 IN UINTN StartBit, 960 IN UINTN EndBit, 961 IN UINT32 AndData 962 ) 963 { 964 return PciCf8BitFieldAnd32 (Address, StartBit, EndBit, AndData); 965 } 966 967 /** 968 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a 969 bitwise inclusive OR, and writes the result back to the bit field in the 970 32-bit port. 971 972 Reads the 32-bit PCI configuration register specified by Address, performs a 973 bitwise AND followed by a bitwise inclusive OR between the read result and 974 the value specified by AndData, and writes the result to the 32-bit PCI 975 configuration register specified by Address. The value written to the PCI 976 configuration register is returned. This function must guarantee that all PCI 977 read and write operations are serialized. Extra left bits in both AndData and 978 OrData are stripped. 979 980 If Address > 0x0FFFFFFF, then ASSERT(). 981 If StartBit is greater than 31, then ASSERT(). 982 If EndBit is greater than 31, then ASSERT(). 983 If EndBit is less than StartBit, then ASSERT(). 984 985 @param Address PCI configuration register to write. 986 @param StartBit The ordinal of the least significant bit in the bit field. 987 Range 0..31. 988 @param EndBit The ordinal of the most significant bit in the bit field. 989 Range 0..31. 990 @param AndData The value to AND with the PCI configuration register. 991 @param OrData The value to OR with the result of the AND operation. 992 993 @return The value written back to the PCI configuration register. 994 995 **/ 996 UINT32 997 EFIAPI 998 PciBitFieldAndThenOr32 ( 999 IN UINTN Address, 1000 IN UINTN StartBit, 1001 IN UINTN EndBit, 1002 IN UINT32 AndData, 1003 IN UINT32 OrData 1004 ) 1005 { 1006 return PciCf8BitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData); 1007 } 1008 1009 /** 1010 Reads a range of PCI configuration registers into a caller supplied buffer. 1011 1012 Reads the range of PCI configuration registers specified by StartAddress and 1013 Size into the buffer specified by Buffer. This function only allows the PCI 1014 configuration registers from a single PCI function to be read. Size is 1015 returned. When possible 32-bit PCI configuration read cycles are used to read 1016 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit 1017 and 16-bit PCI configuration read cycles may be used at the beginning and the 1018 end of the range. 1019 1020 If StartAddress > 0x0FFFFFFF, then ASSERT(). 1021 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). 1022 If Size > 0 and Buffer is NULL, then ASSERT(). 1023 1024 @param StartAddress Starting address that encodes the PCI Bus, Device, 1025 Function and Register. 1026 @param Size Size in bytes of the transfer. 1027 @param Buffer Pointer to a buffer receiving the data read. 1028 1029 @return Size 1030 1031 **/ 1032 UINTN 1033 EFIAPI 1034 PciReadBuffer ( 1035 IN UINTN StartAddress, 1036 IN UINTN Size, 1037 OUT VOID *Buffer 1038 ) 1039 { 1040 return PciCf8ReadBuffer (StartAddress, Size, Buffer); 1041 } 1042 1043 /** 1044 Copies the data in a caller supplied buffer to a specified range of PCI 1045 configuration space. 1046 1047 Writes the range of PCI configuration registers specified by StartAddress and 1048 Size from the buffer specified by Buffer. This function only allows the PCI 1049 configuration registers from a single PCI function to be written. Size is 1050 returned. When possible 32-bit PCI configuration write cycles are used to 1051 write from StartAdress to StartAddress + Size. Due to alignment restrictions, 1052 8-bit and 16-bit PCI configuration write cycles may be used at the beginning 1053 and the end of the range. 1054 1055 If StartAddress > 0x0FFFFFFF, then ASSERT(). 1056 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). 1057 If Size > 0 and Buffer is NULL, then ASSERT(). 1058 1059 @param StartAddress Starting address that encodes the PCI Bus, Device, 1060 Function and Register. 1061 @param Size Size in bytes of the transfer. 1062 @param Buffer Pointer to a buffer containing the data to write. 1063 1064 @return Size 1065 1066 **/ 1067 UINTN 1068 EFIAPI 1069 PciWriteBuffer ( 1070 IN UINTN StartAddress, 1071 IN UINTN Size, 1072 IN VOID *Buffer 1073 ) 1074 { 1075 return PciCf8WriteBuffer (StartAddress, Size, Buffer); 1076 } 1077
