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      1 ;------------------------------------------------------------------------------
      2 ;
      3 ; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
      4 ; This program and the accompanying materials
      5 ; are licensed and made available under the terms and conditions of the BSD License
      6 ; which accompanies this distribution.  The full text of the license may be found at
      7 ; http://opensource.org/licenses/bsd-license.php.
      8 ;
      9 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     10 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     11 ;
     12 ; Abstract:
     13 ;
     14 ;------------------------------------------------------------------------------
     15 
     16 
     17 SECTION .data
     18 ;
     19 ; Float control word initial value:
     20 ; all exceptions masked, double-precision, round-to-nearest
     21 ;
     22 ASM_PFX(mFpuControlWord):
     23     dw    0x027F
     24 ;
     25 ; Multimedia-extensions control word:
     26 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
     27 ;
     28 ASM_PFX(mMmxControlWord):
     29      dd     0x01F80
     30 
     31 SECTION .text
     32 
     33 ;
     34 ; Initializes floating point units for requirement of UEFI specification.
     35 ;
     36 ; This function initializes floating-point control word to 0x027F (all exceptions
     37 ; masked,double-precision, round-to-nearest) and multimedia-extensions control word
     38 ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
     39 ; for masked underflow).
     40 ;
     41 
     42 global ASM_PFX(InitializeFloatingPointUnits)
     43 ASM_PFX(InitializeFloatingPointUnits):
     44 
     45 
     46     push    ebx
     47 
     48     ;
     49     ; Initialize floating point units
     50     ;
     51     finit
     52     fldcw    [ASM_PFX(mFpuControlWord)]
     53 
     54     ;
     55     ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
     56     ; whether the processor supports SSE instruction.
     57     ;
     58     mov     eax, 1
     59     cpuid
     60     bt      edx, 25
     61     jnc     Done
     62 
     63     ;
     64     ; Set OSFXSR bit 9 in CR4
     65     ;
     66     mov     eax, cr4
     67     or      eax, BIT9
     68     mov     cr4, eax
     69 
     70     ;
     71     ; The processor should support SSE instruction and we can use
     72     ; ldmxcsr instruction
     73     ;
     74     ldmxcsr [ASM_PFX(mMmxControlWord)]
     75 Done:
     76     pop     ebx
     77 
     78     ret
     79