1 /** @file 2 Provides services to maintain instruction and data caches. 3 4 The Cache Maintenance Library provides abstractions for basic processor cache operations. 5 It removes the need to use assembly in C code. 6 7 Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR> 8 This program and the accompanying materials 9 are licensed and made available under the terms and conditions of the BSD License 10 which accompanies this distribution. The full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php 12 13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 15 16 **/ 17 18 #ifndef __CACHE_MAINTENANCE_LIB__ 19 #define __CACHE_MAINTENANCE_LIB__ 20 21 /** 22 Invalidates the entire instruction cache in cache coherency domain of the 23 calling CPU. 24 25 **/ 26 VOID 27 EFIAPI 28 InvalidateInstructionCache ( 29 VOID 30 ); 31 32 /** 33 Invalidates a range of instruction cache lines in the cache coherency domain 34 of the calling CPU. 35 36 Invalidates the instruction cache lines specified by Address and Length. If 37 Address is not aligned on a cache line boundary, then entire instruction 38 cache line containing Address is invalidated. If Address + Length is not 39 aligned on a cache line boundary, then the entire instruction cache line 40 containing Address + Length -1 is invalidated. This function may choose to 41 invalidate the entire instruction cache if that is more efficient than 42 invalidating the specified range. If Length is 0, then no instruction cache 43 lines are invalidated. Address is returned. 44 45 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). 46 47 @param Address The base address of the instruction cache lines to 48 invalidate. If the CPU is in a physical addressing mode, then 49 Address is a physical address. If the CPU is in a virtual 50 addressing mode, then Address is a virtual address. 51 52 @param Length The number of bytes to invalidate from the instruction cache. 53 54 @return Address. 55 56 **/ 57 VOID * 58 EFIAPI 59 InvalidateInstructionCacheRange ( 60 IN VOID *Address, 61 IN UINTN Length 62 ); 63 64 /** 65 Writes Back and Invalidates the entire data cache in cache coherency domain 66 of the calling CPU. 67 68 Writes Back and Invalidates the entire data cache in cache coherency domain 69 of the calling CPU. This function guarantees that all dirty cache lines are 70 written back to system memory, and also invalidates all the data cache lines 71 in the cache coherency domain of the calling CPU. 72 73 **/ 74 VOID 75 EFIAPI 76 WriteBackInvalidateDataCache ( 77 VOID 78 ); 79 80 /** 81 Writes Back and Invalidates a range of data cache lines in the cache 82 coherency domain of the calling CPU. 83 84 Writes Back and Invalidate the data cache lines specified by Address and 85 Length. If Address is not aligned on a cache line boundary, then entire data 86 cache line containing Address is written back and invalidated. If Address + 87 Length is not aligned on a cache line boundary, then the entire data cache 88 line containing Address + Length -1 is written back and invalidated. This 89 function may choose to write back and invalidate the entire data cache if 90 that is more efficient than writing back and invalidating the specified 91 range. If Length is 0, then no data cache lines are written back and 92 invalidated. Address is returned. 93 94 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). 95 96 @param Address The base address of the data cache lines to write back and 97 invalidate. If the CPU is in a physical addressing mode, then 98 Address is a physical address. If the CPU is in a virtual 99 addressing mode, then Address is a virtual address. 100 @param Length The number of bytes to write back and invalidate from the 101 data cache. 102 103 @return Address of cache invalidation. 104 105 **/ 106 VOID * 107 EFIAPI 108 WriteBackInvalidateDataCacheRange ( 109 IN VOID *Address, 110 IN UINTN Length 111 ); 112 113 /** 114 Writes Back the entire data cache in cache coherency domain of the calling 115 CPU. 116 117 Writes Back the entire data cache in cache coherency domain of the calling 118 CPU. This function guarantees that all dirty cache lines are written back to 119 system memory. This function may also invalidate all the data cache lines in 120 the cache coherency domain of the calling CPU. 121 122 **/ 123 VOID 124 EFIAPI 125 WriteBackDataCache ( 126 VOID 127 ); 128 129 /** 130 Writes Back a range of data cache lines in the cache coherency domain of the 131 calling CPU. 132 133 Writes Back the data cache lines specified by Address and Length. If Address 134 is not aligned on a cache line boundary, then entire data cache line 135 containing Address is written back. If Address + Length is not aligned on a 136 cache line boundary, then the entire data cache line containing Address + 137 Length -1 is written back. This function may choose to write back the entire 138 data cache if that is more efficient than writing back the specified range. 139 If Length is 0, then no data cache lines are written back. This function may 140 also invalidate all the data cache lines in the specified range of the cache 141 coherency domain of the calling CPU. Address is returned. 142 143 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). 144 145 @param Address The base address of the data cache lines to write back. If 146 the CPU is in a physical addressing mode, then Address is a 147 physical address. If the CPU is in a virtual addressing 148 mode, then Address is a virtual address. 149 @param Length The number of bytes to write back from the data cache. 150 151 @return Address of cache written in main memory. 152 153 **/ 154 VOID * 155 EFIAPI 156 WriteBackDataCacheRange ( 157 IN VOID *Address, 158 IN UINTN Length 159 ); 160 161 /** 162 Invalidates the entire data cache in cache coherency domain of the calling 163 CPU. 164 165 Invalidates the entire data cache in cache coherency domain of the calling 166 CPU. This function must be used with care because dirty cache lines are not 167 written back to system memory. It is typically used for cache diagnostics. If 168 the CPU does not support invalidation of the entire data cache, then a write 169 back and invalidate operation should be performed on the entire data cache. 170 171 **/ 172 VOID 173 EFIAPI 174 InvalidateDataCache ( 175 VOID 176 ); 177 178 /** 179 Invalidates a range of data cache lines in the cache coherency domain of the 180 calling CPU. 181 182 Invalidates the data cache lines specified by Address and Length. If Address 183 is not aligned on a cache line boundary, then entire data cache line 184 containing Address is invalidated. If Address + Length is not aligned on a 185 cache line boundary, then the entire data cache line containing Address + 186 Length -1 is invalidated. This function must never invalidate any cache lines 187 outside the specified range. If Length is 0, the no data cache lines are 188 invalidated. Address is returned. This function must be used with care 189 because dirty cache lines are not written back to system memory. It is 190 typically used for cache diagnostics. If the CPU does not support 191 invalidation of a data cache range, then a write back and invalidate 192 operation should be performed on the data cache range. 193 194 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). 195 196 @param Address The base address of the data cache lines to invalidate. If 197 the CPU is in a physical addressing mode, then Address is a 198 physical address. If the CPU is in a virtual addressing mode, 199 then Address is a virtual address. 200 @param Length The number of bytes to invalidate from the data cache. 201 202 @return Address. 203 204 **/ 205 VOID * 206 EFIAPI 207 InvalidateDataCacheRange ( 208 IN VOID *Address, 209 IN UINTN Length 210 ); 211 212 #endif 213
