1 /** @file 2 This files describes the CPU I/O 2 Protocol. 3 4 This protocol provides an I/O abstraction for a system processor. This protocol 5 is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions. 6 The I/O or memory primitives can be used by the consumer of the protocol to materialize 7 bus-specific configuration cycles, such as the transitional configuration address and data 8 ports for PCI. Only drivers that require direct access to the entire system should use this 9 protocol. 10 11 Note: This is a boot-services only protocol and it may not be used by runtime drivers after 12 ExitBootServices(). It is different from the Framework CPU I/O Protocol, which is a runtime 13 protocol and can be used by runtime drivers after ExitBootServices(). 14 15 Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR> 16 This program and the accompanying materials 17 are licensed and made available under the terms and conditions of the BSD License 18 which accompanies this distribution. The full text of the license may be found at 19 http://opensource.org/licenses/bsd-license.php 20 21 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 22 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 23 24 @par Revision Reference: 25 This Protocol is defined in UEFI Platform Initialization Specification 1.2 26 Volume 5: Standards 27 28 **/ 29 30 #ifndef __CPU_IO2_H__ 31 #define __CPU_IO2_H__ 32 33 #define EFI_CPU_IO2_PROTOCOL_GUID \ 34 { \ 35 0xad61f191, 0xae5f, 0x4c0e, {0xb9, 0xfa, 0xe8, 0x69, 0xd2, 0x88, 0xc6, 0x4f} \ 36 } 37 38 typedef struct _EFI_CPU_IO2_PROTOCOL EFI_CPU_IO2_PROTOCOL; 39 40 /// 41 /// Enumeration that defines the width of the I/O operation. 42 /// 43 typedef enum { 44 EfiCpuIoWidthUint8, 45 EfiCpuIoWidthUint16, 46 EfiCpuIoWidthUint32, 47 EfiCpuIoWidthUint64, 48 EfiCpuIoWidthFifoUint8, 49 EfiCpuIoWidthFifoUint16, 50 EfiCpuIoWidthFifoUint32, 51 EfiCpuIoWidthFifoUint64, 52 EfiCpuIoWidthFillUint8, 53 EfiCpuIoWidthFillUint16, 54 EfiCpuIoWidthFillUint32, 55 EfiCpuIoWidthFillUint64, 56 EfiCpuIoWidthMaximum 57 } EFI_CPU_IO_PROTOCOL_WIDTH; 58 59 /** 60 Enables a driver to access registers in the PI CPU I/O space. 61 62 The Io.Read() and Io.Write() functions enable a driver to access PCI controller 63 registers in the PI CPU I/O space. 64 65 The I/O operations are carried out exactly as requested. The caller is responsible 66 for satisfying any alignment and I/O width restrictions that a PI System on a 67 platform might require. For example on some platforms, width requests of 68 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 69 be handled by the driver. 70 71 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, 72 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for 73 each of the Count operations that is performed. 74 75 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, 76 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is 77 incremented for each of the Count operations that is performed. The read or 78 write operation is performed Count times on the same Address. 79 80 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, 81 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is 82 incremented for each of the Count operations that is performed. The read or 83 write operation is performed Count times from the first element of Buffer. 84 85 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. 86 @param[in] Width Signifies the width of the I/O or Memory operation. 87 @param[in] Address The base address of the I/O operation. 88 @param[in] Count The number of I/O operations to perform. The number 89 of bytes moved is Width size * Count, starting at Address. 90 @param[in, out] Buffer For read operations, the destination buffer to store the results. 91 For write operations, the source buffer from which to write data. 92 93 @retval EFI_SUCCESS The data was read from or written to the PI system. 94 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. 95 @retval EFI_INVALID_PARAMETER Buffer is NULL. 96 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. 97 @retval EFI_UNSUPPORTED The address range specified by Address, Width, 98 and Count is not valid for this PI system. 99 100 **/ 101 typedef 102 EFI_STATUS 103 (EFIAPI *EFI_CPU_IO_PROTOCOL_IO_MEM)( 104 IN EFI_CPU_IO2_PROTOCOL *This, 105 IN EFI_CPU_IO_PROTOCOL_WIDTH Width, 106 IN UINT64 Address, 107 IN UINTN Count, 108 IN OUT VOID *Buffer 109 ); 110 111 /// 112 /// Service for read and write accesses. 113 /// 114 typedef struct { 115 /// 116 /// This service provides the various modalities of memory and I/O read. 117 /// 118 EFI_CPU_IO_PROTOCOL_IO_MEM Read; 119 /// 120 /// This service provides the various modalities of memory and I/O write. 121 /// 122 EFI_CPU_IO_PROTOCOL_IO_MEM Write; 123 } EFI_CPU_IO_PROTOCOL_ACCESS; 124 125 /// 126 /// Provides the basic memory and I/O interfaces that are used to abstract 127 /// accesses to devices in a system. 128 /// 129 struct _EFI_CPU_IO2_PROTOCOL { 130 /// 131 /// Enables a driver to access memory-mapped registers in the EFI system memory space. 132 /// 133 EFI_CPU_IO_PROTOCOL_ACCESS Mem; 134 /// 135 /// Enables a driver to access registers in the EFI CPU I/O space. 136 /// 137 EFI_CPU_IO_PROTOCOL_ACCESS Io; 138 }; 139 140 extern EFI_GUID gEfiCpuIo2ProtocolGuid; 141 142 #endif 143
