1 /** @file 2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. 3 4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 #include "PiSmmCpuDxeSmm.h" 16 17 // 18 // SMM CPU Private Data structure that contains SMM Configuration Protocol 19 // along its supporting fields. 20 // 21 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = { 22 SMM_CPU_PRIVATE_DATA_SIGNATURE, // Signature 23 NULL, // SmmCpuHandle 24 NULL, // Pointer to ProcessorInfo array 25 NULL, // Pointer to Operation array 26 NULL, // Pointer to CpuSaveStateSize array 27 NULL, // Pointer to CpuSaveState array 28 { {0} }, // SmmReservedSmramRegion 29 { 30 SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp 31 0, // SmmCoreEntryContext.CurrentlyExecutingCpu 32 0, // SmmCoreEntryContext.NumberOfCpus 33 NULL, // SmmCoreEntryContext.CpuSaveStateSize 34 NULL // SmmCoreEntryContext.CpuSaveState 35 }, 36 NULL, // SmmCoreEntry 37 { 38 mSmmCpuPrivateData.SmmReservedSmramRegion, // SmmConfiguration.SmramReservedRegions 39 RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry 40 }, 41 }; 42 43 CPU_HOT_PLUG_DATA mCpuHotPlugData = { 44 CPU_HOT_PLUG_DATA_REVISION_1, // Revision 45 0, // Array Length of SmBase and APIC ID 46 NULL, // Pointer to APIC ID array 47 NULL, // Pointer to SMBASE array 48 0, // Reserved 49 0, // SmrrBase 50 0 // SmrrSize 51 }; 52 53 // 54 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM 55 // 56 SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate = &mSmmCpuPrivateData; 57 58 // 59 // SMM Relocation variables 60 // 61 volatile BOOLEAN *mRebased; 62 volatile BOOLEAN mIsBsp; 63 64 /// 65 /// Handle for the SMM CPU Protocol 66 /// 67 EFI_HANDLE mSmmCpuHandle = NULL; 68 69 /// 70 /// SMM CPU Protocol instance 71 /// 72 EFI_SMM_CPU_PROTOCOL mSmmCpu = { 73 SmmReadSaveState, 74 SmmWriteSaveState 75 }; 76 77 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; 78 79 // 80 // SMM stack information 81 // 82 UINTN mSmmStackArrayBase; 83 UINTN mSmmStackArrayEnd; 84 UINTN mSmmStackSize; 85 86 UINTN mMaxNumberOfCpus = 1; 87 UINTN mNumberOfCpus = 1; 88 89 // 90 // SMM ready to lock flag 91 // 92 BOOLEAN mSmmReadyToLock = FALSE; 93 94 // 95 // Global used to cache PCD for SMM Code Access Check enable 96 // 97 BOOLEAN mSmmCodeAccessCheckEnable = FALSE; 98 99 // 100 // Spin lock used to serialize setting of SMM Code Access Check feature 101 // 102 SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL; 103 104 /** 105 Initialize IDT to setup exception handlers for SMM. 106 107 **/ 108 VOID 109 InitializeSmmIdt ( 110 VOID 111 ) 112 { 113 EFI_STATUS Status; 114 BOOLEAN InterruptState; 115 IA32_DESCRIPTOR DxeIdtr; 116 117 // 118 // There are 32 (not 255) entries in it since only processor 119 // generated exceptions will be handled. 120 // 121 gcSmiIdtr.Limit = (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 32) - 1; 122 // 123 // Allocate page aligned IDT, because it might be set as read only. 124 // 125 gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr.Limit + 1)); 126 ASSERT (gcSmiIdtr.Base != 0); 127 ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1); 128 129 // 130 // Disable Interrupt and save DXE IDT table 131 // 132 InterruptState = SaveAndDisableInterrupts (); 133 AsmReadIdtr (&DxeIdtr); 134 // 135 // Load SMM temporary IDT table 136 // 137 AsmWriteIdtr (&gcSmiIdtr); 138 // 139 // Setup SMM default exception handlers, SMM IDT table 140 // will be updated and saved in gcSmiIdtr 141 // 142 Status = InitializeCpuExceptionHandlers (NULL); 143 ASSERT_EFI_ERROR (Status); 144 // 145 // Restore DXE IDT table and CPU interrupt 146 // 147 AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr); 148 SetInterruptState (InterruptState); 149 } 150 151 /** 152 Search module name by input IP address and output it. 153 154 @param CallerIpAddress Caller instruction pointer. 155 156 **/ 157 VOID 158 DumpModuleInfoByIp ( 159 IN UINTN CallerIpAddress 160 ) 161 { 162 UINTN Pe32Data; 163 EFI_IMAGE_DOS_HEADER *DosHdr; 164 EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr; 165 VOID *PdbPointer; 166 UINT64 DumpIpAddress; 167 168 // 169 // Find Image Base 170 // 171 Pe32Data = CallerIpAddress & ~(SIZE_4KB - 1); 172 while (Pe32Data != 0) { 173 DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data; 174 if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) { 175 // 176 // DOS image header is present, so read the PE header after the DOS image header. 177 // 178 Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff)); 179 // 180 // Make sure PE header address does not overflow and is less than the initial address. 181 // 182 if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < CallerIpAddress)) { 183 if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) { 184 // 185 // It's PE image. 186 // 187 break; 188 } 189 } 190 } 191 192 // 193 // Not found the image base, check the previous aligned address 194 // 195 Pe32Data -= SIZE_4KB; 196 } 197 198 DumpIpAddress = CallerIpAddress; 199 DEBUG ((EFI_D_ERROR, "It is invoked from the instruction before IP(0x%lx)", DumpIpAddress)); 200 201 if (Pe32Data != 0) { 202 PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data); 203 if (PdbPointer != NULL) { 204 DEBUG ((EFI_D_ERROR, " in module (%a)", PdbPointer)); 205 } 206 } 207 } 208 209 /** 210 Read information from the CPU save state. 211 212 @param This EFI_SMM_CPU_PROTOCOL instance 213 @param Width The number of bytes to read from the CPU save state. 214 @param Register Specifies the CPU register to read form the save state. 215 @param CpuIndex Specifies the zero-based index of the CPU save state. 216 @param Buffer Upon return, this holds the CPU register value read from the save state. 217 218 @retval EFI_SUCCESS The register was read from Save State 219 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor 220 @retval EFI_INVALID_PARAMTER This or Buffer is NULL. 221 222 **/ 223 EFI_STATUS 224 EFIAPI 225 SmmReadSaveState ( 226 IN CONST EFI_SMM_CPU_PROTOCOL *This, 227 IN UINTN Width, 228 IN EFI_SMM_SAVE_STATE_REGISTER Register, 229 IN UINTN CpuIndex, 230 OUT VOID *Buffer 231 ) 232 { 233 EFI_STATUS Status; 234 235 // 236 // Retrieve pointer to the specified CPU's SMM Save State buffer 237 // 238 if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) { 239 return EFI_INVALID_PARAMETER; 240 } 241 242 // 243 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID 244 // 245 if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) { 246 // 247 // The pseudo-register only supports the 64-bit size specified by Width. 248 // 249 if (Width != sizeof (UINT64)) { 250 return EFI_INVALID_PARAMETER; 251 } 252 // 253 // If the processor is in SMM at the time the SMI occurred, 254 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer. 255 // Otherwise, EFI_NOT_FOUND is returned. 256 // 257 if (*(mSmmMpSyncData->CpuData[CpuIndex].Present)) { 258 *(UINT64 *)Buffer = gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId; 259 return EFI_SUCCESS; 260 } else { 261 return EFI_NOT_FOUND; 262 } 263 } 264 265 if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) { 266 return EFI_INVALID_PARAMETER; 267 } 268 269 Status = SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer); 270 if (Status == EFI_UNSUPPORTED) { 271 Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer); 272 } 273 return Status; 274 } 275 276 /** 277 Write data to the CPU save state. 278 279 @param This EFI_SMM_CPU_PROTOCOL instance 280 @param Width The number of bytes to read from the CPU save state. 281 @param Register Specifies the CPU register to write to the save state. 282 @param CpuIndex Specifies the zero-based index of the CPU save state 283 @param Buffer Upon entry, this holds the new CPU register value. 284 285 @retval EFI_SUCCESS The register was written from Save State 286 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor 287 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct 288 289 **/ 290 EFI_STATUS 291 EFIAPI 292 SmmWriteSaveState ( 293 IN CONST EFI_SMM_CPU_PROTOCOL *This, 294 IN UINTN Width, 295 IN EFI_SMM_SAVE_STATE_REGISTER Register, 296 IN UINTN CpuIndex, 297 IN CONST VOID *Buffer 298 ) 299 { 300 EFI_STATUS Status; 301 302 // 303 // Retrieve pointer to the specified CPU's SMM Save State buffer 304 // 305 if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) { 306 return EFI_INVALID_PARAMETER; 307 } 308 309 // 310 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored 311 // 312 if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) { 313 return EFI_SUCCESS; 314 } 315 316 if (!mSmmMpSyncData->CpuData[CpuIndex].Present) { 317 return EFI_INVALID_PARAMETER; 318 } 319 320 Status = SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer); 321 if (Status == EFI_UNSUPPORTED) { 322 Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer); 323 } 324 return Status; 325 } 326 327 328 /** 329 C function for SMI handler. To change all processor's SMMBase Register. 330 331 **/ 332 VOID 333 EFIAPI 334 SmmInitHandler ( 335 VOID 336 ) 337 { 338 UINT32 ApicId; 339 UINTN Index; 340 341 // 342 // Update SMM IDT entries' code segment and load IDT 343 // 344 AsmWriteIdtr (&gcSmiIdtr); 345 ApicId = GetApicId (); 346 347 ASSERT (mNumberOfCpus <= mMaxNumberOfCpus); 348 349 for (Index = 0; Index < mNumberOfCpus; Index++) { 350 if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) { 351 // 352 // Initialize SMM specific features on the currently executing CPU 353 // 354 SmmCpuFeaturesInitializeProcessor ( 355 Index, 356 mIsBsp, 357 gSmmCpuPrivate->ProcessorInfo, 358 &mCpuHotPlugData 359 ); 360 361 if (!mSmmS3Flag) { 362 // 363 // Check XD and BTS features on each processor on normal boot 364 // 365 CheckFeatureSupported (); 366 } 367 368 if (mIsBsp) { 369 // 370 // BSP rebase is already done above. 371 // Initialize private data during S3 resume 372 // 373 InitializeMpSyncData (); 374 } 375 376 // 377 // Hook return after RSM to set SMM re-based flag 378 // 379 SemaphoreHook (Index, &mRebased[Index]); 380 381 return; 382 } 383 } 384 ASSERT (FALSE); 385 } 386 387 /** 388 Relocate SmmBases for each processor. 389 390 Execute on first boot and all S3 resumes 391 392 **/ 393 VOID 394 EFIAPI 395 SmmRelocateBases ( 396 VOID 397 ) 398 { 399 UINT8 BakBuf[BACK_BUF_SIZE]; 400 SMRAM_SAVE_STATE_MAP BakBuf2; 401 SMRAM_SAVE_STATE_MAP *CpuStatePtr; 402 UINT8 *U8Ptr; 403 UINT32 ApicId; 404 UINTN Index; 405 UINTN BspIndex; 406 407 // 408 // Make sure the reserved size is large enough for procedure SmmInitTemplate. 409 // 410 ASSERT (sizeof (BakBuf) >= gcSmmInitSize); 411 412 // 413 // Patch ASM code template with current CR0, CR3, and CR4 values 414 // 415 gSmmCr0 = (UINT32)AsmReadCr0 (); 416 gSmmCr3 = (UINT32)AsmReadCr3 (); 417 gSmmCr4 = (UINT32)AsmReadCr4 (); 418 419 // 420 // Patch GDTR for SMM base relocation 421 // 422 gcSmiInitGdtr.Base = gcSmiGdtr.Base; 423 gcSmiInitGdtr.Limit = gcSmiGdtr.Limit; 424 425 U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET); 426 CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); 427 428 // 429 // Backup original contents at address 0x38000 430 // 431 CopyMem (BakBuf, U8Ptr, sizeof (BakBuf)); 432 CopyMem (&BakBuf2, CpuStatePtr, sizeof (BakBuf2)); 433 434 // 435 // Load image for relocation 436 // 437 CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize); 438 439 // 440 // Retrieve the local APIC ID of current processor 441 // 442 ApicId = GetApicId (); 443 444 // 445 // Relocate SM bases for all APs 446 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate 447 // 448 mIsBsp = FALSE; 449 BspIndex = (UINTN)-1; 450 for (Index = 0; Index < mNumberOfCpus; Index++) { 451 mRebased[Index] = FALSE; 452 if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) { 453 SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId); 454 // 455 // Wait for this AP to finish its 1st SMI 456 // 457 while (!mRebased[Index]); 458 } else { 459 // 460 // BSP will be Relocated later 461 // 462 BspIndex = Index; 463 } 464 } 465 466 // 467 // Relocate BSP's SMM base 468 // 469 ASSERT (BspIndex != (UINTN)-1); 470 mIsBsp = TRUE; 471 SendSmiIpi (ApicId); 472 // 473 // Wait for the BSP to finish its 1st SMI 474 // 475 while (!mRebased[BspIndex]); 476 477 // 478 // Restore contents at address 0x38000 479 // 480 CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2)); 481 CopyMem (U8Ptr, BakBuf, sizeof (BakBuf)); 482 } 483 484 /** 485 SMM Ready To Lock event notification handler. 486 487 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to 488 perform additional lock actions that must be performed from SMM on the next SMI. 489 490 @param[in] Protocol Points to the protocol's unique identifier. 491 @param[in] Interface Points to the interface instance. 492 @param[in] Handle The handle on which the interface was installed. 493 494 @retval EFI_SUCCESS Notification handler runs successfully. 495 **/ 496 EFI_STATUS 497 EFIAPI 498 SmmReadyToLockEventNotify ( 499 IN CONST EFI_GUID *Protocol, 500 IN VOID *Interface, 501 IN EFI_HANDLE Handle 502 ) 503 { 504 GetAcpiCpuData (); 505 506 // 507 // Cache a copy of UEFI memory map before we start profiling feature. 508 // 509 GetUefiMemoryMap (); 510 511 // 512 // Set SMM ready to lock flag and return 513 // 514 mSmmReadyToLock = TRUE; 515 return EFI_SUCCESS; 516 } 517 518 /** 519 The module Entry Point of the CPU SMM driver. 520 521 @param ImageHandle The firmware allocated handle for the EFI image. 522 @param SystemTable A pointer to the EFI System Table. 523 524 @retval EFI_SUCCESS The entry point is executed successfully. 525 @retval Other Some error occurs when executing this entry point. 526 527 **/ 528 EFI_STATUS 529 EFIAPI 530 PiCpuSmmEntry ( 531 IN EFI_HANDLE ImageHandle, 532 IN EFI_SYSTEM_TABLE *SystemTable 533 ) 534 { 535 EFI_STATUS Status; 536 EFI_MP_SERVICES_PROTOCOL *MpServices; 537 UINTN NumberOfEnabledProcessors; 538 UINTN Index; 539 VOID *Buffer; 540 UINTN BufferPages; 541 UINTN TileCodeSize; 542 UINTN TileDataSize; 543 UINTN TileSize; 544 UINT8 *Stacks; 545 VOID *Registration; 546 UINT32 RegEax; 547 UINT32 RegEdx; 548 UINTN FamilyId; 549 UINTN ModelId; 550 UINT32 Cr3; 551 552 // 553 // Initialize Debug Agent to support source level debug in SMM code 554 // 555 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL); 556 557 // 558 // Report the start of CPU SMM initialization. 559 // 560 REPORT_STATUS_CODE ( 561 EFI_PROGRESS_CODE, 562 EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT 563 ); 564 565 // 566 // Fix segment address of the long-mode-switch jump 567 // 568 if (sizeof (UINTN) == sizeof (UINT64)) { 569 gSmmJmpAddr.Segment = LONG_MODE_CODE_SEGMENT; 570 } 571 572 // 573 // Find out SMRR Base and SMRR Size 574 // 575 FindSmramInfo (&mCpuHotPlugData.SmrrBase, &mCpuHotPlugData.SmrrSize); 576 577 // 578 // Get MP Services Protocol 579 // 580 Status = SystemTable->BootServices->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices); 581 ASSERT_EFI_ERROR (Status); 582 583 // 584 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors 585 // 586 Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus, &NumberOfEnabledProcessors); 587 ASSERT_EFI_ERROR (Status); 588 ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber)); 589 590 // 591 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE. 592 // A constant BSP index makes no sense because it may be hot removed. 593 // 594 DEBUG_CODE ( 595 if (FeaturePcdGet (PcdCpuHotPlugSupport)) { 596 597 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection)); 598 } 599 ); 600 601 // 602 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable. 603 // 604 mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable); 605 DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable)); 606 607 // 608 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors 609 // 610 if (FeaturePcdGet (PcdCpuHotPlugSupport)) { 611 mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber); 612 } else { 613 mMaxNumberOfCpus = mNumberOfCpus; 614 } 615 gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus; 616 617 // 618 // The CPU save state and code for the SMI entry point are tiled within an SMRAM 619 // allocated buffer. The minimum size of this buffer for a uniprocessor system 620 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area 621 // just below SMBASE + 64KB. If more than one CPU is present in the platform, 622 // then the SMI entry point and the CPU save state areas can be tiles to minimize 623 // the total amount SMRAM required for all the CPUs. The tile size can be computed 624 // by adding the // CPU save state size, any extra CPU specific context, and 625 // the size of code that must be placed at the SMI entry point to transfer 626 // control to a C function in the native SMM execution mode. This size is 627 // rounded up to the nearest power of 2 to give the tile size for a each CPU. 628 // The total amount of memory required is the maximum number of CPUs that 629 // platform supports times the tile size. The picture below shows the tiling, 630 // where m is the number of tiles that fit in 32KB. 631 // 632 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer 633 // | CPU m+1 Save State | 634 // +-----------------------------+ 635 // | CPU m+1 Extra Data | 636 // +-----------------------------+ 637 // | Padding | 638 // +-----------------------------+ 639 // | CPU 2m SMI Entry | 640 // +#############################+ <-- Base of allocated buffer + 64 KB 641 // | CPU m-1 Save State | 642 // +-----------------------------+ 643 // | CPU m-1 Extra Data | 644 // +-----------------------------+ 645 // | Padding | 646 // +-----------------------------+ 647 // | CPU 2m-1 SMI Entry | 648 // +=============================+ <-- 2^n offset from Base of allocated buffer 649 // | . . . . . . . . . . . . | 650 // +=============================+ <-- 2^n offset from Base of allocated buffer 651 // | CPU 2 Save State | 652 // +-----------------------------+ 653 // | CPU 2 Extra Data | 654 // +-----------------------------+ 655 // | Padding | 656 // +-----------------------------+ 657 // | CPU m+1 SMI Entry | 658 // +=============================+ <-- Base of allocated buffer + 32 KB 659 // | CPU 1 Save State | 660 // +-----------------------------+ 661 // | CPU 1 Extra Data | 662 // +-----------------------------+ 663 // | Padding | 664 // +-----------------------------+ 665 // | CPU m SMI Entry | 666 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB 667 // | CPU 0 Save State | 668 // +-----------------------------+ 669 // | CPU 0 Extra Data | 670 // +-----------------------------+ 671 // | Padding | 672 // +-----------------------------+ 673 // | CPU m-1 SMI Entry | 674 // +=============================+ <-- 2^n offset from Base of allocated buffer 675 // | . . . . . . . . . . . . | 676 // +=============================+ <-- 2^n offset from Base of allocated buffer 677 // | Padding | 678 // +-----------------------------+ 679 // | CPU 1 SMI Entry | 680 // +=============================+ <-- 2^n offset from Base of allocated buffer 681 // | Padding | 682 // +-----------------------------+ 683 // | CPU 0 SMI Entry | 684 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB 685 // 686 687 // 688 // Retrieve CPU Family 689 // 690 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL); 691 FamilyId = (RegEax >> 8) & 0xf; 692 ModelId = (RegEax >> 4) & 0xf; 693 if (FamilyId == 0x06 || FamilyId == 0x0f) { 694 ModelId = ModelId | ((RegEax >> 12) & 0xf0); 695 } 696 697 RegEdx = 0; 698 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); 699 if (RegEax >= CPUID_EXTENDED_CPU_SIG) { 700 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx); 701 } 702 // 703 // Determine the mode of the CPU at the time an SMI occurs 704 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual 705 // Volume 3C, Section 34.4.1.1 706 // 707 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; 708 if ((RegEdx & BIT29) != 0) { 709 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; 710 } 711 if (FamilyId == 0x06) { 712 if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) { 713 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; 714 } 715 } 716 717 // 718 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU 719 // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point. 720 // This size is rounded up to nearest power of 2. 721 // 722 TileCodeSize = GetSmiHandlerSize (); 723 TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB); 724 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); 725 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); 726 TileSize = TileDataSize + TileCodeSize - 1; 727 TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); 728 DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); 729 730 // 731 // If the TileSize is larger than space available for the SMI Handler of 732 // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save 733 // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then 734 // the SMI Handler size must be reduced or the size of the extra CPU specific 735 // context must be reduced. 736 // 737 ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET)); 738 739 // 740 // Allocate buffer for all of the tiles. 741 // 742 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual 743 // Volume 3C, Section 34.11 SMBASE Relocation 744 // For Pentium and Intel486 processors, the SMBASE values must be 745 // aligned on a 32-KByte boundary or the processor will enter shutdown 746 // state during the execution of a RSM instruction. 747 // 748 // Intel486 processors: FamilyId is 4 749 // Pentium processors : FamilyId is 5 750 // 751 BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1)); 752 if ((FamilyId == 4) || (FamilyId == 5)) { 753 Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB); 754 } else { 755 Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB); 756 } 757 ASSERT (Buffer != NULL); 758 DEBUG ((EFI_D_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages))); 759 760 // 761 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA. 762 // 763 gSmmCpuPrivate->ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus); 764 ASSERT (gSmmCpuPrivate->ProcessorInfo != NULL); 765 766 gSmmCpuPrivate->Operation = (SMM_CPU_OPERATION *)AllocatePool (sizeof (SMM_CPU_OPERATION) * mMaxNumberOfCpus); 767 ASSERT (gSmmCpuPrivate->Operation != NULL); 768 769 gSmmCpuPrivate->CpuSaveStateSize = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus); 770 ASSERT (gSmmCpuPrivate->CpuSaveStateSize != NULL); 771 772 gSmmCpuPrivate->CpuSaveState = (VOID **)AllocatePool (sizeof (VOID *) * mMaxNumberOfCpus); 773 ASSERT (gSmmCpuPrivate->CpuSaveState != NULL); 774 775 mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize; 776 mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState = gSmmCpuPrivate->CpuSaveState; 777 778 // 779 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA. 780 // 781 mCpuHotPlugData.ApicId = (UINT64 *)AllocatePool (sizeof (UINT64) * mMaxNumberOfCpus); 782 ASSERT (mCpuHotPlugData.ApicId != NULL); 783 mCpuHotPlugData.SmBase = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus); 784 ASSERT (mCpuHotPlugData.SmBase != NULL); 785 mCpuHotPlugData.ArrayLength = (UINT32)mMaxNumberOfCpus; 786 787 // 788 // Retrieve APIC ID of each enabled processor from the MP Services protocol. 789 // Also compute the SMBASE address, CPU Save State address, and CPU Save state 790 // size for each CPU in the platform 791 // 792 for (Index = 0; Index < mMaxNumberOfCpus; Index++) { 793 mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; 794 gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP); 795 gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); 796 gSmmCpuPrivate->Operation[Index] = SmmCpuNone; 797 798 if (Index < mNumberOfCpus) { 799 Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]); 800 ASSERT_EFI_ERROR (Status); 801 mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId; 802 803 DEBUG ((EFI_D_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n", 804 Index, 805 (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId, 806 mCpuHotPlugData.SmBase[Index], 807 gSmmCpuPrivate->CpuSaveState[Index], 808 gSmmCpuPrivate->CpuSaveStateSize[Index] 809 )); 810 } else { 811 gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID; 812 mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID; 813 } 814 } 815 816 // 817 // Allocate SMI stacks for all processors. 818 // 819 if (FeaturePcdGet (PcdCpuSmmStackGuard)) { 820 // 821 // 2 more pages is allocated for each processor. 822 // one is guard page and the other is known good stack. 823 // 824 // +-------------------------------------------+-----+-------------------------------------------+ 825 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack | 826 // +-------------------------------------------+-----+-------------------------------------------+ 827 // | | | | 828 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->| 829 // 830 mSmmStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2); 831 Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2)); 832 ASSERT (Stacks != NULL); 833 mSmmStackArrayBase = (UINTN)Stacks; 834 mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize - 1; 835 } else { 836 mSmmStackSize = PcdGet32 (PcdCpuSmmStackSize); 837 Stacks = (UINT8 *) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize)); 838 ASSERT (Stacks != NULL); 839 } 840 841 // 842 // Set SMI stack for SMM base relocation 843 // 844 gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)); 845 846 // 847 // Initialize IDT 848 // 849 InitializeSmmIdt (); 850 851 // 852 // Relocate SMM Base addresses to the ones allocated from SMRAM 853 // 854 mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus); 855 ASSERT (mRebased != NULL); 856 SmmRelocateBases (); 857 858 // 859 // Call hook for BSP to perform extra actions in normal mode after all 860 // SMM base addresses have been relocated on all CPUs 861 // 862 SmmCpuFeaturesSmmRelocationComplete (); 863 864 DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported)); 865 866 // 867 // SMM Time initialization 868 // 869 InitializeSmmTimer (); 870 871 // 872 // Initialize MP globals 873 // 874 Cr3 = InitializeMpServiceData (Stacks, mSmmStackSize); 875 876 // 877 // Fill in SMM Reserved Regions 878 // 879 gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0; 880 gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize = 0; 881 882 // 883 // Install the SMM Configuration Protocol onto a new handle on the handle database. 884 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer 885 // to an SMRAM address will be present in the handle database 886 // 887 Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces ( 888 &gSmmCpuPrivate->SmmCpuHandle, 889 &gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration, 890 NULL 891 ); 892 ASSERT_EFI_ERROR (Status); 893 894 // 895 // Install the SMM CPU Protocol into SMM protocol database 896 // 897 Status = gSmst->SmmInstallProtocolInterface ( 898 &mSmmCpuHandle, 899 &gEfiSmmCpuProtocolGuid, 900 EFI_NATIVE_INTERFACE, 901 &mSmmCpu 902 ); 903 ASSERT_EFI_ERROR (Status); 904 905 // 906 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported. 907 // 908 if (FeaturePcdGet (PcdCpuHotPlugSupport)) { 909 Status = PcdSet64S (PcdCpuHotPlugDataAddress, (UINT64)(UINTN)&mCpuHotPlugData); 910 ASSERT_EFI_ERROR (Status); 911 } 912 913 // 914 // Initialize SMM CPU Services Support 915 // 916 Status = InitializeSmmCpuServices (mSmmCpuHandle); 917 ASSERT_EFI_ERROR (Status); 918 919 // 920 // register SMM Ready To Lock Protocol notification 921 // 922 Status = gSmst->SmmRegisterProtocolNotify ( 923 &gEfiSmmReadyToLockProtocolGuid, 924 SmmReadyToLockEventNotify, 925 &Registration 926 ); 927 ASSERT_EFI_ERROR (Status); 928 929 // 930 // Initialize SMM Profile feature 931 // 932 InitSmmProfile (Cr3); 933 934 GetAcpiS3EnableFlag (); 935 InitSmmS3ResumeState (Cr3); 936 937 DEBUG ((EFI_D_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n")); 938 939 return EFI_SUCCESS; 940 } 941 942 /** 943 944 Find out SMRAM information including SMRR base and SMRR size. 945 946 @param SmrrBase SMRR base 947 @param SmrrSize SMRR size 948 949 **/ 950 VOID 951 FindSmramInfo ( 952 OUT UINT32 *SmrrBase, 953 OUT UINT32 *SmrrSize 954 ) 955 { 956 EFI_STATUS Status; 957 UINTN Size; 958 EFI_SMM_ACCESS2_PROTOCOL *SmmAccess; 959 EFI_SMRAM_DESCRIPTOR *CurrentSmramRange; 960 EFI_SMRAM_DESCRIPTOR *SmramRanges; 961 UINTN SmramRangeCount; 962 UINTN Index; 963 UINT64 MaxSize; 964 BOOLEAN Found; 965 966 // 967 // Get SMM Access Protocol 968 // 969 Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess); 970 ASSERT_EFI_ERROR (Status); 971 972 // 973 // Get SMRAM information 974 // 975 Size = 0; 976 Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL); 977 ASSERT (Status == EFI_BUFFER_TOO_SMALL); 978 979 SmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size); 980 ASSERT (SmramRanges != NULL); 981 982 Status = SmmAccess->GetCapabilities (SmmAccess, &Size, SmramRanges); 983 ASSERT_EFI_ERROR (Status); 984 985 SmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR); 986 987 // 988 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size 989 // 990 CurrentSmramRange = NULL; 991 for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < SmramRangeCount; Index++) { 992 // 993 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization 994 // 995 if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) { 996 continue; 997 } 998 999 if (SmramRanges[Index].CpuStart >= BASE_1MB) { 1000 if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) <= BASE_4GB) { 1001 if (SmramRanges[Index].PhysicalSize >= MaxSize) { 1002 MaxSize = SmramRanges[Index].PhysicalSize; 1003 CurrentSmramRange = &SmramRanges[Index]; 1004 } 1005 } 1006 } 1007 } 1008 1009 ASSERT (CurrentSmramRange != NULL); 1010 1011 *SmrrBase = (UINT32)CurrentSmramRange->CpuStart; 1012 *SmrrSize = (UINT32)CurrentSmramRange->PhysicalSize; 1013 1014 do { 1015 Found = FALSE; 1016 for (Index = 0; Index < SmramRangeCount; Index++) { 1017 if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase == (SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) { 1018 *SmrrBase = (UINT32)SmramRanges[Index].CpuStart; 1019 *SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize); 1020 Found = TRUE; 1021 } else if ((*SmrrBase + *SmrrSize) == SmramRanges[Index].CpuStart && SmramRanges[Index].PhysicalSize > 0) { 1022 *SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize); 1023 Found = TRUE; 1024 } 1025 } 1026 } while (Found); 1027 1028 FreePool (SmramRanges); 1029 DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize)); 1030 } 1031 1032 /** 1033 Configure SMM Code Access Check feature on an AP. 1034 SMM Feature Control MSR will be locked after configuration. 1035 1036 @param[in,out] Buffer Pointer to private data buffer. 1037 **/ 1038 VOID 1039 EFIAPI 1040 ConfigSmmCodeAccessCheckOnCurrentProcessor ( 1041 IN OUT VOID *Buffer 1042 ) 1043 { 1044 UINTN CpuIndex; 1045 UINT64 SmmFeatureControlMsr; 1046 UINT64 NewSmmFeatureControlMsr; 1047 1048 // 1049 // Retrieve the CPU Index from the context passed in 1050 // 1051 CpuIndex = *(UINTN *)Buffer; 1052 1053 // 1054 // Get the current SMM Feature Control MSR value 1055 // 1056 SmmFeatureControlMsr = SmmCpuFeaturesGetSmmRegister (CpuIndex, SmmRegFeatureControl); 1057 1058 // 1059 // Compute the new SMM Feature Control MSR value 1060 // 1061 NewSmmFeatureControlMsr = SmmFeatureControlMsr; 1062 if (mSmmCodeAccessCheckEnable) { 1063 NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT; 1064 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) { 1065 NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT; 1066 } 1067 } 1068 1069 // 1070 // Only set the SMM Feature Control MSR value if the new value is different than the current value 1071 // 1072 if (NewSmmFeatureControlMsr != SmmFeatureControlMsr) { 1073 SmmCpuFeaturesSetSmmRegister (CpuIndex, SmmRegFeatureControl, NewSmmFeatureControlMsr); 1074 } 1075 1076 // 1077 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR 1078 // 1079 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock); 1080 } 1081 1082 /** 1083 Configure SMM Code Access Check feature for all processors. 1084 SMM Feature Control MSR will be locked after configuration. 1085 **/ 1086 VOID 1087 ConfigSmmCodeAccessCheck ( 1088 VOID 1089 ) 1090 { 1091 UINTN Index; 1092 EFI_STATUS Status; 1093 1094 // 1095 // Check to see if the Feature Control MSR is supported on this CPU 1096 // 1097 Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu; 1098 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) { 1099 mSmmCodeAccessCheckEnable = FALSE; 1100 return; 1101 } 1102 1103 // 1104 // Check to see if the CPU supports the SMM Code Access Check feature 1105 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl 1106 // 1107 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) { 1108 mSmmCodeAccessCheckEnable = FALSE; 1109 return; 1110 } 1111 1112 // 1113 // Initialize the lock used to serialize the MSR programming in BSP and all APs 1114 // 1115 InitializeSpinLock (mConfigSmmCodeAccessCheckLock); 1116 1117 // 1118 // Acquire Config SMM Code Access Check spin lock. The BSP will release the 1119 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor(). 1120 // 1121 AcquireSpinLock (mConfigSmmCodeAccessCheckLock); 1122 1123 // 1124 // Enable SMM Code Access Check feature on the BSP. 1125 // 1126 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index); 1127 1128 // 1129 // Enable SMM Code Access Check feature for the APs. 1130 // 1131 for (Index = 0; Index < gSmst->NumberOfCpus; Index++) { 1132 if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) { 1133 1134 // 1135 // Acquire Config SMM Code Access Check spin lock. The AP will release the 1136 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor(). 1137 // 1138 AcquireSpinLock (mConfigSmmCodeAccessCheckLock); 1139 1140 // 1141 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP. 1142 // 1143 Status = gSmst->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor, Index, &Index); 1144 ASSERT_EFI_ERROR (Status); 1145 1146 // 1147 // Wait for the AP to release the Config SMM Code Access Check spin lock. 1148 // 1149 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock)) { 1150 CpuPause (); 1151 } 1152 1153 // 1154 // Release the Config SMM Code Access Check spin lock. 1155 // 1156 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock); 1157 } 1158 } 1159 } 1160 1161 /** 1162 This API provides a way to allocate memory for page table. 1163 1164 This API can be called more once to allocate memory for page tables. 1165 1166 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the 1167 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL 1168 is returned. If there is not enough memory remaining to satisfy the request, then NULL is 1169 returned. 1170 1171 @param Pages The number of 4 KB pages to allocate. 1172 1173 @return A pointer to the allocated buffer or NULL if allocation fails. 1174 1175 **/ 1176 VOID * 1177 AllocatePageTableMemory ( 1178 IN UINTN Pages 1179 ) 1180 { 1181 VOID *Buffer; 1182 1183 Buffer = SmmCpuFeaturesAllocatePageTableMemory (Pages); 1184 if (Buffer != NULL) { 1185 return Buffer; 1186 } 1187 return AllocatePages (Pages); 1188 } 1189 1190 /** 1191 Allocate pages for code. 1192 1193 @param[in] Pages Number of pages to be allocated. 1194 1195 @return Allocated memory. 1196 **/ 1197 VOID * 1198 AllocateCodePages ( 1199 IN UINTN Pages 1200 ) 1201 { 1202 EFI_STATUS Status; 1203 EFI_PHYSICAL_ADDRESS Memory; 1204 1205 if (Pages == 0) { 1206 return NULL; 1207 } 1208 1209 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory); 1210 if (EFI_ERROR (Status)) { 1211 return NULL; 1212 } 1213 return (VOID *) (UINTN) Memory; 1214 } 1215 1216 /** 1217 Allocate aligned pages for code. 1218 1219 @param[in] Pages Number of pages to be allocated. 1220 @param[in] Alignment The requested alignment of the allocation. 1221 Must be a power of two. 1222 If Alignment is zero, then byte alignment is used. 1223 1224 @return Allocated memory. 1225 **/ 1226 VOID * 1227 AllocateAlignedCodePages ( 1228 IN UINTN Pages, 1229 IN UINTN Alignment 1230 ) 1231 { 1232 EFI_STATUS Status; 1233 EFI_PHYSICAL_ADDRESS Memory; 1234 UINTN AlignedMemory; 1235 UINTN AlignmentMask; 1236 UINTN UnalignedPages; 1237 UINTN RealPages; 1238 1239 // 1240 // Alignment must be a power of two or zero. 1241 // 1242 ASSERT ((Alignment & (Alignment - 1)) == 0); 1243 1244 if (Pages == 0) { 1245 return NULL; 1246 } 1247 if (Alignment > EFI_PAGE_SIZE) { 1248 // 1249 // Calculate the total number of pages since alignment is larger than page size. 1250 // 1251 AlignmentMask = Alignment - 1; 1252 RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment); 1253 // 1254 // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow. 1255 // 1256 ASSERT (RealPages > Pages); 1257 1258 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory); 1259 if (EFI_ERROR (Status)) { 1260 return NULL; 1261 } 1262 AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask; 1263 UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory); 1264 if (UnalignedPages > 0) { 1265 // 1266 // Free first unaligned page(s). 1267 // 1268 Status = gSmst->SmmFreePages (Memory, UnalignedPages); 1269 ASSERT_EFI_ERROR (Status); 1270 } 1271 Memory = (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_TO_SIZE (Pages)); 1272 UnalignedPages = RealPages - Pages - UnalignedPages; 1273 if (UnalignedPages > 0) { 1274 // 1275 // Free last unaligned page(s). 1276 // 1277 Status = gSmst->SmmFreePages (Memory, UnalignedPages); 1278 ASSERT_EFI_ERROR (Status); 1279 } 1280 } else { 1281 // 1282 // Do not over-allocate pages in this case. 1283 // 1284 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory); 1285 if (EFI_ERROR (Status)) { 1286 return NULL; 1287 } 1288 AlignedMemory = (UINTN) Memory; 1289 } 1290 return (VOID *) AlignedMemory; 1291 } 1292 1293 /** 1294 Perform the remaining tasks. 1295 1296 **/ 1297 VOID 1298 PerformRemainingTasks ( 1299 VOID 1300 ) 1301 { 1302 if (mSmmReadyToLock) { 1303 // 1304 // Start SMM Profile feature 1305 // 1306 if (FeaturePcdGet (PcdCpuSmmProfileEnable)) { 1307 SmmProfileStart (); 1308 } 1309 // 1310 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable. 1311 // 1312 InitPaging (); 1313 1314 // 1315 // Mark critical region to be read-only in page table 1316 // 1317 SetMemMapAttributes (); 1318 1319 // 1320 // For outside SMRAM, we only map SMM communication buffer or MMIO. 1321 // 1322 SetUefiMemMapAttributes (); 1323 1324 // 1325 // Set page table itself to be read-only 1326 // 1327 SetPageTableAttributes (); 1328 1329 // 1330 // Configure SMM Code Access Check feature if available. 1331 // 1332 ConfigSmmCodeAccessCheck (); 1333 1334 SmmCpuFeaturesCompleteSmmReadyToLock (); 1335 1336 // 1337 // Clean SMM ready to lock flag 1338 // 1339 mSmmReadyToLock = FALSE; 1340 } 1341 } 1342 1343 /** 1344 Perform the pre tasks. 1345 1346 **/ 1347 VOID 1348 PerformPreTasks ( 1349 VOID 1350 ) 1351 { 1352 RestoreSmmConfigurationInS3 (); 1353 } 1354
