1 2 TITLE Cpu.asm: Assembly code for the x64 resources 3 4 ; 5 ; This file contains an 'Intel Sample Driver' and is 6 ; licensed for Intel CPUs and chipsets under the terms of your 7 ; license agreement with Intel or your vendor. This file may 8 ; be modified by the user, subject to additional terms of the 9 ; license agreement 10 ; 11 ; 12 ; Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved 13 ; 15 ; This program and the accompanying materials are licensed and made available under 17 ; the terms and conditions of the BSD License that accompanies this distribution. 19 ; The full text of the license may be found at 21 ; http://opensource.org/licenses/bsd-license.php. 23 ; 25 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 27 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 29 ; 31 ; 32 ; 33 ; 34 ; 35 ;* Module Name: 36 ;* 37 ;* Cpu.asm 38 ;* 39 ;* Abstract: 40 ;* 41 ;------------------------------------------------------------------------------ 42 43 text SEGMENT 44 45 46 ;------------------------------------------------------------------------------ 47 ; VOID 48 ; EfiHalt ( 49 ; VOID 50 ; ) 51 ;------------------------------------------------------------------------------ 52 EfiHalt PROC PUBLIC 53 hlt 54 ret 55 EfiHalt ENDP 56 57 58 ;------------------------------------------------------------------------------ 59 ; VOID 60 ; EfiWbinvd ( 61 ; VOID 62 ; ) 63 ;------------------------------------------------------------------------------ 64 EfiWbinvd PROC PUBLIC 65 wbinvd 66 ret 67 EfiWbinvd ENDP 68 69 70 ;------------------------------------------------------------------------------ 71 ; VOID 72 ; EfiInvd ( 73 ; VOID 74 ; ) 75 ;------------------------------------------------------------------------------ 76 EfiInvd PROC PUBLIC 77 invd 78 ret 79 EfiInvd ENDP 80 81 ;------------------------------------------------------------------------------ 82 ; VOID 83 ; EfiCpuid ( 84 ; IN UINT32 RegisterInEax, // rcx 85 ; OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx 86 ; ) 87 ;------------------------------------------------------------------------------ 88 EfiCpuid PROC PUBLIC 89 push rbx 90 91 mov r8, rdx ; r8 = *Reg 92 mov rax, rcx ; RegisterInEax 93 cpuid 94 cmp r8, 0 95 je _Exit 96 mov [r8 + 0], eax ; Reg->RegEax 97 mov [r8 + 4], ebx ; Reg->RegEbx 98 mov [r8 + 8], ecx ; Reg->RegEcx 99 mov [r8 + 12], edx ; Reg->RegEdx 100 101 _Exit: 102 pop rbx 103 ret 104 EfiCpuid ENDP 105 106 ;------------------------------------------------------------------------------ 107 ; UINT64 108 ; EfiReadMsr ( 109 ; IN UINT32 Index, // rcx 110 ; ) 111 ;------------------------------------------------------------------------------ 112 EfiReadMsr PROC PUBLIC 113 rdmsr 114 sal rdx, 32 ; edx:eax -> rax 115 or rax, rdx ; rax = edx:eax 116 ret 117 EfiReadMsr ENDP 118 119 ;------------------------------------------------------------------------------ 120 ; VOID 121 ; EfiWriteMsr ( 122 ; IN UINT32 Index, // rcx 123 ; IN UINT64 Value // rdx 124 ; ) 125 ;------------------------------------------------------------------------------ 126 EfiWriteMsr PROC PUBLIC 127 mov rax, rdx ; rdx = Value 128 sar rdx, 32 ; convert rdx to edx upper 32-bits 129 wrmsr ; wrmsr[ecx] result = edx:eax 130 ret 131 EfiWriteMsr ENDP 132 133 134 ;------------------------------------------------------------------------------ 135 ; UINT64 136 ; EfiReadTsc ( 137 ; VOID 138 ; ); 139 ;------------------------------------------------------------------------------ 140 EfiReadTsc PROC PUBLIC 141 rdtsc 142 shl rax, 32 143 shrd rax, rdx, 32 144 ret 145 EfiReadTsc ENDP 146 147 ;------------------------------------------------------------------------------ 148 ; VOID 149 ; EfiDisableCache ( 150 ; VOID 151 ; ); 152 ;------------------------------------------------------------------------------ 153 EfiDisableCache PROC PUBLIC 154 ; added a check to see if cache is already disabled. If it is, then skip. 155 mov rax, cr0 156 and rax, 060000000h 157 cmp rax, 0 158 jne @f 159 mov rax, cr0 160 or rax, 060000000h 161 mov cr0, rax 162 wbinvd 163 @@: 164 ret 165 EfiDisableCache ENDP 166 167 ;------------------------------------------------------------------------------ 168 ; VOID 169 ; EfiEnableCache ( 170 ; VOID 171 ; ); 172 ;------------------------------------------------------------------------------ 173 EfiEnableCache PROC PUBLIC 174 wbinvd 175 mov rax, cr0 176 and rax, 09fffffffh 177 mov cr0, rax 178 ret 179 EfiEnableCache ENDP 180 181 ;------------------------------------------------------------------------------ 182 ; UINTN 183 ; EfiGetEflags ( 184 ; VOID 185 ; ); 186 ;------------------------------------------------------------------------------ 187 EfiGetEflags PROC PUBLIC 188 pushfq 189 pop rax 190 ret 191 EfiGetEflags ENDP 192 193 ;------------------------------------------------------------------------------ 194 ; VOID 195 ; EfiDisableInterrupts ( 196 ; VOID 197 ; ); 198 ;------------------------------------------------------------------------------ 199 EfiDisableInterrupts PROC PUBLIC 200 cli 201 ret 202 EfiDisableInterrupts ENDP 203 204 ;------------------------------------------------------------------------------ 205 ; VOID 206 ; EfiEnableInterrupts ( 207 ; VOID 208 ; ); 209 ;------------------------------------------------------------------------------ 210 EfiEnableInterrupts PROC PUBLIC 211 sti 212 ret 213 EfiEnableInterrupts ENDP 214 ;------------------------------------------------------------------------------ 215 ; VOID 216 ; EfiCpuidExt ( 217 ; IN UINT32 RegisterInEax, 218 ; IN UINT32 CacheLevel, 219 ; OUT EFI_CPUID_REGISTER *Regs 220 ; ) 221 ;------------------------------------------------------------------------------ 222 EfiCpuidExt PROC PUBLIC 223 push rbx 224 mov rax, rcx ; rax = RegisterInEax 225 mov rcx, rdx ; rcx = CacheLevel 226 227 cpuid 228 mov [r8 + 0 ], eax ; Reg->RegEax 229 mov [r8 + 4 ], ebx ; Reg->RegEbx 230 mov [r8 + 8 ], ecx ; Reg->RegEcx 231 mov [r8 + 12], edx ; Reg->RegEdx 232 233 pop rbx 234 ret 235 EfiCpuidExt ENDP 236 END 237
