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      1 /** @file
      2 
      3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
      4 
      5   This program and the accompanying materials are licensed and made available under
      7   the terms and conditions of the BSD License that accompanies this distribution.
      9   The full text of the license may be found at
     11   http://opensource.org/licenses/bsd-license.php.
     13 
     15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     17   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     19 
     21 
     23 Module Name:
     24 
     25 
     26   PeiPostCode.c
     27 
     28 Abstract:
     29 
     30   Worker functions for PostCode
     31 
     32 --*/
     33 
     34 #include "EfiStatusCode.h"
     35 
     36 #pragma pack(1)
     37 typedef struct {
     38   EFI_STATUS_CODE_VALUE   StatusValue;
     39   UINT8                   Port80Value;
     40 } EFI_STATUS_CODE_TO_PORT_80;
     41 #pragma pack()
     42 
     43 //
     44 // see Edk\Foundation\Library\EfiCommonLib\PostCode.c for DXE/BDS POST codes.
     45 //
     46 EFI_STATUS_CODE_TO_PORT_80  mPeiPort80Table[] = {
     47   //
     48   // Platform init
     49   //
     50   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_INIT,          0x11},
     51   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP1,         0x12},
     52   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP2,         0x13},
     53   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP3,         0x14},
     54   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP4,         0x15},
     55 
     56   //
     57   // SMBUS
     58   //
     59   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_INIT,             0x16},
     60   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_EXEC_ENTRY,       0x17},
     61   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_EXEC_EXIT,        0x18},
     62 
     63   //
     64   // Clock
     65   //
     66   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY,       0x19},
     67   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_EXIT,        0x1A},
     68 
     69   //
     70   // Over clocking support
     71   //
     72   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_OVERCLOCK_PEI_INIT_ENTRY,   0x1B},
     73   {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_OVERCLOCK_PEI_INIT_EXIT,    0x1C},
     74 
     75   //
     76   // MRC
     77   //
     78   {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_INIT_BEGIN,        0x21},
     79   {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_SPD_READ,          0x23},
     80   {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PRESENCE_DETECT,   0x24},
     81   {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TIMING,            0x25},
     82   {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_OPTIMIZING,        0x26},
     83   {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_CONFIGURING,       0x27},
     84   {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TEST,              0x28},
     85   {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_COMPLETE,          0x29},
     86 
     87   //
     88   // Platform Init after MRC
     89   //
     90   {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PROG_MTRR,         0x2A},
     91   {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PROG_MTRR_END,     0x2B},
     92 
     93   {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_BEGIN,        0x31},
     94   {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_AUTO,         0x32},
     95   {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD,          0x33},
     96   {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_START,         0x34},
     97   {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE,   0x35},
     98 
     99   {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_INIT,      0x41},
    100   {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_STEP1,     0x42},
    101   {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_END,       0x43},
    102   {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_INIT,  0x44},
    103   {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_STEP1, 0x45},
    104   {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_END,   0x46}
    105 };
    106 
    107 BOOLEAN
    108 PeiCodeTypeToPostCode (
    109   IN  EFI_STATUS_CODE_TYPE    CodeType,
    110   IN  EFI_STATUS_CODE_VALUE   Value,
    111   OUT UINT8                   *PostCode
    112   )
    113 {
    114   UINTN             Index;
    115 
    116   if (CodeType == EFI_PROGRESS_CODE) {
    117     if ((Value == (EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_BEGIN)) ||
    118         (Value == (EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_END)) ||
    119         (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_BEGIN)) ||
    120         (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_END))) {
    121       return FALSE;
    122     }
    123   } else {
    124     return FALSE;
    125   }
    126 
    127   for (Index = 0; Index < sizeof(mPeiPort80Table)/sizeof(EFI_STATUS_CODE_TO_PORT_80); Index++) {
    128     if (mPeiPort80Table[Index].StatusValue == Value) {
    129       *PostCode = mPeiPort80Table[Index].Port80Value;
    130       return TRUE;
    131     }
    132   }
    133 
    134   return FALSE;
    135 }
    136