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      1 /*
      2 
      3 Copyright (c) 2009, 2010, 2011 STMicroelectronics
      4 Written by Christophe Lyon
      5 
      6 Permission is hereby granted, free of charge, to any person obtaining a copy
      7 of this software and associated documentation files (the "Software"), to deal
      8 in the Software without restriction, including without limitation the rights
      9 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 copies of the Software, and to permit persons to whom the Software is
     11 furnished to do so, subject to the following conditions:
     12 
     13 The above copyright notice and this permission notice shall be included in
     14 all copies or substantial portions of the Software.
     15 
     16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
     19 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 THE SOFTWARE.
     23 
     24 */
     25 
     26 /* Template file for binary operator validation */
     27 
     28 #if defined(__arm__) || defined(__aarch64__)
     29 #include <arm_neon.h>
     30 #else
     31 #include "stm-arm-neon.h"
     32 #endif
     33 
     34 #include "stm-arm-neon-ref.h"
     35 
     36 #define FNNAME1(NAME) void exec_ ## NAME (void)
     37 #define FNNAME(NAME) FNNAME1(NAME)
     38 
     39 FNNAME (INSN_NAME)
     40 {
     41   /* Basic test: y=OP(x,x), then store the result.  */
     42 #define TEST_BINARY_OP1(INSN, Q, T1, T2, W, N)				\
     43   VECT_VAR(vector_res, T1, W, N) =					\
     44     INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N),			\
     45 		      VECT_VAR(vector2, T1, W, N));			\
     46   vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
     47 
     48 #define TEST_BINARY_OP(INSN, Q, T1, T2, W, N)				\
     49   TEST_BINARY_OP1(INSN, Q, T1, T2, W, N)				\
     50 
     51   /* With ARM RVCT, we need to declare variables before any executable
     52      statement  */
     53   DECL_VARIABLE_ALL_VARIANTS(vector);
     54   DECL_VARIABLE_ALL_VARIANTS(vector2);
     55   DECL_VARIABLE_ALL_VARIANTS(vector_res);
     56 
     57   clean_results ();
     58 
     59   /* Initialize input "vector" from "buffer"  */
     60   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
     61 
     62   /* Fill input vector2 with arbitrary values */
     63   VDUP(vector2, , int, s, 8, 8, 2);
     64   VDUP(vector2, , int, s, 16, 4, -4);
     65   VDUP(vector2, , int, s, 32, 2, 3);
     66   VDUP(vector2, , int, s, 64, 1, 100);
     67   VDUP(vector2, , uint, u, 8, 8, 20);
     68   VDUP(vector2, , uint, u, 16, 4, 30);
     69   VDUP(vector2, , uint, u, 32, 2, 40);
     70   VDUP(vector2, , uint, u, 64, 1, 2);
     71   VDUP(vector2, q, int, s, 8, 16, -10);
     72   VDUP(vector2, q, int, s, 16, 8, -20);
     73   VDUP(vector2, q, int, s, 32, 4, -30);
     74   VDUP(vector2, q, int, s, 64, 2, 24);
     75   VDUP(vector2, q, uint, u, 8, 16, 12);
     76   VDUP(vector2, q, uint, u, 16, 8, 3);
     77   VDUP(vector2, q, uint, u, 32, 4, 55);
     78   VDUP(vector2, q, uint, u, 64, 2, 3);
     79 
     80   /* Apply a binary operator named INSN_NAME  */
     81   TEST_MACRO_ALL_VARIANTS_1_5(TEST_BINARY_OP, INSN_NAME);
     82 
     83   dump_results_hex (TEST_MSG);
     84 
     85 #ifdef EXTRA_TESTS
     86   EXTRA_TESTS();
     87 #endif
     88 }
     89