1 #!/usr/bin/env python 2 3 # Capstone Python bindings, by Nguyen Anh Quynnh <aquynh (at] gmail.com> 4 5 from __future__ import print_function 6 from capstone import * 7 from capstone.arm64 import * 8 from xprint import to_hex, to_x 9 10 11 ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" 12 13 all_tests = ( 14 (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"), 15 ) 16 17 18 def print_insn_detail(insn): 19 # print address, mnemonic and operands 20 print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) 21 22 # "data" instruction generated by SKIPDATA option has no detail 23 if insn.id == 0: 24 return 25 26 if len(insn.operands) > 0: 27 print("\top_count: %u" % len(insn.operands)) 28 c = -1 29 for i in insn.operands: 30 c += 1 31 if i.type == ARM64_OP_REG: 32 print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) 33 if i.type == ARM64_OP_IMM: 34 print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) 35 if i.type == ARM64_OP_CIMM: 36 print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm)) 37 if i.type == ARM64_OP_FP: 38 print("\t\toperands[%u].type: FP = %f" % (c, i.fp)) 39 if i.type == ARM64_OP_MEM: 40 print("\t\toperands[%u].type: MEM" % c) 41 if i.mem.base != 0: 42 print("\t\t\toperands[%u].mem.base: REG = %s" \ 43 % (c, insn.reg_name(i.mem.base))) 44 if i.mem.index != 0: 45 print("\t\t\toperands[%u].mem.index: REG = %s" \ 46 % (c, insn.reg_name(i.mem.index))) 47 if i.mem.disp != 0: 48 print("\t\t\toperands[%u].mem.disp: 0x%s" \ 49 % (c, to_x(i.mem.disp))) 50 if i.type == ARM64_OP_REG_MRS: 51 print("\t\toperands[%u].type: REG_MRS = 0x%x" % (c, i.reg)) 52 if i.type == ARM64_OP_REG_MSR: 53 print("\t\toperands[%u].type: REG_MSR = 0x%x" % (c, i.reg)) 54 if i.type == ARM64_OP_PSTATE: 55 print("\t\toperands[%u].type: PSTATE = 0x%x" % (c, i.pstate)) 56 if i.type == ARM64_OP_SYS: 57 print("\t\toperands[%u].type: SYS = 0x%x" % (c, i.sys)) 58 if i.type == ARM64_OP_PREFETCH: 59 print("\t\toperands[%u].type: PREFETCH = 0x%x" % (c, i.prefetch)) 60 if i.type == ARM64_OP_BARRIER: 61 print("\t\toperands[%u].type: BARRIER = 0x%x" % (c, i.barrier)) 62 63 if i.shift.type != ARM64_SFT_INVALID and i.shift.value: 64 print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value)) 65 66 if i.ext != ARM64_EXT_INVALID: 67 print("\t\t\tExt: %u" % i.ext) 68 69 if i.vas != ARM64_VAS_INVALID: 70 print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas) 71 72 if i.vess != ARM64_VESS_INVALID: 73 print("\t\t\tVector Element Size Specifier: %u" % i.vess) 74 75 if i.vector_index != -1: 76 print("\t\t\tVector Index: %u" % i.vector_index) 77 78 if insn.writeback: 79 print("\tWrite-back: True") 80 if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]: 81 print("\tCode-condition: %u" % insn.cc) 82 if insn.update_flags: 83 print("\tUpdate-flags: True") 84 85 86 # ## Test class Cs 87 def test_class(): 88 89 for (arch, mode, code, comment) in all_tests: 90 print("*" * 16) 91 print("Platform: %s" % comment) 92 print("Code: %s" % to_hex(code)) 93 print("Disasm:") 94 95 try: 96 md = Cs(arch, mode) 97 md.detail = True 98 for insn in md.disasm(code, 0x2c): 99 print_insn_detail(insn) 100 print () 101 print("0x%x:\n" % (insn.address + insn.size)) 102 except CsError as e: 103 print("ERROR: %s" % e) 104 105 106 if __name__ == '__main__': 107 test_class() 108
