1 /* Capstone Disassembler Engine */ 2 /* By Nguyen Anh Quynh <aquynh (at) gmail.com>, 2013> */ 3 4 #include <stdio.h> 5 #include <stdlib.h> 6 7 #include <platform.h> 8 #include <capstone.h> 9 10 struct platform { 11 cs_arch arch; 12 cs_mode mode; 13 unsigned char *code; 14 size_t size; 15 char *comment; 16 cs_opt_type opt_type; 17 cs_opt_value opt_value; 18 }; 19 20 static void print_string_hex(unsigned char *str, size_t len) 21 { 22 unsigned char *c; 23 24 printf("Code: "); 25 for (c = str; c < str + len; c++) { 26 printf("0x%02x ", *c & 0xff); 27 } 28 printf("\n"); 29 } 30 31 static void test() 32 { 33 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" 34 #define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" 35 //#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng 36 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00" 37 //#define ARM_CODE "\x04\xe0\x2d\xe5" 38 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" 39 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" 40 #define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" 41 #define THUMB_MCLASS "\xef\xf3\x02\x80" 42 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68" 43 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" 44 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" 45 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00" 46 #define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" 47 #define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0" 48 //#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw 49 //#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2 50 //#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0 51 //#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8] 52 #define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9" 53 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" 54 #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" 55 #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" 56 #define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" 57 #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" 58 struct platform { 59 cs_arch arch; 60 cs_mode mode; 61 unsigned char *code; 62 size_t size; 63 char *comment; 64 cs_opt_type opt_type; 65 cs_opt_value opt_value; 66 }; 67 struct platform platforms[] = { 68 { 69 CS_ARCH_X86, 70 CS_MODE_16, 71 (unsigned char*)X86_CODE16, 72 sizeof(X86_CODE16) - 1, 73 "X86 16bit (Intel syntax)" 74 }, 75 { 76 CS_ARCH_X86, 77 CS_MODE_32, 78 (unsigned char*)X86_CODE32, 79 sizeof(X86_CODE32) - 1, 80 "X86 32bit (ATT syntax)", 81 CS_OPT_SYNTAX, 82 CS_OPT_SYNTAX_ATT, 83 }, 84 { 85 CS_ARCH_X86, 86 CS_MODE_32, 87 (unsigned char*)X86_CODE32, 88 sizeof(X86_CODE32) - 1, 89 "X86 32 (Intel syntax)" 90 }, 91 { 92 CS_ARCH_X86, 93 CS_MODE_64, 94 (unsigned char*)X86_CODE64, 95 sizeof(X86_CODE64) - 1, 96 "X86 64 (Intel syntax)" 97 }, 98 { 99 CS_ARCH_ARM, 100 CS_MODE_ARM, 101 (unsigned char*)ARM_CODE, 102 sizeof(ARM_CODE) - 1, 103 "ARM" 104 }, 105 { 106 CS_ARCH_ARM, 107 CS_MODE_THUMB, 108 (unsigned char*)THUMB_CODE2, 109 sizeof(THUMB_CODE2) - 1, 110 "THUMB-2" 111 }, 112 { 113 CS_ARCH_ARM, 114 CS_MODE_ARM, 115 (unsigned char*)ARM_CODE2, 116 sizeof(ARM_CODE2) - 1, 117 "ARM: Cortex-A15 + NEON" 118 }, 119 { 120 CS_ARCH_ARM, 121 CS_MODE_THUMB, 122 (unsigned char*)THUMB_CODE, 123 sizeof(THUMB_CODE) - 1, 124 "THUMB" 125 }, 126 { 127 CS_ARCH_ARM, 128 (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), 129 (unsigned char*)THUMB_MCLASS, 130 sizeof(THUMB_MCLASS) - 1, 131 "Thumb-MClass" 132 }, 133 { 134 CS_ARCH_ARM, 135 (cs_mode)(CS_MODE_ARM + CS_MODE_V8), 136 (unsigned char*)ARMV8, 137 sizeof(ARMV8) - 1, 138 "Arm-V8" 139 }, 140 { 141 CS_ARCH_MIPS, 142 (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), 143 (unsigned char*)MIPS_CODE, 144 sizeof(MIPS_CODE) - 1, 145 "MIPS-32 (Big-endian)" 146 }, 147 { 148 CS_ARCH_MIPS, 149 (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN), 150 (unsigned char*)MIPS_CODE2, 151 sizeof(MIPS_CODE2) - 1, 152 "MIPS-64-EL (Little-endian)" 153 }, 154 { 155 CS_ARCH_MIPS, 156 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), 157 (unsigned char*)MIPS_32R6M, 158 sizeof(MIPS_32R6M) - 1, 159 "MIPS-32R6 | Micro (Big-endian)" 160 }, 161 { 162 CS_ARCH_MIPS, 163 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), 164 (unsigned char*)MIPS_32R6, 165 sizeof(MIPS_32R6) - 1, 166 "MIPS-32R6 (Big-endian)" 167 }, 168 { 169 CS_ARCH_ARM64, 170 CS_MODE_ARM, 171 (unsigned char*)ARM64_CODE, 172 sizeof(ARM64_CODE) - 1, 173 "ARM-64" 174 }, 175 { 176 CS_ARCH_PPC, 177 CS_MODE_BIG_ENDIAN, 178 (unsigned char*)PPC_CODE, 179 sizeof(PPC_CODE) - 1, 180 "PPC-64" 181 }, 182 { 183 CS_ARCH_PPC, 184 CS_MODE_BIG_ENDIAN, 185 (unsigned char*)PPC_CODE, 186 sizeof(PPC_CODE) - 1, 187 "PPC-64, print register with number only", 188 CS_OPT_SYNTAX, 189 CS_OPT_SYNTAX_NOREGNAME 190 }, 191 { 192 CS_ARCH_SPARC, 193 CS_MODE_BIG_ENDIAN, 194 (unsigned char*)SPARC_CODE, 195 sizeof(SPARC_CODE) - 1, 196 "Sparc" 197 }, 198 { 199 CS_ARCH_SPARC, 200 (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), 201 (unsigned char*)SPARCV9_CODE, 202 sizeof(SPARCV9_CODE) - 1, 203 "SparcV9" 204 }, 205 { 206 CS_ARCH_SYSZ, 207 (cs_mode)0, 208 (unsigned char*)SYSZ_CODE, 209 sizeof(SYSZ_CODE) - 1, 210 "SystemZ" 211 }, 212 { 213 CS_ARCH_XCORE, 214 (cs_mode)0, 215 (unsigned char*)XCORE_CODE, 216 sizeof(XCORE_CODE) - 1, 217 "XCore" 218 }, 219 }; 220 221 csh handle; 222 uint64_t address = 0x1000; 223 cs_insn *insn; 224 int i; 225 size_t count; 226 cs_err err; 227 228 for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { 229 printf("****************\n"); 230 printf("Platform: %s\n", platforms[i].comment); 231 err = cs_open(platforms[i].arch, platforms[i].mode, &handle); 232 if (err) { 233 printf("Failed on cs_open() with error returned: %u\n", err); 234 continue; 235 } 236 237 if (platforms[i].opt_type) 238 cs_option(handle, platforms[i].opt_type, platforms[i].opt_value); 239 240 count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); 241 if (count) { 242 size_t j; 243 244 print_string_hex(platforms[i].code, platforms[i].size); 245 printf("Disasm:\n"); 246 247 for (j = 0; j < count; j++) { 248 printf("0x%" PRIx64 ":\t%s\t\t%s\n", 249 insn[j].address, insn[j].mnemonic, insn[j].op_str); 250 } 251 252 // print out the next offset, after the last insn 253 printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); 254 255 // free memory allocated by cs_disasm() 256 cs_free(insn, count); 257 } else { 258 printf("****************\n"); 259 printf("Platform: %s\n", platforms[i].comment); 260 print_string_hex(platforms[i].code, platforms[i].size); 261 printf("ERROR: Failed to disasm given code!\n"); 262 } 263 264 printf("\n"); 265 266 cs_close(&handle); 267 } 268 } 269 270 int main() 271 { 272 test(); 273 274 #if 0 275 #define offsetof(st, m) __builtin_offsetof(st, m) 276 277 cs_insn insn; 278 printf("size: %lu\n", sizeof(insn)); 279 printf("@id: %lu\n", offsetof(cs_insn, id)); 280 printf("@address: %lu\n", offsetof(cs_insn, address)); 281 printf("@size: %lu\n", offsetof(cs_insn, size)); 282 printf("@bytes: %lu\n", offsetof(cs_insn, bytes)); 283 printf("@mnemonic: %lu\n", offsetof(cs_insn, mnemonic)); 284 printf("@op_str: %lu\n", offsetof(cs_insn, op_str)); 285 printf("@regs_read: %lu\n", offsetof(cs_insn, regs_read)); 286 printf("@regs_read_count: %lu\n", offsetof(cs_insn, regs_read_count)); 287 printf("@regs_write: %lu\n", offsetof(cs_insn, regs_write)); 288 printf("@regs_write_count: %lu\n", offsetof(cs_insn, regs_write_count)); 289 printf("@groups: %lu\n", offsetof(cs_insn, groups)); 290 printf("@groups_count: %lu\n", offsetof(cs_insn, groups_count)); 291 printf("@arch: %lu\n", offsetof(cs_insn, x86)); 292 #endif 293 294 return 0; 295 } 296
