1 // REQUIRES: arm-registered-target 2 // RUN: %clang_cc1 -triple thumbv7-apple-darwin \ 3 // RUN: -target-abi apcs-gnu \ 4 // RUN: -target-cpu cortex-a8 \ 5 // RUN: -mfloat-abi soft \ 6 // RUN: -target-feature +soft-float-abi \ 7 // RUN: -ffreestanding \ 8 // RUN: -emit-llvm -w -o - %s | FileCheck %s 9 10 #include <arm_neon.h> 11 12 // Radar 11998303: Avoid using i64 types for vld1q_lane and vst1q_lane Neon 13 // intrinsics with <2 x i64> vectors to avoid poor code for i64 in the backend. 14 void t1(uint64_t *src, uint8_t *dst) { 15 // CHECK: @t1 16 uint64x2_t q = vld1q_u64(src); 17 // CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8 18 vst1q_lane_u64(dst, q, 1); 19 // CHECK: bitcast <16 x i8> %{{.*}} to <2 x i64> 20 // CHECK: shufflevector <2 x i64> 21 // CHECK: call void @llvm.arm.neon.vst1.p0i8.v1i64 22 } 23 24 void t2(uint64_t *src1, uint8_t *src2, uint64x2_t *dst) { 25 // CHECK: @t2 26 uint64x2_t q = vld1q_u64(src1); 27 // CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8 28 q = vld1q_lane_u64(src2, q, 0); 29 // CHECK: shufflevector <2 x i64> 30 // CHECK: call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8 31 // CHECK: shufflevector <1 x i64> 32 *dst = q; 33 // CHECK: store <2 x i64> 34 } 35
