1 // REQUIRES: arm-registered-target 2 // RUN: %clang_cc1 -triple thumbv7-apple-darwin \ 3 // RUN: -target-cpu cortex-a8 \ 4 // RUN: -ffreestanding \ 5 // RUN: -emit-llvm -w -o - %s | opt -S -mem2reg | FileCheck %s 6 7 #include <arm_neon.h> 8 9 uint8x8_t test_shift_vshr(uint8x8_t a) { 10 // CHECK-LABEL: test_shift_vshr 11 // CHECK: %{{.*}} = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> 12 return vshr_n_u8(a, 5); 13 } 14 15 int8x8_t test_shift_vshr_smax(int8x8_t a) { 16 // CHECK-LABEL: test_shift_vshr_smax 17 // CHECK: %{{.*}} = ashr <8 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 18 return vshr_n_s8(a, 8); 19 } 20 21 uint8x8_t test_shift_vshr_umax(uint8x8_t a) { 22 // CHECK-LABEL: test_shift_vshr_umax 23 // CHECK: ret <8 x i8> zeroinitializer 24 return vshr_n_u8(a, 8); 25 } 26 27 uint8x8_t test_shift_vsra(uint8x8_t a, uint8x8_t b) { 28 // CHECK-LABEL: test_shift_vsra 29 // CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> 30 // CHECK: %{{.*}} = add <8 x i8> %a, %[[SHR]] 31 return vsra_n_u8(a, b, 5); 32 } 33 34 int8x8_t test_shift_vsra_smax(int8x8_t a, int8x8_t b) { 35 // CHECK-LABEL: test_shift_vsra_smax 36 // CHECK: %[[SHR:.*]] = ashr <8 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 37 // CHECK: %{{.*}} = add <8 x i8> %a, %[[SHR]] 38 return vsra_n_s8(a, b, 8); 39 } 40 41 uint8x8_t test_shift_vsra_umax(uint8x8_t a, uint8x8_t b) { 42 // CHECK-LABEL: test_shift_vsra_umax 43 // CHECK: [[RES:%.*]] = add <8 x i8> %a, zeroinitializer 44 // CHECK: ret <8 x i8> [[RES]] 45 return vsra_n_u8(a, b, 8); 46 } 47
