1 // Test host codegen. 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 6 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 8 9 // Test target codegen - host bc file has to be created first. 10 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 11 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 12 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 13 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 15 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 16 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 17 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 18 19 // expected-no-diagnostics 20 #ifndef HEADER 21 #define HEADER 22 23 // CHECK-DAG: [[TT:%.+]] = type { i64, i8 } 24 // CHECK-DAG: [[S1:%.+]] = type { double } 25 // CHECK-DAG: [[ENTTY:%.+]] = type { i8*, i8*, i[[SZ:32|64]] } 26 // CHECK-DAG: [[DEVTY:%.+]] = type { i8*, i8*, [[ENTTY]]*, [[ENTTY]]* } 27 // CHECK-DAG: [[DSCTY:%.+]] = type { i32, [[DEVTY]]*, [[ENTTY]]*, [[ENTTY]]* } 28 29 // TCHECK: [[ENTTY:%.+]] = type { i8*, i8*, i{{32|64}} } 30 31 // We have 8 target regions, but only 7 that actually will generate offloading 32 // code, only 6 will have mapped arguments, and only 4 have all-constant map 33 // sizes. 34 35 // CHECK-DAG: [[SIZET2:@.+]] = private unnamed_addr constant [1 x i{{32|64}}] [i[[SZ:32|64]] 2] 36 // CHECK-DAG: [[MAPT2:@.+]] = private unnamed_addr constant [1 x i32] [i32 288] 37 // CHECK-DAG: [[SIZET3:@.+]] = private unnamed_addr constant [2 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2] 38 // CHECK-DAG: [[MAPT3:@.+]] = private unnamed_addr constant [2 x i32] [i32 288, i32 288] 39 // CHECK-DAG: [[MAPT4:@.+]] = private unnamed_addr constant [9 x i32] [i32 288, i32 35, i32 288, i32 35, i32 35, i32 288, i32 288, i32 35, i32 35] 40 // CHECK-DAG: [[SIZET5:@.+]] = private unnamed_addr constant [3 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2, i[[SZ]] 40] 41 // CHECK-DAG: [[MAPT5:@.+]] = private unnamed_addr constant [3 x i32] [i32 288, i32 288, i32 35] 42 // CHECK-DAG: [[SIZET6:@.+]] = private unnamed_addr constant [4 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2, i[[SZ]] 1, i[[SZ]] 40] 43 // CHECK-DAG: [[MAPT6:@.+]] = private unnamed_addr constant [4 x i32] [i32 288, i32 288, i32 288, i32 35] 44 // CHECK-DAG: [[MAPT7:@.+]] = private unnamed_addr constant [5 x i32] [i32 35, i32 288, i32 288, i32 288, i32 35] 45 // CHECK-DAG: @{{.*}} = private constant i8 0 46 // CHECK-DAG: @{{.*}} = private constant i8 0 47 // CHECK-DAG: @{{.*}} = private constant i8 0 48 // CHECK-DAG: @{{.*}} = private constant i8 0 49 // CHECK-DAG: @{{.*}} = private constant i8 0 50 // CHECK-DAG: @{{.*}} = private constant i8 0 51 // CHECK-DAG: @{{.*}} = private constant i8 0 52 53 // TCHECK: @{{.+}} = constant [[ENTTY]] 54 // TCHECK: @{{.+}} = constant [[ENTTY]] 55 // TCHECK: @{{.+}} = constant [[ENTTY]] 56 // TCHECK: @{{.+}} = constant [[ENTTY]] 57 // TCHECK: @{{.+}} = constant [[ENTTY]] 58 // TCHECK: @{{.+}} = constant [[ENTTY]] 59 // TCHECK: @{{.+}} = constant [[ENTTY]] 60 // TCHECK-NOT: @{{.+}} = constant [[ENTTY]] 61 62 // Check if offloading descriptor is created. 63 // CHECK: [[ENTBEGIN:@.+]] = external constant [[ENTTY]] 64 // CHECK: [[ENTEND:@.+]] = external constant [[ENTTY]] 65 // CHECK: [[DEVBEGIN:@.+]] = external constant i8 66 // CHECK: [[DEVEND:@.+]] = external constant i8 67 // CHECK: [[IMAGES:@.+]] = internal unnamed_addr constant [1 x [[DEVTY]]] [{{.+}} { i8* [[DEVBEGIN]], i8* [[DEVEND]], [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }] 68 // CHECK: [[DESC:@.+]] = internal constant [[DSCTY]] { i32 1, [[DEVTY]]* getelementptr inbounds ([1 x [[DEVTY]]], [1 x [[DEVTY]]]* [[IMAGES]], i32 0, i32 0), [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] } 69 70 // Check target registration is registered as a Ctor. 71 // CHECK: appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* bitcast (void (i8*)* [[REGFN:@.+]] to void ()*), i8* null }] 72 73 74 template<typename tx, typename ty> 75 struct TT{ 76 tx X; 77 ty Y; 78 }; 79 80 // CHECK: define {{.*}}[[FOO:@.+]]( 81 int foo(int n) { 82 int a = 0; 83 short aa = 0; 84 float b[10]; 85 float bn[n]; 86 double c[5][10]; 87 double cn[5][n]; 88 TT<long long, char> d; 89 90 // CHECK: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i32* null) 91 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 92 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 93 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 94 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 95 // CHECK: [[FAIL]] 96 // CHECK: call void [[HVT0:@.+]]() 97 // CHECK-NEXT: br label %[[END]] 98 // CHECK: [[END]] 99 #pragma omp target 100 { 101 } 102 103 // CHECK: store i32 0, i32* [[RHV:%.+]], align 4 104 // CHECK: store i32 -1, i32* [[RHV]], align 4 105 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 106 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 107 // CHECK: call void [[HVT1:@.+]](i[[SZ]] {{[^,]+}}) 108 #pragma omp target if(0) 109 { 110 a += 1; 111 } 112 113 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 1, i8** [[BP:%[^,]+]], i8** [[P:%[^,]+]], i[[SZ]]* getelementptr inbounds ([1 x i[[SZ]]], [1 x i[[SZ]]]* [[SIZET2]], i32 0, i32 0), i32* getelementptr inbounds ([1 x i32], [1 x i32]* [[MAPT2]], i32 0, i32 0)) 114 // CHECK-DAG: [[BP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPR:%[^,]+]], i32 0, i32 0 115 // CHECK-DAG: [[P]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PR:%[^,]+]], i32 0, i32 0 116 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPR]], i32 0, i32 [[IDX0:[0-9]+]] 117 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PR]], i32 0, i32 [[IDX0]] 118 // CHECK-DAG: store i8* [[BP0:%[^,]+]], i8** [[BPADDR0]] 119 // CHECK-DAG: store i8* [[P0:%[^,]+]], i8** [[PADDR0]] 120 // CHECK-DAG: [[BP0]] = inttoptr i[[SZ]] %{{.+}} to i8* 121 // CHECK-DAG: [[P0]] = inttoptr i[[SZ]] %{{.+}} to i8* 122 123 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 124 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 125 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 126 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 127 // CHECK: [[FAIL]] 128 // CHECK: call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}}) 129 // CHECK-NEXT: br label %[[END]] 130 // CHECK: [[END]] 131 #pragma omp target if(1) 132 { 133 aa += 1; 134 } 135 136 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 10 137 // CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]] 138 // CHECK: [[IFTHEN]] 139 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 2, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([2 x i[[SZ]]], [2 x i[[SZ]]]* [[SIZET3]], i32 0, i32 0), i32* getelementptr inbounds ([2 x i32], [2 x i32]* [[MAPT3]], i32 0, i32 0)) 140 // CHECK-DAG: [[BPR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP:%[^,]+]], i32 0, i32 0 141 // CHECK-DAG: [[PR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P:%[^,]+]], i32 0, i32 0 142 143 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 0 144 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 0 145 // CHECK-DAG: store i8* [[BP0:%[^,]+]], i8** [[BPADDR0]] 146 // CHECK-DAG: store i8* [[P0:%[^,]+]], i8** [[PADDR0]] 147 // CHECK-DAG: [[BP0]] = inttoptr i[[SZ]] %{{.+}} to i8* 148 // CHECK-DAG: [[P0]] = inttoptr i[[SZ]] %{{.+}} to i8* 149 150 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 1 151 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 1 152 // CHECK-DAG: store i8* [[BP1:%[^,]+]], i8** [[BPADDR1]] 153 // CHECK-DAG: store i8* [[P1:%[^,]+]], i8** [[PADDR1]] 154 // CHECK-DAG: [[BP1]] = inttoptr i[[SZ]] %{{.+}} to i8* 155 // CHECK-DAG: [[P1]] = inttoptr i[[SZ]] %{{.+}} to i8* 156 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 157 // CHECK-NEXT: br label %[[IFEND:.+]] 158 159 // CHECK: [[IFELSE]] 160 // CHECK: store i32 -1, i32* [[RHV]], align 4 161 // CHECK-NEXT: br label %[[IFEND:.+]] 162 163 // CHECK: [[IFEND]] 164 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 165 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 166 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 167 // CHECK: [[FAIL]] 168 // CHECK: call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}}) 169 // CHECK-NEXT: br label %[[END]] 170 // CHECK: [[END]] 171 #pragma omp target if(n>10) 172 { 173 a += 1; 174 aa += 1; 175 } 176 177 // We capture 3 VLA sizes in this target region 178 // CHECK-64: [[A_VAL:%.+]] = load i32, i32* %{{.+}}, 179 // CHECK-64: [[A_ADDR:%.+]] = bitcast i[[SZ]]* [[A_CADDR:%.+]] to i32* 180 // CHECK-64: store i32 [[A_VAL]], i32* [[A_ADDR]], 181 // CHECK-64: [[A_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[A_CADDR]], 182 183 // CHECK-32: [[A_VAL:%.+]] = load i32, i32* %{{.+}}, 184 // CHECK-32: store i32 [[A_VAL]], i32* [[A_CADDR:%.+]], 185 // CHECK-32: [[A_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[A_CADDR]], 186 187 // CHECK: [[BNSIZE:%.+]] = mul nuw i[[SZ]] [[VLA0:%.+]], 4 188 // CHECK: [[CNELEMSIZE2:%.+]] = mul nuw i[[SZ]] 5, [[VLA1:%.+]] 189 // CHECK: [[CNSIZE:%.+]] = mul nuw i[[SZ]] [[CNELEMSIZE2]], 8 190 191 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 20 192 // CHECK: br i1 [[IF]], label %[[TRY:[^,]+]], label %[[FAIL:[^,]+]] 193 // CHECK: [[TRY]] 194 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 9, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SR:%[^,]+]], i32* getelementptr inbounds ([9 x i32], [9 x i32]* [[MAPT4]], i32 0, i32 0)) 195 // CHECK-DAG: [[BPR]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP:%[^,]+]], i32 0, i32 0 196 // CHECK-DAG: [[PR]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P:%[^,]+]], i32 0, i32 0 197 // CHECK-DAG: [[SR]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S:%[^,]+]], i32 0, i32 0 198 199 // CHECK-DAG: [[SADDR0:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX0:[0-9]+]] 200 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX0]] 201 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX0]] 202 // CHECK-DAG: [[SADDR1:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX1:[0-9]+]] 203 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX1]] 204 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX1]] 205 // CHECK-DAG: [[SADDR2:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX2:[0-9]+]] 206 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX2]] 207 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX2]] 208 // CHECK-DAG: [[SADDR3:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX3:[0-9]+]] 209 // CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX3]] 210 // CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX3]] 211 // CHECK-DAG: [[SADDR4:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX4:[0-9]+]] 212 // CHECK-DAG: [[BPADDR4:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX4]] 213 // CHECK-DAG: [[PADDR4:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX4]] 214 // CHECK-DAG: [[SADDR5:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX5:[0-9]+]] 215 // CHECK-DAG: [[BPADDR5:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX5]] 216 // CHECK-DAG: [[PADDR5:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX5]] 217 // CHECK-DAG: [[SADDR6:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX6:[0-9]+]] 218 // CHECK-DAG: [[BPADDR6:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX6]] 219 // CHECK-DAG: [[PADDR6:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX6]] 220 // CHECK-DAG: [[SADDR7:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX7:[0-9]+]] 221 // CHECK-DAG: [[BPADDR7:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX7]] 222 // CHECK-DAG: [[PADDR7:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX7]] 223 // CHECK-DAG: [[SADDR8:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX8:[0-9]+]] 224 // CHECK-DAG: [[BPADDR8:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX8]] 225 // CHECK-DAG: [[PADDR8:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX8]] 226 227 // The names below are not necessarily consistent with the names used for the 228 // addresses above as some are repeated. 229 // CHECK-DAG: [[BP0:%[^,]+]] = inttoptr i[[SZ]] [[VLA0]] to i8* 230 // CHECK-DAG: [[P0:%[^,]+]] = inttoptr i[[SZ]] [[VLA0]] to i8* 231 // CHECK-DAG: store i8* [[BP0]], i8** {{%[^,]+}} 232 // CHECK-DAG: store i8* [[P0]], i8** {{%[^,]+}} 233 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}} 234 235 // CHECK-DAG: [[BP1:%[^,]+]] = inttoptr i[[SZ]] [[VLA1]] to i8* 236 // CHECK-DAG: [[P1:%[^,]+]] = inttoptr i[[SZ]] [[VLA1]] to i8* 237 // CHECK-DAG: store i8* [[BP1]], i8** {{%[^,]+}} 238 // CHECK-DAG: store i8* [[P1]], i8** {{%[^,]+}} 239 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}} 240 241 // CHECK-DAG: store i8* inttoptr (i[[SZ]] 5 to i8*), i8** {{%[^,]+}} 242 // CHECK-DAG: store i8* inttoptr (i[[SZ]] 5 to i8*), i8** {{%[^,]+}} 243 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}} 244 245 // CHECK-DAG: [[BP3:%[^,]+]] = inttoptr i[[SZ]] [[A_CVAL]] to i8* 246 // CHECK-DAG: [[P3:%[^,]+]] = inttoptr i[[SZ]] [[A_CVAL]] to i8* 247 // CHECK-DAG: store i8* [[BP3]], i8** {{%[^,]+}} 248 // CHECK-DAG: store i8* [[P3]], i8** {{%[^,]+}} 249 // CHECK-DAG: store i[[SZ]] 4, i[[SZ]]* {{%[^,]+}} 250 251 // CHECK-DAG: [[BP4:%[^,]+]] = bitcast [10 x float]* %{{.+}} to i8* 252 // CHECK-DAG: [[P4:%[^,]+]] = bitcast [10 x float]* %{{.+}} to i8* 253 // CHECK-DAG: store i8* [[BP4]], i8** {{%[^,]+}} 254 // CHECK-DAG: store i8* [[P4]], i8** {{%[^,]+}} 255 // CHECK-DAG: store i[[SZ]] 40, i[[SZ]]* {{%[^,]+}} 256 257 // CHECK-DAG: [[BP5:%[^,]+]] = bitcast float* %{{.+}} to i8* 258 // CHECK-DAG: [[P5:%[^,]+]] = bitcast float* %{{.+}} to i8* 259 // CHECK-DAG: store i8* [[BP5]], i8** {{%[^,]+}} 260 // CHECK-DAG: store i8* [[P5]], i8** {{%[^,]+}} 261 // CHECK-DAG: store i[[SZ]] [[BNSIZE]], i[[SZ]]* {{%[^,]+}} 262 263 // CHECK-DAG: [[BP6:%[^,]+]] = bitcast [5 x [10 x double]]* %{{.+}} to i8* 264 // CHECK-DAG: [[P6:%[^,]+]] = bitcast [5 x [10 x double]]* %{{.+}} to i8* 265 // CHECK-DAG: store i8* [[BP6]], i8** {{%[^,]+}} 266 // CHECK-DAG: store i8* [[P6]], i8** {{%[^,]+}} 267 // CHECK-DAG: store i[[SZ]] 400, i[[SZ]]* {{%[^,]+}} 268 269 // CHECK-DAG: [[BP7:%[^,]+]] = bitcast double* %{{.+}} to i8* 270 // CHECK-DAG: [[P7:%[^,]+]] = bitcast double* %{{.+}} to i8* 271 // CHECK-DAG: store i8* [[BP7]], i8** {{%[^,]+}} 272 // CHECK-DAG: store i8* [[P7]], i8** {{%[^,]+}} 273 // CHECK-DAG: store i[[SZ]] [[CNSIZE]], i[[SZ]]* {{%[^,]+}} 274 275 // CHECK-DAG: [[BP8:%[^,]+]] = bitcast [[TT]]* %{{.+}} to i8* 276 // CHECK-DAG: [[P8:%[^,]+]] = bitcast [[TT]]* %{{.+}} to i8* 277 // CHECK-DAG: store i8* [[BP8]], i8** {{%[^,]+}} 278 // CHECK-DAG: store i8* [[P8]], i8** {{%[^,]+}} 279 // CHECK-DAG: store i[[SZ]] {{12|16}}, i[[SZ]]* {{%[^,]+}} 280 281 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 282 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 283 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 284 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 285 286 // CHECK: [[FAIL]] 287 // CHECK: call void [[HVT4:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 288 // CHECK-NEXT: br label %[[END]] 289 // CHECK: [[END]] 290 #pragma omp target if(n>20) 291 { 292 a += 1; 293 b[2] += 1.0; 294 bn[3] += 1.0; 295 c[1][2] += 1.0; 296 cn[1][3] += 1.0; 297 d.X += 1; 298 d.Y += 1; 299 } 300 301 return a; 302 } 303 304 // Check that the offloading functions are emitted and that the arguments are 305 // correct and loaded correctly for the target regions in foo(). 306 307 // CHECK: define internal void [[HVT0]]() 308 309 // CHECK: define internal void [[HVT1]](i[[SZ]] %{{.+}}) 310 // Create stack storage and store argument in there. 311 // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align 312 // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align 313 // CHECK-64: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i32* 314 // CHECK-64: load i32, i32* [[AA_CADDR]], align 315 // CHECK-32: load i32, i32* [[AA_ADDR]], align 316 317 // CHECK: define internal void [[HVT2]](i[[SZ]] %{{.+}}) 318 // Create stack storage and store argument in there. 319 // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align 320 // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align 321 // CHECK: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16* 322 // CHECK: load i16, i16* [[AA_CADDR]], align 323 324 // CHECK: define internal void [[HVT3]] 325 // Create stack storage and store argument in there. 326 // CHECK: [[A_ADDR:%.+]] = alloca i[[SZ]], align 327 // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align 328 // CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[A_ADDR]], align 329 // CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align 330 // CHECK-64-DAG:[[A_CADDR:%.+]] = bitcast i[[SZ]]* [[A_ADDR]] to i32* 331 // CHECK-DAG: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16* 332 // CHECK-64-DAG:load i32, i32* [[A_CADDR]], align 333 // CHECK-32-DAG:load i32, i32* [[A_ADDR]], align 334 // CHECK-DAG: load i16, i16* [[AA_CADDR]], align 335 336 // CHECK: define internal void [[HVT4]] 337 // Create local storage for each capture. 338 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] 339 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x float]* 340 // CHECK: [[LOCAL_VLA1:%.+]] = alloca i[[SZ]] 341 // CHECK: [[LOCAL_BN:%.+]] = alloca float* 342 // CHECK: [[LOCAL_C:%.+]] = alloca [5 x [10 x double]]* 343 // CHECK: [[LOCAL_VLA2:%.+]] = alloca i[[SZ]] 344 // CHECK: [[LOCAL_VLA3:%.+]] = alloca i[[SZ]] 345 // CHECK: [[LOCAL_CN:%.+]] = alloca double* 346 // CHECK: [[LOCAL_D:%.+]] = alloca [[TT]]* 347 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 348 // CHECK-DAG: store [10 x float]* [[ARG_B:%.+]], [10 x float]** [[LOCAL_B]] 349 // CHECK-DAG: store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]] 350 // CHECK-DAG: store float* [[ARG_BN:%.+]], float** [[LOCAL_BN]] 351 // CHECK-DAG: store [5 x [10 x double]]* [[ARG_C:%.+]], [5 x [10 x double]]** [[LOCAL_C]] 352 // CHECK-DAG: store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]] 353 // CHECK-DAG: store i[[SZ]] [[ARG_VLA3:%.+]], i[[SZ]]* [[LOCAL_VLA3]] 354 // CHECK-DAG: store double* [[ARG_CN:%.+]], double** [[LOCAL_CN]] 355 // CHECK-DAG: store [[TT]]* [[ARG_D:%.+]], [[TT]]** [[LOCAL_D]] 356 357 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 358 // CHECK-DAG: [[REF_B:%.+]] = load [10 x float]*, [10 x float]** [[LOCAL_B]], 359 // CHECK-DAG: [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]], 360 // CHECK-DAG: [[REF_BN:%.+]] = load float*, float** [[LOCAL_BN]], 361 // CHECK-DAG: [[REF_C:%.+]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[LOCAL_C]], 362 // CHECK-DAG: [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]], 363 // CHECK-DAG: [[VAL_VLA3:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA3]], 364 // CHECK-DAG: [[REF_CN:%.+]] = load double*, double** [[LOCAL_CN]], 365 // CHECK-DAG: [[REF_D:%.+]] = load [[TT]]*, [[TT]]** [[LOCAL_D]], 366 367 // Use captures. 368 // CHECK-64-DAG: load i32, i32* [[REF_A]] 369 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 370 // CHECK-DAG: getelementptr inbounds [10 x float], [10 x float]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 371 // CHECK-DAG: getelementptr inbounds float, float* [[REF_BN]], i[[SZ]] 3 372 // CHECK-DAG: getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[REF_C]], i[[SZ]] 0, i[[SZ]] 1 373 // CHECK-DAG: getelementptr inbounds double, double* [[REF_CN]], i[[SZ]] %{{.+}} 374 // CHECK-DAG: getelementptr inbounds [[TT]], [[TT]]* [[REF_D]], i32 0, i32 0 375 376 template<typename tx> 377 tx ftemplate(int n) { 378 tx a = 0; 379 short aa = 0; 380 tx b[10]; 381 382 #pragma omp target if(n>40) 383 { 384 a += 1; 385 aa += 1; 386 b[2] += 1; 387 } 388 389 return a; 390 } 391 392 static 393 int fstatic(int n) { 394 int a = 0; 395 short aa = 0; 396 char aaa = 0; 397 int b[10]; 398 399 #pragma omp target if(n>50) 400 { 401 a += 1; 402 aa += 1; 403 aaa += 1; 404 b[2] += 1; 405 } 406 407 return a; 408 } 409 410 struct S1 { 411 double a; 412 413 int r1(int n){ 414 int b = n+1; 415 short int c[2][n]; 416 417 #pragma omp target if(n>60) 418 { 419 this->a = (double)b + 1.5; 420 c[1][1] = ++a; 421 } 422 423 return c[1][1] + (int)b; 424 } 425 }; 426 427 // CHECK: define {{.*}}@{{.*}}bar{{.*}} 428 int bar(int n){ 429 int a = 0; 430 431 // CHECK: call {{.*}}i32 [[FOO]](i32 {{.*}}) 432 a += foo(n); 433 434 S1 S; 435 // CHECK: call {{.*}}i32 [[FS1:@.+]]([[S1]]* {{.*}}, i32 {{.*}}) 436 a += S.r1(n); 437 438 // CHECK: call {{.*}}i32 [[FSTATIC:@.+]](i32 {{.*}}) 439 a += fstatic(n); 440 441 // CHECK: call {{.*}}i32 [[FTEMPLATE:@.+]](i32 {{.*}}) 442 a += ftemplate<int>(n); 443 444 return a; 445 } 446 447 // 448 // CHECK: define {{.*}}[[FS1]] 449 // 450 // CHECK: i8* @llvm.stacksave() 451 // CHECK-64: [[B_ADDR:%.+]] = bitcast i[[SZ]]* [[B_CADDR:%.+]] to i32* 452 // CHECK-64: store i32 %{{.+}}, i32* [[B_ADDR]], 453 // CHECK-64: [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]], 454 455 // CHECK-32: store i32 %{{.+}}, i32* [[B_ADDR:%.+]], 456 // CHECK-32: [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]], 457 458 // We capture 2 VLA sizes in this target region 459 // CHECK: [[CELEMSIZE2:%.+]] = mul nuw i[[SZ]] 2, [[VLA0:%.+]] 460 // CHECK: [[CSIZE:%.+]] = mul nuw i[[SZ]] [[CELEMSIZE2]], 2 461 462 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 60 463 // CHECK: br i1 [[IF]], label %[[TRY:[^,]+]], label %[[FAIL:[^,]+]] 464 // CHECK: [[TRY]] 465 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 5, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SR:%[^,]+]], i32* getelementptr inbounds ([5 x i32], [5 x i32]* [[MAPT7]], i32 0, i32 0)) 466 // CHECK-DAG: [[BPR]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP:%.+]], i32 0, i32 0 467 // CHECK-DAG: [[PR]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P:%.+]], i32 0, i32 0 468 // CHECK-DAG: [[SR]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S:%.+]], i32 0, i32 0 469 // CHECK-DAG: [[SADDR0:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 [[IDX0:[0-9]+]] 470 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 [[IDX0]] 471 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 [[IDX0]] 472 // CHECK-DAG: [[SADDR1:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 [[IDX1:[0-9]+]] 473 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 [[IDX1]] 474 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 [[IDX1]] 475 // CHECK-DAG: [[SADDR2:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 [[IDX2:[0-9]+]] 476 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 [[IDX2]] 477 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 [[IDX2]] 478 // CHECK-DAG: [[SADDR3:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 [[IDX3:[0-9]+]] 479 // CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 [[IDX3]] 480 // CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 [[IDX3]] 481 482 // The names below are not necessarily consistent with the names used for the 483 // addresses above as some are repeated. 484 // CHECK-DAG: [[BP0:%[^,]+]] = inttoptr i[[SZ]] [[VLA0]] to i8* 485 // CHECK-DAG: [[P0:%[^,]+]] = inttoptr i[[SZ]] [[VLA0]] to i8* 486 // CHECK-DAG: store i8* [[BP0]], i8** {{%[^,]+}} 487 // CHECK-DAG: store i8* [[P0]], i8** {{%[^,]+}} 488 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}} 489 490 // CHECK-DAG: store i8* inttoptr (i[[SZ]] 2 to i8*), i8** {{%[^,]+}} 491 // CHECK-DAG: store i8* inttoptr (i[[SZ]] 2 to i8*), i8** {{%[^,]+}} 492 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}} 493 494 // CHECK-DAG: [[BP2:%[^,]+]] = inttoptr i[[SZ]] [[B_CVAL]] to i8* 495 // CHECK-DAG: [[P2:%[^,]+]] = inttoptr i[[SZ]] [[B_CVAL]] to i8* 496 // CHECK-DAG: store i8* [[BP2]], i8** {{%[^,]+}} 497 // CHECK-DAG: store i8* [[P2]], i8** {{%[^,]+}} 498 // CHECK-DAG: store i[[SZ]] 4, i[[SZ]]* {{%[^,]+}} 499 500 // CHECK-DAG: [[BP3:%[^,]+]] = bitcast [[S1]]* %{{.+}} to i8* 501 // CHECK-DAG: [[P3:%[^,]+]] = bitcast [[S1]]* %{{.+}} to i8* 502 // CHECK-DAG: store i8* [[BP3]], i8** {{%[^,]+}} 503 // CHECK-DAG: store i8* [[P3]], i8** {{%[^,]+}} 504 // CHECK-DAG: store i[[SZ]] 8, i[[SZ]]* {{%[^,]+}} 505 506 // CHECK-DAG: [[BP4:%[^,]+]] = bitcast i16* %{{.+}} to i8* 507 // CHECK-DAG: [[P4:%[^,]+]] = bitcast i16* %{{.+}} to i8* 508 // CHECK-DAG: store i8* [[BP4]], i8** {{%[^,]+}} 509 // CHECK-DAG: store i8* [[P4]], i8** {{%[^,]+}} 510 // CHECK-DAG: store i[[SZ]] [[CSIZE]], i[[SZ]]* {{%[^,]+}} 511 512 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 513 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 514 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 515 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 516 517 // CHECK: [[FAIL]] 518 // CHECK: call void [[HVT7:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 519 // CHECK-NEXT: br label %[[END]] 520 // CHECK: [[END]] 521 522 // 523 // CHECK: define {{.*}}[[FSTATIC]] 524 // 525 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 50 526 // CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]] 527 // CHECK: [[IFTHEN]] 528 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 4, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([4 x i[[SZ]]], [4 x i[[SZ]]]* [[SIZET6]], i32 0, i32 0), i32* getelementptr inbounds ([4 x i32], [4 x i32]* [[MAPT6]], i32 0, i32 0)) 529 // CHECK-DAG: [[BPR]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP:%.+]], i32 0, i32 0 530 // CHECK-DAG: [[PR]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P:%.+]], i32 0, i32 0 531 532 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 0 533 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 0 534 // CHECK-DAG: store i8* [[BP0:%[^,]+]], i8** [[BPADDR0]] 535 // CHECK-DAG: store i8* [[P0:%[^,]+]], i8** [[PADDR0]] 536 // CHECK-DAG: [[BP0]] = inttoptr i[[SZ]] [[VAL0:%.+]] to i8* 537 // CHECK-DAG: [[P0]] = inttoptr i[[SZ]] [[VAL0]] to i8* 538 539 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 1 540 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 1 541 // CHECK-DAG: store i8* [[BP1:%[^,]+]], i8** [[BPADDR1]] 542 // CHECK-DAG: store i8* [[P1:%[^,]+]], i8** [[PADDR1]] 543 // CHECK-DAG: [[BP1]] = inttoptr i[[SZ]] [[VAL1:%.+]] to i8* 544 // CHECK-DAG: [[P1]] = inttoptr i[[SZ]] [[VAL1]] to i8* 545 546 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 2 547 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 2 548 // CHECK-DAG: store i8* [[BP2:%[^,]+]], i8** [[BPADDR2]] 549 // CHECK-DAG: store i8* [[P2:%[^,]+]], i8** [[PADDR2]] 550 551 // CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 3 552 // CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 3 553 // CHECK-DAG: store i8* [[BP3:%[^,]+]], i8** [[BPADDR3]] 554 // CHECK-DAG: store i8* [[P3:%[^,]+]], i8** [[PADDR3]] 555 // CHECK-DAG: [[BP3]] = bitcast [10 x i32]* %{{.+}} to i8* 556 // CHECK-DAG: [[P3]] = bitcast [10 x i32]* %{{.+}} to i8* 557 558 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 559 // CHECK-NEXT: br label %[[IFEND:.+]] 560 561 // CHECK: [[IFELSE]] 562 // CHECK: store i32 -1, i32* [[RHV]], align 4 563 // CHECK-NEXT: br label %[[IFEND:.+]] 564 565 // CHECK: [[IFEND]] 566 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 567 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 568 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 569 // CHECK: [[FAIL]] 570 // CHECK: call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 571 // CHECK-NEXT: br label %[[END]] 572 // CHECK: [[END]] 573 574 // 575 // CHECK: define {{.*}}[[FTEMPLATE]] 576 // 577 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 40 578 // CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]] 579 // CHECK: [[IFTHEN]] 580 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 3, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([3 x i[[SZ]]], [3 x i[[SZ]]]* [[SIZET5]], i32 0, i32 0), i32* getelementptr inbounds ([3 x i32], [3 x i32]* [[MAPT5]], i32 0, i32 0)) 581 // CHECK-DAG: [[BPR]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP:%.+]], i32 0, i32 0 582 // CHECK-DAG: [[PR]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P:%.+]], i32 0, i32 0 583 584 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 0 585 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 0 586 // CHECK-DAG: store i8* [[BP0:%[^,]+]], i8** [[BPADDR0]] 587 // CHECK-DAG: store i8* [[P0:%[^,]+]], i8** [[PADDR0]] 588 // CHECK-DAG: [[BP0]] = inttoptr i[[SZ]] [[VAL0:%.+]] to i8* 589 // CHECK-DAG: [[P0]] = inttoptr i[[SZ]] [[VAL0]] to i8* 590 591 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 1 592 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 1 593 // CHECK-DAG: store i8* [[BP1:%[^,]+]], i8** [[BPADDR1]] 594 // CHECK-DAG: store i8* [[P1:%[^,]+]], i8** [[PADDR1]] 595 // CHECK-DAG: [[BP1]] = inttoptr i[[SZ]] [[VAL1:%.+]] to i8* 596 // CHECK-DAG: [[P1]] = inttoptr i[[SZ]] [[VAL1]] to i8* 597 598 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 2 599 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 2 600 // CHECK-DAG: store i8* [[BP2:%[^,]+]], i8** [[BPADDR2]] 601 // CHECK-DAG: store i8* [[P2:%[^,]+]], i8** [[PADDR2]] 602 // CHECK-DAG: [[BP2]] = bitcast [10 x i32]* %{{.+}} to i8* 603 // CHECK-DAG: [[P2]] = bitcast [10 x i32]* %{{.+}} to i8* 604 605 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 606 // CHECK-NEXT: br label %[[IFEND:.+]] 607 608 // CHECK: [[IFELSE]] 609 // CHECK: store i32 -1, i32* [[RHV]], align 4 610 // CHECK-NEXT: br label %[[IFEND:.+]] 611 612 // CHECK: [[IFEND]] 613 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 614 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 615 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 616 // CHECK: [[FAIL]] 617 // CHECK: call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 618 // CHECK-NEXT: br label %[[END]] 619 // CHECK: [[END]] 620 621 622 623 // Check that the offloading functions are emitted and that the arguments are 624 // correct and loaded correctly for the target regions of the callees of bar(). 625 626 // CHECK: define internal void [[HVT7]] 627 // Create local storage for each capture. 628 // CHECK: [[LOCAL_THIS:%.+]] = alloca [[S1]]* 629 // CHECK: [[LOCAL_B:%.+]] = alloca i[[SZ]] 630 // CHECK: [[LOCAL_VLA1:%.+]] = alloca i[[SZ]] 631 // CHECK: [[LOCAL_VLA2:%.+]] = alloca i[[SZ]] 632 // CHECK: [[LOCAL_C:%.+]] = alloca i16* 633 // CHECK-DAG: store [[S1]]* [[ARG_THIS:%.+]], [[S1]]** [[LOCAL_THIS]] 634 // CHECK-DAG: store i[[SZ]] [[ARG_B:%.+]], i[[SZ]]* [[LOCAL_B]] 635 // CHECK-DAG: store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]] 636 // CHECK-DAG: store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]] 637 // CHECK-DAG: store i16* [[ARG_C:%.+]], i16** [[LOCAL_C]] 638 // Store captures in the context. 639 // CHECK-DAG: [[REF_THIS:%.+]] = load [[S1]]*, [[S1]]** [[LOCAL_THIS]], 640 // CHECK-64-DAG:[[REF_B:%.+]] = bitcast i[[SZ]]* [[LOCAL_B]] to i32* 641 // CHECK-DAG: [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]], 642 // CHECK-DAG: [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]], 643 // CHECK-DAG: [[REF_C:%.+]] = load i16*, i16** [[LOCAL_C]], 644 // Use captures. 645 // CHECK-DAG: getelementptr inbounds [[S1]], [[S1]]* [[REF_THIS]], i32 0, i32 0 646 // CHECK-64-DAG:load i32, i32* [[REF_B]] 647 // CHECK-32-DAG:load i32, i32* [[LOCAL_B]] 648 // CHECK-DAG: getelementptr inbounds i16, i16* [[REF_C]], i[[SZ]] %{{.+}} 649 650 651 // CHECK: define internal void [[HVT6]] 652 // Create local storage for each capture. 653 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] 654 // CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]] 655 // CHECK: [[LOCAL_AAA:%.+]] = alloca i[[SZ]] 656 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* 657 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 658 // CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] 659 // CHECK-DAG: store i[[SZ]] [[ARG_AAA:%.+]], i[[SZ]]* [[LOCAL_AAA]] 660 // CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] 661 // Store captures in the context. 662 // CHECK-64-DAG: [[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 663 // CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* 664 // CHECK-DAG: [[REF_AAA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AAA]] to i8* 665 // CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], 666 // Use captures. 667 // CHECK-64-DAG: load i32, i32* [[REF_A]] 668 // CHECK-DAG: load i16, i16* [[REF_AA]] 669 // CHECK-DAG: load i8, i8* [[REF_AAA]] 670 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 671 // CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 672 673 // CHECK: define internal void [[HVT5]] 674 // Create local storage for each capture. 675 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] 676 // CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]] 677 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* 678 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 679 // CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] 680 // CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] 681 // Store captures in the context. 682 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 683 // CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* 684 // CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], 685 // Use captures. 686 // CHECK-64-DAG: load i32, i32* [[REF_A]] 687 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 688 // CHECK-DAG: load i16, i16* [[REF_AA]] 689 // CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 690 #endif 691
