1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 #ifndef _ASM_X86_HYPERV_H 3 #define _ASM_X86_HYPERV_H 4 5 #include <linux/types.h> 6 7 /* 8 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 9 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 10 */ 11 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 12 #define HYPERV_CPUID_INTERFACE 0x40000001 13 #define HYPERV_CPUID_VERSION 0x40000002 14 #define HYPERV_CPUID_FEATURES 0x40000003 15 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 16 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 17 18 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 19 #define HYPERV_CPUID_MIN 0x40000005 20 #define HYPERV_CPUID_MAX 0x4000ffff 21 22 /* 23 * Feature identification. EAX indicates which features are available 24 * to the partition based upon the current partition privileges. 25 */ 26 27 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ 28 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0) 29 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ 30 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1) 31 /* Partition reference TSC MSR is available */ 32 #define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9) 33 34 /* A partition's reference time stamp counter (TSC) page */ 35 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 36 37 /* 38 * There is a single feature flag that signifies if the partition has access 39 * to MSRs with local APIC and TSC frequencies. 40 */ 41 #define HV_X64_ACCESS_FREQUENCY_MSRS (1 << 11) 42 43 /* 44 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM 45 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available 46 */ 47 #define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2) 48 /* 49 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through 50 * HV_X64_MSR_STIMER3_COUNT) available 51 */ 52 #define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3) 53 /* 54 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 55 * are available 56 */ 57 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4) 58 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ 59 #define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5) 60 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ 61 #define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6) 62 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ 63 #define HV_X64_MSR_RESET_AVAILABLE (1 << 7) 64 /* 65 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, 66 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, 67 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available 68 */ 69 #define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8) 70 71 /* Frequency MSRs available */ 72 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE (1 << 8) 73 74 /* Crash MSR available */ 75 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10) 76 77 /* 78 * Feature identification: EBX indicates which flags were specified at 79 * partition creation. The format is the same as the partition creation 80 * flag structure defined in section Partition Creation Flags. 81 */ 82 #define HV_X64_CREATE_PARTITIONS (1 << 0) 83 #define HV_X64_ACCESS_PARTITION_ID (1 << 1) 84 #define HV_X64_ACCESS_MEMORY_POOL (1 << 2) 85 #define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3) 86 #define HV_X64_POST_MESSAGES (1 << 4) 87 #define HV_X64_SIGNAL_EVENTS (1 << 5) 88 #define HV_X64_CREATE_PORT (1 << 6) 89 #define HV_X64_CONNECT_PORT (1 << 7) 90 #define HV_X64_ACCESS_STATS (1 << 8) 91 #define HV_X64_DEBUGGING (1 << 11) 92 #define HV_X64_CPU_POWER_MANAGEMENT (1 << 12) 93 #define HV_X64_CONFIGURE_PROFILER (1 << 13) 94 95 /* 96 * Feature identification. EDX indicates which miscellaneous features 97 * are available to the partition. 98 */ 99 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 100 #define HV_X64_MWAIT_AVAILABLE (1 << 0) 101 /* Guest debugging support is available */ 102 #define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1) 103 /* Performance Monitor support is available*/ 104 #define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2) 105 /* Support for physical CPU dynamic partitioning events is available*/ 106 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3) 107 /* 108 * Support for passing hypercall input parameter block via XMM 109 * registers is available 110 */ 111 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4) 112 /* Support for a virtual guest idle state is available */ 113 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5) 114 /* Guest crash data handler available */ 115 #define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10) 116 117 /* 118 * Implementation recommendations. Indicates which behaviors the hypervisor 119 * recommends the OS implement for optimal performance. 120 */ 121 /* 122 * Recommend using hypercall for address space switches rather 123 * than MOV to CR3 instruction 124 */ 125 #define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0) 126 /* Recommend using hypercall for local TLB flushes rather 127 * than INVLPG or MOV to CR3 instructions */ 128 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1) 129 /* 130 * Recommend using hypercall for remote TLB flushes rather 131 * than inter-processor interrupts 132 */ 133 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2) 134 /* 135 * Recommend using MSRs for accessing APIC registers 136 * EOI, ICR and TPR rather than their memory-mapped counterparts 137 */ 138 #define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3) 139 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 140 #define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4) 141 /* 142 * Recommend using relaxed timing for this partition. If used, 143 * the VM should disable any watchdog timeouts that rely on the 144 * timely delivery of external interrupts 145 */ 146 #define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5) 147 148 /* 149 * Virtual APIC support 150 */ 151 #define HV_X64_DEPRECATING_AEOI_RECOMMENDED (1 << 9) 152 153 /* Recommend using the newer ExProcessorMasks interface */ 154 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11) 155 156 /* 157 * Crash notification flag. 158 */ 159 #define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63) 160 161 /* MSR used to identify the guest OS. */ 162 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 163 164 /* MSR used to setup pages used to communicate with the hypervisor. */ 165 #define HV_X64_MSR_HYPERCALL 0x40000001 166 167 /* MSR used to provide vcpu index */ 168 #define HV_X64_MSR_VP_INDEX 0x40000002 169 170 /* MSR used to reset the guest OS. */ 171 #define HV_X64_MSR_RESET 0x40000003 172 173 /* MSR used to provide vcpu runtime in 100ns units */ 174 #define HV_X64_MSR_VP_RUNTIME 0x40000010 175 176 /* MSR used to read the per-partition time reference counter */ 177 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 178 179 /* MSR used to retrieve the TSC frequency */ 180 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 181 182 /* MSR used to retrieve the local APIC timer frequency */ 183 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 184 185 /* Define the virtual APIC registers */ 186 #define HV_X64_MSR_EOI 0x40000070 187 #define HV_X64_MSR_ICR 0x40000071 188 #define HV_X64_MSR_TPR 0x40000072 189 #define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073 190 191 /* Define synthetic interrupt controller model specific registers. */ 192 #define HV_X64_MSR_SCONTROL 0x40000080 193 #define HV_X64_MSR_SVERSION 0x40000081 194 #define HV_X64_MSR_SIEFP 0x40000082 195 #define HV_X64_MSR_SIMP 0x40000083 196 #define HV_X64_MSR_EOM 0x40000084 197 #define HV_X64_MSR_SINT0 0x40000090 198 #define HV_X64_MSR_SINT1 0x40000091 199 #define HV_X64_MSR_SINT2 0x40000092 200 #define HV_X64_MSR_SINT3 0x40000093 201 #define HV_X64_MSR_SINT4 0x40000094 202 #define HV_X64_MSR_SINT5 0x40000095 203 #define HV_X64_MSR_SINT6 0x40000096 204 #define HV_X64_MSR_SINT7 0x40000097 205 #define HV_X64_MSR_SINT8 0x40000098 206 #define HV_X64_MSR_SINT9 0x40000099 207 #define HV_X64_MSR_SINT10 0x4000009A 208 #define HV_X64_MSR_SINT11 0x4000009B 209 #define HV_X64_MSR_SINT12 0x4000009C 210 #define HV_X64_MSR_SINT13 0x4000009D 211 #define HV_X64_MSR_SINT14 0x4000009E 212 #define HV_X64_MSR_SINT15 0x4000009F 213 214 /* 215 * Synthetic Timer MSRs. Four timers per vcpu. 216 */ 217 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 218 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 219 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 220 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 221 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 222 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 223 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 224 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 225 226 /* Hyper-V guest crash notification MSR's */ 227 #define HV_X64_MSR_CRASH_P0 0x40000100 228 #define HV_X64_MSR_CRASH_P1 0x40000101 229 #define HV_X64_MSR_CRASH_P2 0x40000102 230 #define HV_X64_MSR_CRASH_P3 0x40000103 231 #define HV_X64_MSR_CRASH_P4 0x40000104 232 #define HV_X64_MSR_CRASH_CTL 0x40000105 233 #define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63) 234 #define HV_X64_MSR_CRASH_PARAMS \ 235 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 236 237 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 238 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 239 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 240 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 241 242 /* Declare the various hypercall operations. */ 243 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 244 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 245 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 246 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 247 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 248 #define HVCALL_POST_MESSAGE 0x005c 249 #define HVCALL_SIGNAL_EVENT 0x005d 250 251 #define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001 252 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12 253 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \ 254 (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 255 256 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 257 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 258 259 #define HV_PROCESSOR_POWER_STATE_C0 0 260 #define HV_PROCESSOR_POWER_STATE_C1 1 261 #define HV_PROCESSOR_POWER_STATE_C2 2 262 #define HV_PROCESSOR_POWER_STATE_C3 3 263 264 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 265 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 266 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 267 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 268 269 enum HV_GENERIC_SET_FORMAT { 270 HV_GENERIC_SET_SPARCE_4K, 271 HV_GENERIC_SET_ALL, 272 }; 273 274 /* hypercall status code */ 275 #define HV_STATUS_SUCCESS 0 276 #define HV_STATUS_INVALID_HYPERCALL_CODE 2 277 #define HV_STATUS_INVALID_HYPERCALL_INPUT 3 278 #define HV_STATUS_INVALID_ALIGNMENT 4 279 #define HV_STATUS_INSUFFICIENT_MEMORY 11 280 #define HV_STATUS_INVALID_CONNECTION_ID 18 281 #define HV_STATUS_INSUFFICIENT_BUFFERS 19 282 283 typedef struct _HV_REFERENCE_TSC_PAGE { 284 __u32 tsc_sequence; 285 __u32 res1; 286 __u64 tsc_scale; 287 __s64 tsc_offset; 288 } HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; 289 290 /* Define the number of synthetic interrupt sources. */ 291 #define HV_SYNIC_SINT_COUNT (16) 292 /* Define the expected SynIC version. */ 293 #define HV_SYNIC_VERSION_1 (0x1) 294 295 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 296 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 297 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 298 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 299 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 300 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 301 302 #define HV_SYNIC_STIMER_COUNT (4) 303 304 /* Define synthetic interrupt controller message constants. */ 305 #define HV_MESSAGE_SIZE (256) 306 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 307 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 308 309 /* Define hypervisor message types. */ 310 enum hv_message_type { 311 HVMSG_NONE = 0x00000000, 312 313 /* Memory access messages. */ 314 HVMSG_UNMAPPED_GPA = 0x80000000, 315 HVMSG_GPA_INTERCEPT = 0x80000001, 316 317 /* Timer notification messages. */ 318 HVMSG_TIMER_EXPIRED = 0x80000010, 319 320 /* Error messages. */ 321 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 322 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 323 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 324 325 /* Trace buffer complete messages. */ 326 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 327 328 /* Platform-specific processor intercept messages. */ 329 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, 330 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 331 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 332 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 333 HVMSG_X64_APIC_EOI = 0x80010004, 334 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 335 }; 336 337 /* Define synthetic interrupt controller message flags. */ 338 union hv_message_flags { 339 __u8 asu8; 340 struct { 341 __u8 msg_pending:1; 342 __u8 reserved:7; 343 }; 344 }; 345 346 /* Define port identifier type. */ 347 union hv_port_id { 348 __u32 asu32; 349 struct { 350 __u32 id:24; 351 __u32 reserved:8; 352 } u; 353 }; 354 355 /* Define synthetic interrupt controller message header. */ 356 struct hv_message_header { 357 __u32 message_type; 358 __u8 payload_size; 359 union hv_message_flags message_flags; 360 __u8 reserved[2]; 361 union { 362 __u64 sender; 363 union hv_port_id port; 364 }; 365 }; 366 367 /* Define synthetic interrupt controller message format. */ 368 struct hv_message { 369 struct hv_message_header header; 370 union { 371 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 372 } u; 373 }; 374 375 /* Define the synthetic interrupt message page layout. */ 376 struct hv_message_page { 377 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 378 }; 379 380 /* Define timer message payload structure. */ 381 struct hv_timer_message_payload { 382 __u32 timer_index; 383 __u32 reserved; 384 __u64 expiration_time; /* When the timer expired */ 385 __u64 delivery_time; /* When the message was delivered */ 386 }; 387 388 #define HV_STIMER_ENABLE (1ULL << 0) 389 #define HV_STIMER_PERIODIC (1ULL << 1) 390 #define HV_STIMER_LAZY (1ULL << 2) 391 #define HV_STIMER_AUTOENABLE (1ULL << 3) 392 #define HV_STIMER_SINT(config) (__u8)(((config) >> 16) & 0x0F) 393 394 #endif 395
