1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark (at) gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #ifndef __MSM_DRM_H__ 26 #define __MSM_DRM_H__ 27 28 #include <stddef.h> 29 #include "drm.h" 30 31 #if defined(__cplusplus) 32 extern "C" { 33 #endif 34 35 /* Please note that modifications to all structs defined here are 36 * subject to backwards-compatibility constraints: 37 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit 38 * user/kernel compatibility 39 * 2) Keep fields aligned to their size 40 * 3) Because of how drm_ioctl() works, we can add new fields at 41 * the end of an ioctl if some care is taken: drm_ioctl() will 42 * zero out the new fields at the tail of the ioctl, so a zero 43 * value should have a backwards compatible meaning. And for 44 * output params, userspace won't see the newly added output 45 * fields.. so that has to be somehow ok. 46 */ 47 48 #define MSM_PIPE_NONE 0x00 49 #define MSM_PIPE_2D0 0x01 50 #define MSM_PIPE_2D1 0x02 51 #define MSM_PIPE_3D0 0x10 52 53 /* The pipe-id just uses the lower bits, so can be OR'd with flags in 54 * the upper 16 bits (which could be extended further, if needed, maybe 55 * we extend/overload the pipe-id some day to deal with multiple rings, 56 * but even then I don't think we need the full lower 16 bits). 57 */ 58 #define MSM_PIPE_ID_MASK 0xffff 59 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 60 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 61 62 /* timeouts are specified in clock-monotonic absolute times (to simplify 63 * restarting interrupted ioctls). The following struct is logically the 64 * same as 'struct timespec' but 32/64b ABI safe. 65 */ 66 struct drm_msm_timespec { 67 __s64 tv_sec; /* seconds */ 68 __s64 tv_nsec; /* nanoseconds */ 69 }; 70 71 #define MSM_PARAM_GPU_ID 0x01 72 #define MSM_PARAM_GMEM_SIZE 0x02 73 #define MSM_PARAM_CHIP_ID 0x03 74 #define MSM_PARAM_MAX_FREQ 0x04 75 #define MSM_PARAM_TIMESTAMP 0x05 76 77 struct drm_msm_param { 78 __u32 pipe; /* in, MSM_PIPE_x */ 79 __u32 param; /* in, MSM_PARAM_x */ 80 __u64 value; /* out (get_param) or in (set_param) */ 81 }; 82 83 /* 84 * GEM buffers: 85 */ 86 87 #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ 88 #define MSM_BO_GPU_READONLY 0x00000002 89 #define MSM_BO_CACHE_MASK 0x000f0000 90 /* cache modes */ 91 #define MSM_BO_CACHED 0x00010000 92 #define MSM_BO_WC 0x00020000 93 #define MSM_BO_UNCACHED 0x00040000 94 95 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ 96 MSM_BO_GPU_READONLY | \ 97 MSM_BO_CACHED | \ 98 MSM_BO_WC | \ 99 MSM_BO_UNCACHED) 100 101 struct drm_msm_gem_new { 102 __u64 size; /* in */ 103 __u32 flags; /* in, mask of MSM_BO_x */ 104 __u32 handle; /* out */ 105 }; 106 107 struct drm_msm_gem_info { 108 __u32 handle; /* in */ 109 __u32 pad; 110 __u64 offset; /* out, offset to pass to mmap() */ 111 }; 112 113 #define MSM_PREP_READ 0x01 114 #define MSM_PREP_WRITE 0x02 115 #define MSM_PREP_NOSYNC 0x04 116 117 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 118 119 struct drm_msm_gem_cpu_prep { 120 __u32 handle; /* in */ 121 __u32 op; /* in, mask of MSM_PREP_x */ 122 struct drm_msm_timespec timeout; /* in */ 123 }; 124 125 struct drm_msm_gem_cpu_fini { 126 __u32 handle; /* in */ 127 }; 128 129 /* 130 * Cmdstream Submission: 131 */ 132 133 /* The value written into the cmdstream is logically: 134 * 135 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or 136 * 137 * When we have GPU's w/ >32bit ptrs, it should be possible to deal 138 * with this by emit'ing two reloc entries with appropriate shift 139 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. 140 * 141 * NOTE that reloc's must be sorted by order of increasing submit_offset, 142 * otherwise EINVAL. 143 */ 144 struct drm_msm_gem_submit_reloc { 145 __u32 submit_offset; /* in, offset from submit_bo */ 146 __u32 or; /* in, value OR'd with result */ 147 __s32 shift; /* in, amount of left shift (can be negative) */ 148 __u32 reloc_idx; /* in, index of reloc_bo buffer */ 149 __u64 reloc_offset; /* in, offset from start of reloc_bo */ 150 }; 151 152 /* submit-types: 153 * BUF - this cmd buffer is executed normally. 154 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are 155 * processed normally, but the kernel does not setup an IB to 156 * this buffer in the first-level ringbuffer 157 * CTX_RESTORE_BUF - only executed if there has been a GPU context 158 * switch since the last SUBMIT ioctl 159 */ 160 #define MSM_SUBMIT_CMD_BUF 0x0001 161 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 162 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 163 struct drm_msm_gem_submit_cmd { 164 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */ 165 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */ 166 __u32 submit_offset; /* in, offset into submit_bo */ 167 __u32 size; /* in, cmdstream size */ 168 __u32 pad; 169 __u32 nr_relocs; /* in, number of submit_reloc's */ 170 __u64 __user relocs; /* in, ptr to array of submit_reloc's */ 171 }; 172 173 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the 174 * cmdstream buffer(s) themselves or reloc entries) has one (and only 175 * one) entry in the submit->bos[] table. 176 * 177 * As a optimization, the current buffer (gpu virtual address) can be 178 * passed back through the 'presumed' field. If on a subsequent reloc, 179 * userspace passes back a 'presumed' address that is still valid, 180 * then patching the cmdstream for this entry is skipped. This can 181 * avoid kernel needing to map/access the cmdstream bo in the common 182 * case. 183 */ 184 #define MSM_SUBMIT_BO_READ 0x0001 185 #define MSM_SUBMIT_BO_WRITE 0x0002 186 187 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 188 189 struct drm_msm_gem_submit_bo { 190 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */ 191 __u32 handle; /* in, GEM handle */ 192 __u64 presumed; /* in/out, presumed buffer address */ 193 }; 194 195 /* Valid submit ioctl flags: */ 196 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */ 197 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */ 198 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */ 199 #define MSM_SUBMIT_FLAGS ( \ 200 MSM_SUBMIT_NO_IMPLICIT | \ 201 MSM_SUBMIT_FENCE_FD_IN | \ 202 MSM_SUBMIT_FENCE_FD_OUT | \ 203 0) 204 205 /* Each cmdstream submit consists of a table of buffers involved, and 206 * one or more cmdstream buffers. This allows for conditional execution 207 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 208 */ 209 struct drm_msm_gem_submit { 210 __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ 211 __u32 fence; /* out */ 212 __u32 nr_bos; /* in, number of submit_bo's */ 213 __u32 nr_cmds; /* in, number of submit_cmd's */ 214 __u64 __user bos; /* in, ptr to array of submit_bo's */ 215 __u64 __user cmds; /* in, ptr to array of submit_cmd's */ 216 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ 217 }; 218 219 /* The normal way to synchronize with the GPU is just to CPU_PREP on 220 * a buffer if you need to access it from the CPU (other cmdstream 221 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all 222 * handle the required synchronization under the hood). This ioctl 223 * mainly just exists as a way to implement the gallium pipe_fence 224 * APIs without requiring a dummy bo to synchronize on. 225 */ 226 struct drm_msm_wait_fence { 227 __u32 fence; /* in */ 228 __u32 pad; 229 struct drm_msm_timespec timeout; /* in */ 230 }; 231 232 /* madvise provides a way to tell the kernel in case a buffers contents 233 * can be discarded under memory pressure, which is useful for userspace 234 * bo cache where we want to optimistically hold on to buffer allocate 235 * and potential mmap, but allow the pages to be discarded under memory 236 * pressure. 237 * 238 * Typical usage would involve madvise(DONTNEED) when buffer enters BO 239 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. 240 * In the WILLNEED case, 'retained' indicates to userspace whether the 241 * backing pages still exist. 242 */ 243 #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ 244 #define MSM_MADV_DONTNEED 1 /* backing pages not needed */ 245 #define __MSM_MADV_PURGED 2 /* internal state */ 246 247 struct drm_msm_gem_madvise { 248 __u32 handle; /* in, GEM handle */ 249 __u32 madv; /* in, MSM_MADV_x */ 250 __u32 retained; /* out, whether backing store still exists */ 251 }; 252 253 #define DRM_MSM_GET_PARAM 0x00 254 /* placeholder: 255 #define DRM_MSM_SET_PARAM 0x01 256 */ 257 #define DRM_MSM_GEM_NEW 0x02 258 #define DRM_MSM_GEM_INFO 0x03 259 #define DRM_MSM_GEM_CPU_PREP 0x04 260 #define DRM_MSM_GEM_CPU_FINI 0x05 261 #define DRM_MSM_GEM_SUBMIT 0x06 262 #define DRM_MSM_WAIT_FENCE 0x07 263 #define DRM_MSM_GEM_MADVISE 0x08 264 #define DRM_MSM_NUM_IOCTLS 0x09 265 266 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 267 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 268 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 269 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 270 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 271 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 272 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 273 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 274 275 #if defined(__cplusplus) 276 } 277 #endif 278 279 #endif /* __MSM_DRM_H__ */ 280
