1 /* 2 * Copyright (c) 2015 The WebM project authors. All Rights Reserved. 3 * 4 * Use of this source code is governed by a BSD-style license 5 * that can be found in the LICENSE file in the root of the source 6 * tree. An additional intellectual property rights grant can be found 7 * in the file PATENTS. All contributing project authors may 8 * be found in the AUTHORS file in the root of the source tree. 9 */ 10 11 #include <arm_neon.h> 12 13 #include "./vpx_config.h" 14 #include "vpx_dsp/txfm_common.h" 15 #include "vpx_dsp/vpx_dsp_common.h" 16 #include "vpx_dsp/arm/idct_neon.h" 17 #include "vpx_dsp/arm/mem_neon.h" 18 19 void vpx_fdct8x8_neon(const int16_t *input, tran_low_t *final_output, 20 int stride) { 21 int i; 22 // stage 1 23 int16x8_t input_0 = vshlq_n_s16(vld1q_s16(&input[0 * stride]), 2); 24 int16x8_t input_1 = vshlq_n_s16(vld1q_s16(&input[1 * stride]), 2); 25 int16x8_t input_2 = vshlq_n_s16(vld1q_s16(&input[2 * stride]), 2); 26 int16x8_t input_3 = vshlq_n_s16(vld1q_s16(&input[3 * stride]), 2); 27 int16x8_t input_4 = vshlq_n_s16(vld1q_s16(&input[4 * stride]), 2); 28 int16x8_t input_5 = vshlq_n_s16(vld1q_s16(&input[5 * stride]), 2); 29 int16x8_t input_6 = vshlq_n_s16(vld1q_s16(&input[6 * stride]), 2); 30 int16x8_t input_7 = vshlq_n_s16(vld1q_s16(&input[7 * stride]), 2); 31 for (i = 0; i < 2; ++i) { 32 int16x8_t out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7; 33 const int16x8_t v_s0 = vaddq_s16(input_0, input_7); 34 const int16x8_t v_s1 = vaddq_s16(input_1, input_6); 35 const int16x8_t v_s2 = vaddq_s16(input_2, input_5); 36 const int16x8_t v_s3 = vaddq_s16(input_3, input_4); 37 const int16x8_t v_s4 = vsubq_s16(input_3, input_4); 38 const int16x8_t v_s5 = vsubq_s16(input_2, input_5); 39 const int16x8_t v_s6 = vsubq_s16(input_1, input_6); 40 const int16x8_t v_s7 = vsubq_s16(input_0, input_7); 41 // fdct4(step, step); 42 int16x8_t v_x0 = vaddq_s16(v_s0, v_s3); 43 int16x8_t v_x1 = vaddq_s16(v_s1, v_s2); 44 int16x8_t v_x2 = vsubq_s16(v_s1, v_s2); 45 int16x8_t v_x3 = vsubq_s16(v_s0, v_s3); 46 // fdct4(step, step); 47 int32x4_t v_t0_lo = vaddl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1)); 48 int32x4_t v_t0_hi = vaddl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1)); 49 int32x4_t v_t1_lo = vsubl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1)); 50 int32x4_t v_t1_hi = vsubl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1)); 51 int32x4_t v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), cospi_24_64); 52 int32x4_t v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), cospi_24_64); 53 int32x4_t v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), cospi_24_64); 54 int32x4_t v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), cospi_24_64); 55 v_t2_lo = vmlal_n_s16(v_t2_lo, vget_low_s16(v_x3), cospi_8_64); 56 v_t2_hi = vmlal_n_s16(v_t2_hi, vget_high_s16(v_x3), cospi_8_64); 57 v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x2), cospi_8_64); 58 v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x2), cospi_8_64); 59 v_t0_lo = vmulq_n_s32(v_t0_lo, cospi_16_64); 60 v_t0_hi = vmulq_n_s32(v_t0_hi, cospi_16_64); 61 v_t1_lo = vmulq_n_s32(v_t1_lo, cospi_16_64); 62 v_t1_hi = vmulq_n_s32(v_t1_hi, cospi_16_64); 63 { 64 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS); 65 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS); 66 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS); 67 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS); 68 const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS); 69 const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS); 70 const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS); 71 const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS); 72 out_0 = vcombine_s16(a, c); // 00 01 02 03 40 41 42 43 73 out_2 = vcombine_s16(e, g); // 20 21 22 23 60 61 62 63 74 out_4 = vcombine_s16(b, d); // 04 05 06 07 44 45 46 47 75 out_6 = vcombine_s16(f, h); // 24 25 26 27 64 65 66 67 76 } 77 // Stage 2 78 v_x0 = vsubq_s16(v_s6, v_s5); 79 v_x1 = vaddq_s16(v_s6, v_s5); 80 v_t0_lo = vmull_n_s16(vget_low_s16(v_x0), cospi_16_64); 81 v_t0_hi = vmull_n_s16(vget_high_s16(v_x0), cospi_16_64); 82 v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), cospi_16_64); 83 v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), cospi_16_64); 84 { 85 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS); 86 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS); 87 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS); 88 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS); 89 const int16x8_t ab = vcombine_s16(a, b); 90 const int16x8_t cd = vcombine_s16(c, d); 91 // Stage 3 92 v_x0 = vaddq_s16(v_s4, ab); 93 v_x1 = vsubq_s16(v_s4, ab); 94 v_x2 = vsubq_s16(v_s7, cd); 95 v_x3 = vaddq_s16(v_s7, cd); 96 } 97 // Stage 4 98 v_t0_lo = vmull_n_s16(vget_low_s16(v_x3), cospi_4_64); 99 v_t0_hi = vmull_n_s16(vget_high_s16(v_x3), cospi_4_64); 100 v_t0_lo = vmlal_n_s16(v_t0_lo, vget_low_s16(v_x0), cospi_28_64); 101 v_t0_hi = vmlal_n_s16(v_t0_hi, vget_high_s16(v_x0), cospi_28_64); 102 v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), cospi_12_64); 103 v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), cospi_12_64); 104 v_t1_lo = vmlal_n_s16(v_t1_lo, vget_low_s16(v_x2), cospi_20_64); 105 v_t1_hi = vmlal_n_s16(v_t1_hi, vget_high_s16(v_x2), cospi_20_64); 106 v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), cospi_12_64); 107 v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), cospi_12_64); 108 v_t2_lo = vmlsl_n_s16(v_t2_lo, vget_low_s16(v_x1), cospi_20_64); 109 v_t2_hi = vmlsl_n_s16(v_t2_hi, vget_high_s16(v_x1), cospi_20_64); 110 v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), cospi_28_64); 111 v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), cospi_28_64); 112 v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x0), cospi_4_64); 113 v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x0), cospi_4_64); 114 { 115 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS); 116 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS); 117 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS); 118 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS); 119 const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS); 120 const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS); 121 const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS); 122 const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS); 123 out_1 = vcombine_s16(a, c); // 10 11 12 13 50 51 52 53 124 out_3 = vcombine_s16(e, g); // 30 31 32 33 70 71 72 73 125 out_5 = vcombine_s16(b, d); // 14 15 16 17 54 55 56 57 126 out_7 = vcombine_s16(f, h); // 34 35 36 37 74 75 76 77 127 } 128 // transpose 8x8 129 // Can't use transpose_s16_8x8() because the values are arranged in two 4x8 130 // columns. 131 { 132 // 00 01 02 03 40 41 42 43 133 // 10 11 12 13 50 51 52 53 134 // 20 21 22 23 60 61 62 63 135 // 30 31 32 33 70 71 72 73 136 // 04 05 06 07 44 45 46 47 137 // 14 15 16 17 54 55 56 57 138 // 24 25 26 27 64 65 66 67 139 // 34 35 36 37 74 75 76 77 140 const int32x4x2_t r02_s32 = 141 vtrnq_s32(vreinterpretq_s32_s16(out_0), vreinterpretq_s32_s16(out_2)); 142 const int32x4x2_t r13_s32 = 143 vtrnq_s32(vreinterpretq_s32_s16(out_1), vreinterpretq_s32_s16(out_3)); 144 const int32x4x2_t r46_s32 = 145 vtrnq_s32(vreinterpretq_s32_s16(out_4), vreinterpretq_s32_s16(out_6)); 146 const int32x4x2_t r57_s32 = 147 vtrnq_s32(vreinterpretq_s32_s16(out_5), vreinterpretq_s32_s16(out_7)); 148 const int16x8x2_t r01_s16 = 149 vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[0]), 150 vreinterpretq_s16_s32(r13_s32.val[0])); 151 const int16x8x2_t r23_s16 = 152 vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[1]), 153 vreinterpretq_s16_s32(r13_s32.val[1])); 154 const int16x8x2_t r45_s16 = 155 vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[0]), 156 vreinterpretq_s16_s32(r57_s32.val[0])); 157 const int16x8x2_t r67_s16 = 158 vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[1]), 159 vreinterpretq_s16_s32(r57_s32.val[1])); 160 input_0 = r01_s16.val[0]; 161 input_1 = r01_s16.val[1]; 162 input_2 = r23_s16.val[0]; 163 input_3 = r23_s16.val[1]; 164 input_4 = r45_s16.val[0]; 165 input_5 = r45_s16.val[1]; 166 input_6 = r67_s16.val[0]; 167 input_7 = r67_s16.val[1]; 168 // 00 10 20 30 40 50 60 70 169 // 01 11 21 31 41 51 61 71 170 // 02 12 22 32 42 52 62 72 171 // 03 13 23 33 43 53 63 73 172 // 04 14 24 34 44 54 64 74 173 // 05 15 25 35 45 55 65 75 174 // 06 16 26 36 46 56 66 76 175 // 07 17 27 37 47 57 67 77 176 } 177 } // for 178 { 179 // from vpx_dct_sse2.c 180 // Post-condition (division by two) 181 // division of two 16 bits signed numbers using shifts 182 // n / 2 = (n - (n >> 15)) >> 1 183 const int16x8_t sign_in0 = vshrq_n_s16(input_0, 15); 184 const int16x8_t sign_in1 = vshrq_n_s16(input_1, 15); 185 const int16x8_t sign_in2 = vshrq_n_s16(input_2, 15); 186 const int16x8_t sign_in3 = vshrq_n_s16(input_3, 15); 187 const int16x8_t sign_in4 = vshrq_n_s16(input_4, 15); 188 const int16x8_t sign_in5 = vshrq_n_s16(input_5, 15); 189 const int16x8_t sign_in6 = vshrq_n_s16(input_6, 15); 190 const int16x8_t sign_in7 = vshrq_n_s16(input_7, 15); 191 input_0 = vhsubq_s16(input_0, sign_in0); 192 input_1 = vhsubq_s16(input_1, sign_in1); 193 input_2 = vhsubq_s16(input_2, sign_in2); 194 input_3 = vhsubq_s16(input_3, sign_in3); 195 input_4 = vhsubq_s16(input_4, sign_in4); 196 input_5 = vhsubq_s16(input_5, sign_in5); 197 input_6 = vhsubq_s16(input_6, sign_in6); 198 input_7 = vhsubq_s16(input_7, sign_in7); 199 // store results 200 store_s16q_to_tran_low(final_output + 0 * 8, input_0); 201 store_s16q_to_tran_low(final_output + 1 * 8, input_1); 202 store_s16q_to_tran_low(final_output + 2 * 8, input_2); 203 store_s16q_to_tran_low(final_output + 3 * 8, input_3); 204 store_s16q_to_tran_low(final_output + 4 * 8, input_4); 205 store_s16q_to_tran_low(final_output + 5 * 8, input_5); 206 store_s16q_to_tran_low(final_output + 6 * 8, input_6); 207 store_s16q_to_tran_low(final_output + 7 * 8, input_7); 208 } 209 } 210
