1 /* 2 * Copyright (c) 2010 The WebM project authors. All Rights Reserved. 3 * 4 * Use of this source code is governed by a BSD-style license 5 * that can be found in the LICENSE file in the root of the source 6 * tree. An additional intellectual property rights grant can be found 7 * in the file PATENTS. All contributing project authors may 8 * be found in the AUTHORS file in the root of the source tree. 9 */ 10 11 #ifndef VPX_PORTS_X86_H_ 12 #define VPX_PORTS_X86_H_ 13 #include <stdlib.h> 14 15 #if defined(_MSC_VER) 16 #include <intrin.h> /* For __cpuidex, __rdtsc */ 17 #endif 18 19 #include "vpx_config.h" 20 #include "vpx/vpx_integer.h" 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 typedef enum { 27 VPX_CPU_UNKNOWN = -1, 28 VPX_CPU_AMD, 29 VPX_CPU_AMD_OLD, 30 VPX_CPU_CENTAUR, 31 VPX_CPU_CYRIX, 32 VPX_CPU_INTEL, 33 VPX_CPU_NEXGEN, 34 VPX_CPU_NSC, 35 VPX_CPU_RISE, 36 VPX_CPU_SIS, 37 VPX_CPU_TRANSMETA, 38 VPX_CPU_TRANSMETA_OLD, 39 VPX_CPU_UMC, 40 VPX_CPU_VIA, 41 42 VPX_CPU_LAST 43 } vpx_cpu_t; 44 45 #if defined(__GNUC__) && __GNUC__ || defined(__ANDROID__) 46 #if ARCH_X86_64 47 #define cpuid(func, func2, ax, bx, cx, dx) \ 48 __asm__ __volatile__("cpuid \n\t" \ 49 : "=a"(ax), "=b"(bx), "=c"(cx), "=d"(dx) \ 50 : "a"(func), "c"(func2)); 51 #else 52 #define cpuid(func, func2, ax, bx, cx, dx) \ 53 __asm__ __volatile__( \ 54 "mov %%ebx, %%edi \n\t" \ 55 "cpuid \n\t" \ 56 "xchg %%edi, %%ebx \n\t" \ 57 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \ 58 : "a"(func), "c"(func2)); 59 #endif 60 #elif defined(__SUNPRO_C) || \ 61 defined(__SUNPRO_CC) /* end __GNUC__ or __ANDROID__*/ 62 #if ARCH_X86_64 63 #define cpuid(func, func2, ax, bx, cx, dx) \ 64 asm volatile( \ 65 "xchg %rsi, %rbx \n\t" \ 66 "cpuid \n\t" \ 67 "movl %ebx, %edi \n\t" \ 68 "xchg %rsi, %rbx \n\t" \ 69 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \ 70 : "a"(func), "c"(func2)); 71 #else 72 #define cpuid(func, func2, ax, bx, cx, dx) \ 73 asm volatile( \ 74 "pushl %ebx \n\t" \ 75 "cpuid \n\t" \ 76 "movl %ebx, %edi \n\t" \ 77 "popl %ebx \n\t" \ 78 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \ 79 : "a"(func), "c"(func2)); 80 #endif 81 #else /* end __SUNPRO__ */ 82 #if ARCH_X86_64 83 #if defined(_MSC_VER) && _MSC_VER > 1500 84 #define cpuid(func, func2, a, b, c, d) \ 85 do { \ 86 int regs[4]; \ 87 __cpuidex(regs, func, func2); \ 88 a = regs[0]; \ 89 b = regs[1]; \ 90 c = regs[2]; \ 91 d = regs[3]; \ 92 } while (0) 93 #else 94 #define cpuid(func, func2, a, b, c, d) \ 95 do { \ 96 int regs[4]; \ 97 __cpuid(regs, func); \ 98 a = regs[0]; \ 99 b = regs[1]; \ 100 c = regs[2]; \ 101 d = regs[3]; \ 102 } while (0) 103 #endif 104 #else 105 #define cpuid(func, func2, a, b, c, d) \ 106 __asm mov eax, func __asm mov ecx, func2 __asm cpuid __asm mov a, \ 107 eax __asm mov b, ebx __asm mov c, ecx __asm mov d, edx 108 #endif 109 #endif /* end others */ 110 111 // NaCl has no support for xgetbv or the raw opcode. 112 #if !defined(__native_client__) && (defined(__i386__) || defined(__x86_64__)) 113 static INLINE uint64_t xgetbv(void) { 114 const uint32_t ecx = 0; 115 uint32_t eax, edx; 116 // Use the raw opcode for xgetbv for compatibility with older toolchains. 117 __asm__ volatile(".byte 0x0f, 0x01, 0xd0\n" 118 : "=a"(eax), "=d"(edx) 119 : "c"(ecx)); 120 return ((uint64_t)edx << 32) | eax; 121 } 122 #elif (defined(_M_X64) || defined(_M_IX86)) && defined(_MSC_FULL_VER) && \ 123 _MSC_FULL_VER >= 160040219 // >= VS2010 SP1 124 #include <immintrin.h> 125 #define xgetbv() _xgetbv(0) 126 #elif defined(_MSC_VER) && defined(_M_IX86) 127 static INLINE uint64_t xgetbv(void) { 128 uint32_t eax_, edx_; 129 __asm { 130 xor ecx, ecx // ecx = 0 131 // Use the raw opcode for xgetbv for compatibility with older toolchains. 132 __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0 133 mov eax_, eax 134 mov edx_, edx 135 } 136 return ((uint64_t)edx_ << 32) | eax_; 137 } 138 #else 139 #define xgetbv() 0U // no AVX for older x64 or unrecognized toolchains. 140 #endif 141 142 #if defined(_MSC_VER) && _MSC_VER >= 1700 143 #undef NOMINMAX 144 #define NOMINMAX 145 #ifndef WIN32_LEAN_AND_MEAN 146 #define WIN32_LEAN_AND_MEAN 147 #endif 148 #include <windows.h> 149 #if WINAPI_FAMILY_PARTITION(WINAPI_FAMILY_APP) 150 #define getenv(x) NULL 151 #endif 152 #endif 153 154 #define HAS_MMX 0x001 155 #define HAS_SSE 0x002 156 #define HAS_SSE2 0x004 157 #define HAS_SSE3 0x008 158 #define HAS_SSSE3 0x010 159 #define HAS_SSE4_1 0x020 160 #define HAS_AVX 0x040 161 #define HAS_AVX2 0x080 162 #define HAS_AVX512 0x100 163 #ifndef BIT 164 #define BIT(n) (1u << n) 165 #endif 166 167 static INLINE int x86_simd_caps(void) { 168 unsigned int flags = 0; 169 unsigned int mask = ~0; 170 unsigned int max_cpuid_val, reg_eax, reg_ebx, reg_ecx, reg_edx; 171 char *env; 172 (void)reg_ebx; 173 174 /* See if the CPU capabilities are being overridden by the environment */ 175 env = getenv("VPX_SIMD_CAPS"); 176 177 if (env && *env) return (int)strtol(env, NULL, 0); 178 179 env = getenv("VPX_SIMD_CAPS_MASK"); 180 181 if (env && *env) mask = (unsigned int)strtoul(env, NULL, 0); 182 183 /* Ensure that the CPUID instruction supports extended features */ 184 cpuid(0, 0, max_cpuid_val, reg_ebx, reg_ecx, reg_edx); 185 186 if (max_cpuid_val < 1) return 0; 187 188 /* Get the standard feature flags */ 189 cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx); 190 191 if (reg_edx & BIT(23)) flags |= HAS_MMX; 192 193 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */ 194 195 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */ 196 197 if (reg_ecx & BIT(0)) flags |= HAS_SSE3; 198 199 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3; 200 201 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1; 202 203 // bits 27 (OSXSAVE) & 28 (256-bit AVX) 204 if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) { 205 if ((xgetbv() & 0x6) == 0x6) { 206 flags |= HAS_AVX; 207 208 if (max_cpuid_val >= 7) { 209 /* Get the leaf 7 feature flags. Needed to check for AVX2 support */ 210 cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx); 211 212 if (reg_ebx & BIT(5)) flags |= HAS_AVX2; 213 214 // bits 16 (AVX-512F) & 17 (AVX-512DQ) & 28 (AVX-512CD) & 215 // 30 (AVX-512BW) & 32 (AVX-512VL) 216 if ((reg_ebx & (BIT(16) | BIT(17) | BIT(28) | BIT(30) | BIT(31))) == 217 (BIT(16) | BIT(17) | BIT(28) | BIT(30) | BIT(31))) 218 flags |= HAS_AVX512; 219 } 220 } 221 } 222 223 return flags & mask; 224 } 225 226 // Note: 227 // 32-bit CPU cycle counter is light-weighted for most function performance 228 // measurement. For large function (CPU time > a couple of seconds), 64-bit 229 // counter should be used. 230 // 32-bit CPU cycle counter 231 static INLINE unsigned int x86_readtsc(void) { 232 #if defined(__GNUC__) && __GNUC__ 233 unsigned int tsc; 234 __asm__ __volatile__("rdtsc\n\t" : "=a"(tsc) :); 235 return tsc; 236 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC) 237 unsigned int tsc; 238 asm volatile("rdtsc\n\t" : "=a"(tsc) :); 239 return tsc; 240 #else 241 #if ARCH_X86_64 242 return (unsigned int)__rdtsc(); 243 #else 244 __asm rdtsc; 245 #endif 246 #endif 247 } 248 // 64-bit CPU cycle counter 249 static INLINE uint64_t x86_readtsc64(void) { 250 #if defined(__GNUC__) && __GNUC__ 251 uint32_t hi, lo; 252 __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi)); 253 return ((uint64_t)hi << 32) | lo; 254 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC) 255 uint_t hi, lo; 256 asm volatile("rdtsc\n\t" : "=a"(lo), "=d"(hi)); 257 return ((uint64_t)hi << 32) | lo; 258 #else 259 #if ARCH_X86_64 260 return (uint64_t)__rdtsc(); 261 #else 262 __asm rdtsc; 263 #endif 264 #endif 265 } 266 267 #if defined(__GNUC__) && __GNUC__ 268 #define x86_pause_hint() __asm__ __volatile__("pause \n\t") 269 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC) 270 #define x86_pause_hint() asm volatile("pause \n\t") 271 #else 272 #if ARCH_X86_64 273 #define x86_pause_hint() _mm_pause(); 274 #else 275 #define x86_pause_hint() __asm pause 276 #endif 277 #endif 278 279 #if defined(__GNUC__) && __GNUC__ 280 static void x87_set_control_word(unsigned short mode) { 281 __asm__ __volatile__("fldcw %0" : : "m"(*&mode)); 282 } 283 static unsigned short x87_get_control_word(void) { 284 unsigned short mode; 285 __asm__ __volatile__("fstcw %0\n\t" : "=m"(*&mode) :); 286 return mode; 287 } 288 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC) 289 static void x87_set_control_word(unsigned short mode) { 290 asm volatile("fldcw %0" : : "m"(*&mode)); 291 } 292 static unsigned short x87_get_control_word(void) { 293 unsigned short mode; 294 asm volatile("fstcw %0\n\t" : "=m"(*&mode) :); 295 return mode; 296 } 297 #elif ARCH_X86_64 298 /* No fldcw intrinsics on Windows x64, punt to external asm */ 299 extern void vpx_winx64_fldcw(unsigned short mode); 300 extern unsigned short vpx_winx64_fstcw(void); 301 #define x87_set_control_word vpx_winx64_fldcw 302 #define x87_get_control_word vpx_winx64_fstcw 303 #else 304 static void x87_set_control_word(unsigned short mode) { 305 __asm { fldcw mode } 306 } 307 static unsigned short x87_get_control_word(void) { 308 unsigned short mode; 309 __asm { fstcw mode } 310 return mode; 311 } 312 #endif 313 314 static INLINE unsigned int x87_set_double_precision(void) { 315 unsigned int mode = x87_get_control_word(); 316 x87_set_control_word((mode & ~0x300) | 0x200); 317 return mode; 318 } 319 320 extern void vpx_reset_mmx_state(void); 321 322 #ifdef __cplusplus 323 } // extern "C" 324 #endif 325 326 #endif // VPX_PORTS_X86_H_ 327
