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      1 @/******************************************************************************
      2 @ *
      3 @ * Copyright (C) 2018 The Android Open Source Project
      4 @ *
      5 @ * Licensed under the Apache License, Version 2.0 (the "License");
      6 @ * you may not use this file except in compliance with the License.
      7 @ * You may obtain a copy of the License at:
      8 @ *
      9 @ * http:@www.apache.org/licenses/LICENSE-2.0
     10 @ *
     11 @ * Unless required by applicable law or agreed to in writing, software
     12 @ * distributed under the License is distributed on an "AS IS" BASIS,
     13 @ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     14 @ * See the License for the specific language governing permissions and
     15 @ * limitations under the License.
     16 @ *
     17 @ *****************************************************************************
     18 @ * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
     19 @*/
     20 
     21 
     22 .text
     23 .p2align 2
     24 
     25     .global ixheaacd_calc_pre_twid_armv7
     26 ixheaacd_calc_pre_twid_armv7:
     27 
     28     STMFD           sp!, {r4-r12, r14}
     29     VPUSH           {D8-D15}
     30     LDR             R4, [SP, #104]
     31     LDR             R5, [SP, #108]
     32     ADD             R6, R0, R3, LSL #3
     33     SUB             R6, R6, #12
     34     MOV             R7, #-16
     35 
     36 LOOP1:
     37     VLD1.32         {D0, D1}, [R4]!
     38     VLD1.32         {D2, D3}, [R5]!
     39     VLD2.32         {D4, D5}, [R0]!
     40     VLD2.32         {D6, D7}, [R0]!
     41     VLD2.32         {D8, D9}, [R6], R7
     42     VLD2.32         {D10, D11}, [R6], R7
     43 
     44     VREV64.32       D8, D8
     45     VREV64.32       D9, D10
     46     VNEG.S32        D5, D4
     47     VNEG.S32        D7, D6
     48 
     49     VMULL.S32       Q6, D0, D5
     50     VMULL.S32       Q7, D2, D8
     51     VMULL.S32       Q8, D0, D8
     52     VMULL.S32       Q9, D2, D4
     53     VMULL.S32       Q10, D1, D7
     54     VMULL.S32       Q11, D9, D3
     55     VMULL.S32       Q12, D1, D9
     56     VMULL.S32       Q13, D3, D6
     57 
     58 
     59     VSHRN.S64       D12, Q6, #32
     60     VSHRN.S64       D14, Q7, #32
     61     VSHRN.S64       D16, Q8, #32
     62     VSHRN.S64       D18, Q9, #32
     63     VSHRN.S64       D20, Q10, #32
     64     VSHRN.S64       D22, Q11, #32
     65     VSHRN.S64       D24, Q12, #32
     66     VSHRN.S64       D26, Q13, #32
     67 
     68     VSUB.I32        D0, D12, D14
     69     VSUB.I32        D2, D16, D18
     70     VSUB.I32        D1, D20, D22
     71     VSUB.I32        D3, D24, D26
     72 
     73     SUBS            R3, R3, #4
     74     VST1.32         {D0, D1}, [R1]!
     75     VST1.32         {D2, D3}, [R2]!
     76 
     77     BGT             LOOP1
     78     VPOP            {D8-D15}
     79     LDMFD           sp!, {r4-r12, r15}
     80 
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