1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Config/config.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/FileSystem.h" 22 #include "llvm/Support/raw_ostream.h" 23 #include <string.h> 24 25 // Include the platform-specific parts of this class. 26 #ifdef LLVM_ON_UNIX 27 #include "Unix/Host.inc" 28 #endif 29 #ifdef LLVM_ON_WIN32 30 #include "Windows/Host.inc" 31 #endif 32 #ifdef _MSC_VER 33 #include <intrin.h> 34 #endif 35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 36 #include <mach/host_info.h> 37 #include <mach/mach.h> 38 #include <mach/mach_host.h> 39 #include <mach/machine.h> 40 #endif 41 42 #define DEBUG_TYPE "host-detection" 43 44 //===----------------------------------------------------------------------===// 45 // 46 // Implementations of the CPU detection routines 47 // 48 //===----------------------------------------------------------------------===// 49 50 using namespace llvm; 51 52 #if defined(__linux__) 53 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) { 54 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting 55 // memory buffer because the 'file' has 0 size (it can be read from only 56 // as a stream). 57 58 int FD; 59 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD); 60 if (EC) { 61 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n"); 62 return -1; 63 } 64 int Ret = read(FD, Buf, Size); 65 int CloseStatus = close(FD); 66 if (CloseStatus) 67 return -1; 68 return Ret; 69 } 70 #endif 71 72 #if defined(i386) || defined(__i386__) || defined(__x86__) || \ 73 defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \ 74 defined(_M_X64) 75 76 enum VendorSignatures { 77 SIG_INTEL = 0x756e6547 /* Genu */, 78 SIG_AMD = 0x68747541 /* Auth */ 79 }; 80 81 enum ProcessorVendors { 82 VENDOR_INTEL = 1, 83 VENDOR_AMD, 84 VENDOR_OTHER, 85 VENDOR_MAX 86 }; 87 88 enum ProcessorTypes { 89 INTEL_ATOM = 1, 90 INTEL_CORE2, 91 INTEL_COREI7, 92 AMDFAM10H, 93 AMDFAM15H, 94 INTEL_i386, 95 INTEL_i486, 96 INTEL_PENTIUM, 97 INTEL_PENTIUM_PRO, 98 INTEL_PENTIUM_II, 99 INTEL_PENTIUM_III, 100 INTEL_PENTIUM_IV, 101 INTEL_PENTIUM_M, 102 INTEL_CORE_DUO, 103 INTEL_XEONPHI, 104 INTEL_X86_64, 105 INTEL_NOCONA, 106 INTEL_PRESCOTT, 107 AMD_i486, 108 AMDPENTIUM, 109 AMDATHLON, 110 AMDFAM14H, 111 AMDFAM16H, 112 CPU_TYPE_MAX 113 }; 114 115 enum ProcessorSubtypes { 116 INTEL_COREI7_NEHALEM = 1, 117 INTEL_COREI7_WESTMERE, 118 INTEL_COREI7_SANDYBRIDGE, 119 AMDFAM10H_BARCELONA, 120 AMDFAM10H_SHANGHAI, 121 AMDFAM10H_ISTANBUL, 122 AMDFAM15H_BDVER1, 123 AMDFAM15H_BDVER2, 124 INTEL_PENTIUM_MMX, 125 INTEL_CORE2_65, 126 INTEL_CORE2_45, 127 INTEL_COREI7_IVYBRIDGE, 128 INTEL_COREI7_HASWELL, 129 INTEL_COREI7_BROADWELL, 130 INTEL_COREI7_SKYLAKE, 131 INTEL_COREI7_SKYLAKE_AVX512, 132 INTEL_ATOM_BONNELL, 133 INTEL_ATOM_SILVERMONT, 134 INTEL_KNIGHTS_LANDING, 135 AMDPENTIUM_K6, 136 AMDPENTIUM_K62, 137 AMDPENTIUM_K63, 138 AMDPENTIUM_GEODE, 139 AMDATHLON_TBIRD, 140 AMDATHLON_MP, 141 AMDATHLON_XP, 142 AMDATHLON_K8SSE3, 143 AMDATHLON_OPTERON, 144 AMDATHLON_FX, 145 AMDATHLON_64, 146 AMD_BTVER1, 147 AMD_BTVER2, 148 AMDFAM15H_BDVER3, 149 AMDFAM15H_BDVER4, 150 CPU_SUBTYPE_MAX 151 }; 152 153 enum ProcessorFeatures { 154 FEATURE_CMOV = 0, 155 FEATURE_MMX, 156 FEATURE_POPCNT, 157 FEATURE_SSE, 158 FEATURE_SSE2, 159 FEATURE_SSE3, 160 FEATURE_SSSE3, 161 FEATURE_SSE4_1, 162 FEATURE_SSE4_2, 163 FEATURE_AVX, 164 FEATURE_AVX2, 165 FEATURE_AVX512, 166 FEATURE_AVX512SAVE, 167 FEATURE_MOVBE, 168 FEATURE_ADX, 169 FEATURE_EM64T 170 }; 171 172 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 173 /// the specified arguments. If we can't run cpuid on the host, return true. 174 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 175 unsigned *rECX, unsigned *rEDX) { 176 #if defined(__GNUC__) || defined(__clang__) 177 #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64) 178 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 179 asm("movq\t%%rbx, %%rsi\n\t" 180 "cpuid\n\t" 181 "xchgq\t%%rbx, %%rsi\n\t" 182 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 183 : "a"(value)); 184 return false; 185 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 186 asm("movl\t%%ebx, %%esi\n\t" 187 "cpuid\n\t" 188 "xchgl\t%%ebx, %%esi\n\t" 189 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 190 : "a"(value)); 191 return false; 192 // pedantic #else returns to appease -Wunreachable-code (so we don't generate 193 // postprocessed code that looks like "return true; return false;") 194 #else 195 return true; 196 #endif 197 #elif defined(_MSC_VER) 198 // The MSVC intrinsic is portable across x86 and x64. 199 int registers[4]; 200 __cpuid(registers, value); 201 *rEAX = registers[0]; 202 *rEBX = registers[1]; 203 *rECX = registers[2]; 204 *rEDX = registers[3]; 205 return false; 206 #else 207 return true; 208 #endif 209 } 210 211 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 212 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 213 /// return true. 214 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 215 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 216 unsigned *rEDX) { 217 #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64) 218 #if defined(__GNUC__) 219 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 220 asm("movq\t%%rbx, %%rsi\n\t" 221 "cpuid\n\t" 222 "xchgq\t%%rbx, %%rsi\n\t" 223 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 224 : "a"(value), "c"(subleaf)); 225 return false; 226 #elif defined(_MSC_VER) 227 int registers[4]; 228 __cpuidex(registers, value, subleaf); 229 *rEAX = registers[0]; 230 *rEBX = registers[1]; 231 *rECX = registers[2]; 232 *rEDX = registers[3]; 233 return false; 234 #else 235 return true; 236 #endif 237 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 238 #if defined(__GNUC__) 239 asm("movl\t%%ebx, %%esi\n\t" 240 "cpuid\n\t" 241 "xchgl\t%%ebx, %%esi\n\t" 242 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 243 : "a"(value), "c"(subleaf)); 244 return false; 245 #elif defined(_MSC_VER) 246 __asm { 247 mov eax,value 248 mov ecx,subleaf 249 cpuid 250 mov esi,rEAX 251 mov dword ptr [esi],eax 252 mov esi,rEBX 253 mov dword ptr [esi],ebx 254 mov esi,rECX 255 mov dword ptr [esi],ecx 256 mov esi,rEDX 257 mov dword ptr [esi],edx 258 } 259 return false; 260 #else 261 return true; 262 #endif 263 #else 264 return true; 265 #endif 266 } 267 268 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 269 #if defined(__GNUC__) 270 // Check xgetbv; this uses a .byte sequence instead of the instruction 271 // directly because older assemblers do not include support for xgetbv and 272 // there is no easy way to conditionally compile based on the assembler used. 273 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 274 return false; 275 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 276 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 277 *rEAX = Result; 278 *rEDX = Result >> 32; 279 return false; 280 #else 281 return true; 282 #endif 283 } 284 285 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 286 unsigned *Model) { 287 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 288 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 289 if (*Family == 6 || *Family == 0xf) { 290 if (*Family == 0xf) 291 // Examine extended family ID if family ID is F. 292 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 293 // Examine extended model ID if family ID is 6 or F. 294 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 295 } 296 } 297 298 static void 299 getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model, 300 unsigned int Brand_id, unsigned int Features, 301 unsigned *Type, unsigned *Subtype) { 302 if (Brand_id != 0) 303 return; 304 switch (Family) { 305 case 3: 306 *Type = INTEL_i386; 307 break; 308 case 4: 309 switch (Model) { 310 case 0: // Intel486 DX processors 311 case 1: // Intel486 DX processors 312 case 2: // Intel486 SX processors 313 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 314 // IntelDX2 processors 315 case 4: // Intel486 SL processor 316 case 5: // IntelSX2 processors 317 case 7: // Write-Back Enhanced IntelDX2 processors 318 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 319 default: 320 *Type = INTEL_i486; 321 break; 322 } 323 break; 324 case 5: 325 switch (Model) { 326 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 327 // Pentium processors (60, 66) 328 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 329 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 330 // 150, 166, 200) 331 case 3: // Pentium OverDrive processors for Intel486 processor-based 332 // systems 333 *Type = INTEL_PENTIUM; 334 break; 335 case 4: // Pentium OverDrive processor with MMX technology for Pentium 336 // processor (75, 90, 100, 120, 133), Pentium processor with 337 // MMX technology (166, 200) 338 *Type = INTEL_PENTIUM; 339 *Subtype = INTEL_PENTIUM_MMX; 340 break; 341 default: 342 *Type = INTEL_PENTIUM; 343 break; 344 } 345 break; 346 case 6: 347 switch (Model) { 348 case 0x01: // Pentium Pro processor 349 *Type = INTEL_PENTIUM_PRO; 350 break; 351 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 352 // model 03 353 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 354 // model 05, and Intel Celeron processor, model 05 355 case 0x06: // Celeron processor, model 06 356 *Type = INTEL_PENTIUM_II; 357 break; 358 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 359 // processor, model 07 360 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 361 // model 08, and Celeron processor, model 08 362 case 0x0a: // Pentium III Xeon processor, model 0Ah 363 case 0x0b: // Pentium III processor, model 0Bh 364 *Type = INTEL_PENTIUM_III; 365 break; 366 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 367 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 368 // 0Dh. All processors are manufactured using the 90 nm process. 369 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 370 // Integrated Processor with Intel QuickAssist Technology 371 *Type = INTEL_PENTIUM_M; 372 break; 373 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 374 // 0Eh. All processors are manufactured using the 65 nm process. 375 *Type = INTEL_CORE_DUO; 376 break; // yonah 377 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 378 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 379 // mobile processor, Intel Core 2 Extreme processor, Intel 380 // Pentium Dual-Core processor, Intel Xeon processor, model 381 // 0Fh. All processors are manufactured using the 65 nm process. 382 case 0x16: // Intel Celeron processor model 16h. All processors are 383 // manufactured using the 65 nm process 384 *Type = INTEL_CORE2; // "core2" 385 *Subtype = INTEL_CORE2_65; 386 break; 387 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 388 // 17h. All processors are manufactured using the 45 nm process. 389 // 390 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 391 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 392 // the 45 nm process. 393 *Type = INTEL_CORE2; // "penryn" 394 *Subtype = INTEL_CORE2_45; 395 break; 396 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 397 // processors are manufactured using the 45 nm process. 398 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 399 // As found in a Summer 2010 model iMac. 400 case 0x1f: 401 case 0x2e: // Nehalem EX 402 *Type = INTEL_COREI7; // "nehalem" 403 *Subtype = INTEL_COREI7_NEHALEM; 404 break; 405 case 0x25: // Intel Core i7, laptop version. 406 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 407 // processors are manufactured using the 32 nm process. 408 case 0x2f: // Westmere EX 409 *Type = INTEL_COREI7; // "westmere" 410 *Subtype = INTEL_COREI7_WESTMERE; 411 break; 412 case 0x2a: // Intel Core i7 processor. All processors are manufactured 413 // using the 32 nm process. 414 case 0x2d: 415 *Type = INTEL_COREI7; //"sandybridge" 416 *Subtype = INTEL_COREI7_SANDYBRIDGE; 417 break; 418 case 0x3a: 419 case 0x3e: // Ivy Bridge EP 420 *Type = INTEL_COREI7; // "ivybridge" 421 *Subtype = INTEL_COREI7_IVYBRIDGE; 422 break; 423 424 // Haswell: 425 case 0x3c: 426 case 0x3f: 427 case 0x45: 428 case 0x46: 429 *Type = INTEL_COREI7; // "haswell" 430 *Subtype = INTEL_COREI7_HASWELL; 431 break; 432 433 // Broadwell: 434 case 0x3d: 435 case 0x47: 436 case 0x4f: 437 case 0x56: 438 *Type = INTEL_COREI7; // "broadwell" 439 *Subtype = INTEL_COREI7_BROADWELL; 440 break; 441 442 // Skylake: 443 case 0x4e: 444 *Type = INTEL_COREI7; // "skylake-avx512" 445 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; 446 break; 447 case 0x5e: 448 *Type = INTEL_COREI7; // "skylake" 449 *Subtype = INTEL_COREI7_SKYLAKE; 450 break; 451 452 case 0x1c: // Most 45 nm Intel Atom processors 453 case 0x26: // 45 nm Atom Lincroft 454 case 0x27: // 32 nm Atom Medfield 455 case 0x35: // 32 nm Atom Midview 456 case 0x36: // 32 nm Atom Midview 457 *Type = INTEL_ATOM; 458 *Subtype = INTEL_ATOM_BONNELL; 459 break; // "bonnell" 460 461 // Atom Silvermont codes from the Intel software optimization guide. 462 case 0x37: 463 case 0x4a: 464 case 0x4d: 465 case 0x5a: 466 case 0x5d: 467 case 0x4c: // really airmont 468 *Type = INTEL_ATOM; 469 *Subtype = INTEL_ATOM_SILVERMONT; 470 break; // "silvermont" 471 472 case 0x57: 473 *Type = INTEL_XEONPHI; // knl 474 *Subtype = INTEL_KNIGHTS_LANDING; 475 break; 476 477 default: // Unknown family 6 CPU, try to guess. 478 if (Features & (1 << FEATURE_AVX512)) { 479 *Type = INTEL_XEONPHI; // knl 480 *Subtype = INTEL_KNIGHTS_LANDING; 481 break; 482 } 483 if (Features & (1 << FEATURE_ADX)) { 484 *Type = INTEL_COREI7; 485 *Subtype = INTEL_COREI7_BROADWELL; 486 break; 487 } 488 if (Features & (1 << FEATURE_AVX2)) { 489 *Type = INTEL_COREI7; 490 *Subtype = INTEL_COREI7_HASWELL; 491 break; 492 } 493 if (Features & (1 << FEATURE_AVX)) { 494 *Type = INTEL_COREI7; 495 *Subtype = INTEL_COREI7_SANDYBRIDGE; 496 break; 497 } 498 if (Features & (1 << FEATURE_SSE4_2)) { 499 if (Features & (1 << FEATURE_MOVBE)) { 500 *Type = INTEL_ATOM; 501 *Subtype = INTEL_ATOM_SILVERMONT; 502 } else { 503 *Type = INTEL_COREI7; 504 *Subtype = INTEL_COREI7_NEHALEM; 505 } 506 break; 507 } 508 if (Features & (1 << FEATURE_SSE4_1)) { 509 *Type = INTEL_CORE2; // "penryn" 510 *Subtype = INTEL_CORE2_45; 511 break; 512 } 513 if (Features & (1 << FEATURE_SSSE3)) { 514 if (Features & (1 << FEATURE_MOVBE)) { 515 *Type = INTEL_ATOM; 516 *Subtype = INTEL_ATOM_BONNELL; // "bonnell" 517 } else { 518 *Type = INTEL_CORE2; // "core2" 519 *Subtype = INTEL_CORE2_65; 520 } 521 break; 522 } 523 if (Features & (1 << FEATURE_EM64T)) { 524 *Type = INTEL_X86_64; 525 break; // x86-64 526 } 527 if (Features & (1 << FEATURE_SSE2)) { 528 *Type = INTEL_PENTIUM_M; 529 break; 530 } 531 if (Features & (1 << FEATURE_SSE)) { 532 *Type = INTEL_PENTIUM_III; 533 break; 534 } 535 if (Features & (1 << FEATURE_MMX)) { 536 *Type = INTEL_PENTIUM_II; 537 break; 538 } 539 *Type = INTEL_PENTIUM_PRO; 540 break; 541 } 542 break; 543 case 15: { 544 switch (Model) { 545 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 546 // model 00h and manufactured using the 0.18 micron process. 547 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 548 // processor MP, and Intel Celeron processor. All processors are 549 // model 01h and manufactured using the 0.18 micron process. 550 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 551 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 552 // processor, and Mobile Intel Celeron processor. All processors 553 // are model 02h and manufactured using the 0.13 micron process. 554 *Type = 555 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 556 break; 557 558 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 559 // processor. All processors are model 03h and manufactured using 560 // the 90 nm process. 561 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 562 // Pentium D processor, Intel Xeon processor, Intel Xeon 563 // processor MP, Intel Celeron D processor. All processors are 564 // model 04h and manufactured using the 90 nm process. 565 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 566 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 567 // MP, Intel Celeron D processor. All processors are model 06h 568 // and manufactured using the 65 nm process. 569 *Type = 570 ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT); 571 break; 572 573 default: 574 *Type = 575 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); 576 break; 577 } 578 break; 579 } 580 default: 581 break; /*"generic"*/ 582 } 583 } 584 585 static void getAMDProcessorTypeAndSubtype(unsigned int Family, 586 unsigned int Model, 587 unsigned int Features, 588 unsigned *Type, 589 unsigned *Subtype) { 590 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 591 // appears to be no way to generate the wide variety of AMD-specific targets 592 // from the information returned from CPUID. 593 switch (Family) { 594 case 4: 595 *Type = AMD_i486; 596 break; 597 case 5: 598 *Type = AMDPENTIUM; 599 switch (Model) { 600 case 6: 601 case 7: 602 *Subtype = AMDPENTIUM_K6; 603 break; // "k6" 604 case 8: 605 *Subtype = AMDPENTIUM_K62; 606 break; // "k6-2" 607 case 9: 608 case 13: 609 *Subtype = AMDPENTIUM_K63; 610 break; // "k6-3" 611 case 10: 612 *Subtype = AMDPENTIUM_GEODE; 613 break; // "geode" 614 } 615 break; 616 case 6: 617 *Type = AMDATHLON; 618 switch (Model) { 619 case 4: 620 *Subtype = AMDATHLON_TBIRD; 621 break; // "athlon-tbird" 622 case 6: 623 case 7: 624 case 8: 625 *Subtype = AMDATHLON_MP; 626 break; // "athlon-mp" 627 case 10: 628 *Subtype = AMDATHLON_XP; 629 break; // "athlon-xp" 630 } 631 break; 632 case 15: 633 *Type = AMDATHLON; 634 if (Features & (1 << FEATURE_SSE3)) { 635 *Subtype = AMDATHLON_K8SSE3; 636 break; // "k8-sse3" 637 } 638 switch (Model) { 639 case 1: 640 *Subtype = AMDATHLON_OPTERON; 641 break; // "opteron" 642 case 5: 643 *Subtype = AMDATHLON_FX; 644 break; // "athlon-fx"; also opteron 645 default: 646 *Subtype = AMDATHLON_64; 647 break; // "athlon64" 648 } 649 break; 650 case 16: 651 *Type = AMDFAM10H; // "amdfam10" 652 switch (Model) { 653 case 2: 654 *Subtype = AMDFAM10H_BARCELONA; 655 break; 656 case 4: 657 *Subtype = AMDFAM10H_SHANGHAI; 658 break; 659 case 8: 660 *Subtype = AMDFAM10H_ISTANBUL; 661 break; 662 } 663 break; 664 case 20: 665 *Type = AMDFAM14H; 666 *Subtype = AMD_BTVER1; 667 break; // "btver1"; 668 case 21: 669 *Type = AMDFAM15H; 670 if (!(Features & 671 (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback. 672 *Subtype = AMD_BTVER1; 673 break; // "btver1" 674 } 675 if (Model >= 0x50 && Model <= 0x6f) { 676 *Subtype = AMDFAM15H_BDVER4; 677 break; // "bdver4"; 50h-6Fh: Excavator 678 } 679 if (Model >= 0x30 && Model <= 0x3f) { 680 *Subtype = AMDFAM15H_BDVER3; 681 break; // "bdver3"; 30h-3Fh: Steamroller 682 } 683 if (Model >= 0x10 && Model <= 0x1f) { 684 *Subtype = AMDFAM15H_BDVER2; 685 break; // "bdver2"; 10h-1Fh: Piledriver 686 } 687 if (Model <= 0x0f) { 688 *Subtype = AMDFAM15H_BDVER1; 689 break; // "bdver1"; 00h-0Fh: Bulldozer 690 } 691 break; 692 case 22: 693 *Type = AMDFAM16H; 694 if (!(Features & 695 (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback. 696 *Subtype = AMD_BTVER1; 697 break; // "btver1"; 698 } 699 *Subtype = AMD_BTVER2; 700 break; // "btver2" 701 default: 702 break; // "generic" 703 } 704 } 705 706 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, 707 unsigned MaxLeaf) { 708 unsigned Features = 0; 709 unsigned int EAX, EBX; 710 Features |= (((EDX >> 23) & 1) << FEATURE_MMX); 711 Features |= (((EDX >> 25) & 1) << FEATURE_SSE); 712 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); 713 Features |= (((ECX >> 0) & 1) << FEATURE_SSE3); 714 Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3); 715 Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1); 716 Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2); 717 Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE); 718 719 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 720 // indicates that the AVX registers will be saved and restored on context 721 // switch, then we have full AVX support. 722 const unsigned AVXBits = (1 << 27) | (1 << 28); 723 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 724 ((EAX & 0x6) == 0x6); 725 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 726 bool HasLeaf7 = 727 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 728 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); 729 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); 730 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); 731 Features |= (HasAVX << FEATURE_AVX); 732 Features |= (HasAVX2 << FEATURE_AVX2); 733 Features |= (HasAVX512 << FEATURE_AVX512); 734 Features |= (HasAVX512Save << FEATURE_AVX512SAVE); 735 Features |= (HasADX << FEATURE_ADX); 736 737 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 738 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); 739 return Features; 740 } 741 742 StringRef sys::getHostCPUName() { 743 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 744 unsigned MaxLeaf, Vendor; 745 746 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) 747 return "generic"; 748 if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 749 return "generic"; 750 751 unsigned Brand_id = EBX & 0xff; 752 unsigned Family = 0, Model = 0; 753 unsigned Features = 0; 754 detectX86FamilyModel(EAX, &Family, &Model); 755 Features = getAvailableFeatures(ECX, EDX, MaxLeaf); 756 757 unsigned Type; 758 unsigned Subtype; 759 760 if (Vendor == SIG_INTEL) { 761 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type, 762 &Subtype); 763 switch (Type) { 764 case INTEL_i386: 765 return "i386"; 766 case INTEL_i486: 767 return "i486"; 768 case INTEL_PENTIUM: 769 if (Subtype == INTEL_PENTIUM_MMX) 770 return "pentium-mmx"; 771 return "pentium"; 772 case INTEL_PENTIUM_PRO: 773 return "pentiumpro"; 774 case INTEL_PENTIUM_II: 775 return "pentium2"; 776 case INTEL_PENTIUM_III: 777 return "pentium3"; 778 case INTEL_PENTIUM_IV: 779 return "pentium4"; 780 case INTEL_PENTIUM_M: 781 return "pentium-m"; 782 case INTEL_CORE_DUO: 783 return "yonah"; 784 case INTEL_CORE2: 785 switch (Subtype) { 786 case INTEL_CORE2_65: 787 return "core2"; 788 case INTEL_CORE2_45: 789 return "penryn"; 790 default: 791 return "core2"; 792 } 793 case INTEL_COREI7: 794 switch (Subtype) { 795 case INTEL_COREI7_NEHALEM: 796 return "nehalem"; 797 case INTEL_COREI7_WESTMERE: 798 return "westmere"; 799 case INTEL_COREI7_SANDYBRIDGE: 800 return "sandybridge"; 801 case INTEL_COREI7_IVYBRIDGE: 802 return "ivybridge"; 803 case INTEL_COREI7_HASWELL: 804 return "haswell"; 805 case INTEL_COREI7_BROADWELL: 806 return "broadwell"; 807 case INTEL_COREI7_SKYLAKE: 808 return "skylake"; 809 case INTEL_COREI7_SKYLAKE_AVX512: 810 return "skylake-avx512"; 811 default: 812 return "corei7"; 813 } 814 case INTEL_ATOM: 815 switch (Subtype) { 816 case INTEL_ATOM_BONNELL: 817 return "bonnell"; 818 case INTEL_ATOM_SILVERMONT: 819 return "silvermont"; 820 default: 821 return "atom"; 822 } 823 case INTEL_XEONPHI: 824 return "knl"; /*update for more variants added*/ 825 case INTEL_X86_64: 826 return "x86-64"; 827 case INTEL_NOCONA: 828 return "nocona"; 829 case INTEL_PRESCOTT: 830 return "prescott"; 831 default: 832 return "generic"; 833 } 834 } else if (Vendor == SIG_AMD) { 835 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 836 switch (Type) { 837 case AMD_i486: 838 return "i486"; 839 case AMDPENTIUM: 840 switch (Subtype) { 841 case AMDPENTIUM_K6: 842 return "k6"; 843 case AMDPENTIUM_K62: 844 return "k6-2"; 845 case AMDPENTIUM_K63: 846 return "k6-3"; 847 case AMDPENTIUM_GEODE: 848 return "geode"; 849 default: 850 return "pentium"; 851 } 852 case AMDATHLON: 853 switch (Subtype) { 854 case AMDATHLON_TBIRD: 855 return "athlon-tbird"; 856 case AMDATHLON_MP: 857 return "athlon-mp"; 858 case AMDATHLON_XP: 859 return "athlon-xp"; 860 case AMDATHLON_K8SSE3: 861 return "k8-sse3"; 862 case AMDATHLON_OPTERON: 863 return "opteron"; 864 case AMDATHLON_FX: 865 return "athlon-fx"; 866 case AMDATHLON_64: 867 return "athlon64"; 868 default: 869 return "athlon"; 870 } 871 case AMDFAM10H: 872 if(Subtype == AMDFAM10H_BARCELONA) 873 return "barcelona"; 874 return "amdfam10"; 875 case AMDFAM14H: 876 return "btver1"; 877 case AMDFAM15H: 878 switch (Subtype) { 879 case AMDFAM15H_BDVER1: 880 return "bdver1"; 881 case AMDFAM15H_BDVER2: 882 return "bdver2"; 883 case AMDFAM15H_BDVER3: 884 return "bdver3"; 885 case AMDFAM15H_BDVER4: 886 return "bdver4"; 887 case AMD_BTVER1: 888 return "btver1"; 889 default: 890 return "amdfam15"; 891 } 892 case AMDFAM16H: 893 switch (Subtype) { 894 case AMD_BTVER1: 895 return "btver1"; 896 case AMD_BTVER2: 897 return "btver2"; 898 default: 899 return "amdfam16"; 900 } 901 default: 902 return "generic"; 903 } 904 } 905 return "generic"; 906 } 907 908 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 909 StringRef sys::getHostCPUName() { 910 host_basic_info_data_t hostInfo; 911 mach_msg_type_number_t infoCount; 912 913 infoCount = HOST_BASIC_INFO_COUNT; 914 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 915 &infoCount); 916 917 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 918 return "generic"; 919 920 switch (hostInfo.cpu_subtype) { 921 case CPU_SUBTYPE_POWERPC_601: 922 return "601"; 923 case CPU_SUBTYPE_POWERPC_602: 924 return "602"; 925 case CPU_SUBTYPE_POWERPC_603: 926 return "603"; 927 case CPU_SUBTYPE_POWERPC_603e: 928 return "603e"; 929 case CPU_SUBTYPE_POWERPC_603ev: 930 return "603ev"; 931 case CPU_SUBTYPE_POWERPC_604: 932 return "604"; 933 case CPU_SUBTYPE_POWERPC_604e: 934 return "604e"; 935 case CPU_SUBTYPE_POWERPC_620: 936 return "620"; 937 case CPU_SUBTYPE_POWERPC_750: 938 return "750"; 939 case CPU_SUBTYPE_POWERPC_7400: 940 return "7400"; 941 case CPU_SUBTYPE_POWERPC_7450: 942 return "7450"; 943 case CPU_SUBTYPE_POWERPC_970: 944 return "970"; 945 default:; 946 } 947 948 return "generic"; 949 } 950 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 951 StringRef sys::getHostCPUName() { 952 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 953 // and so we must use an operating-system interface to determine the current 954 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 955 const char *generic = "generic"; 956 957 // The cpu line is second (after the 'processor: 0' line), so if this 958 // buffer is too small then something has changed (or is wrong). 959 char buffer[1024]; 960 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 961 if (CPUInfoSize == -1) 962 return generic; 963 964 const char *CPUInfoStart = buffer; 965 const char *CPUInfoEnd = buffer + CPUInfoSize; 966 967 const char *CIP = CPUInfoStart; 968 969 const char *CPUStart = 0; 970 size_t CPULen = 0; 971 972 // We need to find the first line which starts with cpu, spaces, and a colon. 973 // After the colon, there may be some additional spaces and then the cpu type. 974 while (CIP < CPUInfoEnd && CPUStart == 0) { 975 if (CIP < CPUInfoEnd && *CIP == '\n') 976 ++CIP; 977 978 if (CIP < CPUInfoEnd && *CIP == 'c') { 979 ++CIP; 980 if (CIP < CPUInfoEnd && *CIP == 'p') { 981 ++CIP; 982 if (CIP < CPUInfoEnd && *CIP == 'u') { 983 ++CIP; 984 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 985 ++CIP; 986 987 if (CIP < CPUInfoEnd && *CIP == ':') { 988 ++CIP; 989 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 990 ++CIP; 991 992 if (CIP < CPUInfoEnd) { 993 CPUStart = CIP; 994 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 995 *CIP != ',' && *CIP != '\n')) 996 ++CIP; 997 CPULen = CIP - CPUStart; 998 } 999 } 1000 } 1001 } 1002 } 1003 1004 if (CPUStart == 0) 1005 while (CIP < CPUInfoEnd && *CIP != '\n') 1006 ++CIP; 1007 } 1008 1009 if (CPUStart == 0) 1010 return generic; 1011 1012 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 1013 .Case("604e", "604e") 1014 .Case("604", "604") 1015 .Case("7400", "7400") 1016 .Case("7410", "7400") 1017 .Case("7447", "7400") 1018 .Case("7455", "7450") 1019 .Case("G4", "g4") 1020 .Case("POWER4", "970") 1021 .Case("PPC970FX", "970") 1022 .Case("PPC970MP", "970") 1023 .Case("G5", "g5") 1024 .Case("POWER5", "g5") 1025 .Case("A2", "a2") 1026 .Case("POWER6", "pwr6") 1027 .Case("POWER7", "pwr7") 1028 .Case("POWER8", "pwr8") 1029 .Case("POWER8E", "pwr8") 1030 .Case("POWER9", "pwr9") 1031 .Default(generic); 1032 } 1033 #elif defined(__linux__) && defined(__arm__) 1034 StringRef sys::getHostCPUName() { 1035 // The cpuid register on arm is not accessible from user space. On Linux, 1036 // it is exposed through the /proc/cpuinfo file. 1037 1038 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line 1039 // in all cases. 1040 char buffer[1024]; 1041 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1042 if (CPUInfoSize == -1) 1043 return "generic"; 1044 1045 StringRef Str(buffer, CPUInfoSize); 1046 1047 SmallVector<StringRef, 32> Lines; 1048 Str.split(Lines, "\n"); 1049 1050 // Look for the CPU implementer line. 1051 StringRef Implementer; 1052 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1053 if (Lines[I].startswith("CPU implementer")) 1054 Implementer = Lines[I].substr(15).ltrim("\t :"); 1055 1056 if (Implementer == "0x41") // ARM Ltd. 1057 // Look for the CPU part line. 1058 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1059 if (Lines[I].startswith("CPU part")) 1060 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 1061 // values correspond to the "Part number" in the CP15/c0 register. The 1062 // contents are specified in the various processor manuals. 1063 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 1064 .Case("0x926", "arm926ej-s") 1065 .Case("0xb02", "mpcore") 1066 .Case("0xb36", "arm1136j-s") 1067 .Case("0xb56", "arm1156t2-s") 1068 .Case("0xb76", "arm1176jz-s") 1069 .Case("0xc08", "cortex-a8") 1070 .Case("0xc09", "cortex-a9") 1071 .Case("0xc0f", "cortex-a15") 1072 .Case("0xc20", "cortex-m0") 1073 .Case("0xc23", "cortex-m3") 1074 .Case("0xc24", "cortex-m4") 1075 .Default("generic"); 1076 1077 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 1078 // Look for the CPU part line. 1079 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1080 if (Lines[I].startswith("CPU part")) 1081 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 1082 // values correspond to the "Part number" in the CP15/c0 register. The 1083 // contents are specified in the various processor manuals. 1084 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 1085 .Case("0x06f", "krait") // APQ8064 1086 .Default("generic"); 1087 1088 return "generic"; 1089 } 1090 #elif defined(__linux__) && defined(__s390x__) 1091 StringRef sys::getHostCPUName() { 1092 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 1093 1094 // The "processor 0:" line comes after a fair amount of other information, 1095 // including a cache breakdown, but this should be plenty. 1096 char buffer[2048]; 1097 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1098 if (CPUInfoSize == -1) 1099 return "generic"; 1100 1101 StringRef Str(buffer, CPUInfoSize); 1102 SmallVector<StringRef, 32> Lines; 1103 Str.split(Lines, "\n"); 1104 1105 // Look for the CPU features. 1106 SmallVector<StringRef, 32> CPUFeatures; 1107 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1108 if (Lines[I].startswith("features")) { 1109 size_t Pos = Lines[I].find(":"); 1110 if (Pos != StringRef::npos) { 1111 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 1112 break; 1113 } 1114 } 1115 1116 // We need to check for the presence of vector support independently of 1117 // the machine type, since we may only use the vector register set when 1118 // supported by the kernel (and hypervisor). 1119 bool HaveVectorSupport = false; 1120 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1121 if (CPUFeatures[I] == "vx") 1122 HaveVectorSupport = true; 1123 } 1124 1125 // Now check the processor machine type. 1126 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 1127 if (Lines[I].startswith("processor ")) { 1128 size_t Pos = Lines[I].find("machine = "); 1129 if (Pos != StringRef::npos) { 1130 Pos += sizeof("machine = ") - 1; 1131 unsigned int Id; 1132 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 1133 if (Id >= 2964 && HaveVectorSupport) 1134 return "z13"; 1135 if (Id >= 2827) 1136 return "zEC12"; 1137 if (Id >= 2817) 1138 return "z196"; 1139 } 1140 } 1141 break; 1142 } 1143 } 1144 1145 return "generic"; 1146 } 1147 #else 1148 StringRef sys::getHostCPUName() { return "generic"; } 1149 #endif 1150 1151 #if defined(i386) || defined(__i386__) || defined(__x86__) || \ 1152 defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \ 1153 defined(_M_X64) 1154 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1155 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1156 unsigned MaxLevel; 1157 union { 1158 unsigned u[3]; 1159 char c[12]; 1160 } text; 1161 1162 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1163 MaxLevel < 1) 1164 return false; 1165 1166 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1167 1168 Features["cmov"] = (EDX >> 15) & 1; 1169 Features["mmx"] = (EDX >> 23) & 1; 1170 Features["sse"] = (EDX >> 25) & 1; 1171 Features["sse2"] = (EDX >> 26) & 1; 1172 Features["sse3"] = (ECX >> 0) & 1; 1173 Features["ssse3"] = (ECX >> 9) & 1; 1174 Features["sse4.1"] = (ECX >> 19) & 1; 1175 Features["sse4.2"] = (ECX >> 20) & 1; 1176 1177 Features["pclmul"] = (ECX >> 1) & 1; 1178 Features["cx16"] = (ECX >> 13) & 1; 1179 Features["movbe"] = (ECX >> 22) & 1; 1180 Features["popcnt"] = (ECX >> 23) & 1; 1181 Features["aes"] = (ECX >> 25) & 1; 1182 Features["rdrnd"] = (ECX >> 30) & 1; 1183 1184 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1185 // indicates that the AVX registers will be saved and restored on context 1186 // switch, then we have full AVX support. 1187 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1188 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1189 Features["avx"] = HasAVXSave; 1190 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1191 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1192 1193 // Only enable XSAVE if OS has enabled support for saving YMM state. 1194 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1195 1196 // AVX512 requires additional context to be saved by the OS. 1197 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1198 1199 unsigned MaxExtLevel; 1200 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1201 1202 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1203 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1204 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1205 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1206 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1207 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1208 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1209 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1210 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1211 1212 bool HasLeaf7 = 1213 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1214 1215 // AVX2 is only supported if we have the OS save support from AVX. 1216 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1217 1218 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1219 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1220 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1221 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1); 1222 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1223 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1224 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1225 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1226 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1227 Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1); 1228 Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1); 1229 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1230 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1231 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1232 1233 // AVX512 is only supported if the OS supports the context save for it. 1234 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1235 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1236 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1237 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1238 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1239 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1240 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1241 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1242 1243 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1244 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1245 // Enable protection keys 1246 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1247 1248 bool HasLeafD = MaxLevel >= 0xd && 1249 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1250 1251 // Only enable XSAVE if OS has enabled support for saving YMM state. 1252 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1253 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1254 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1255 1256 return true; 1257 } 1258 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1259 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1260 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line 1261 // in all cases. 1262 char buffer[1024]; 1263 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 1264 if (CPUInfoSize == -1) 1265 return false; 1266 1267 StringRef Str(buffer, CPUInfoSize); 1268 1269 SmallVector<StringRef, 32> Lines; 1270 Str.split(Lines, "\n"); 1271 1272 SmallVector<StringRef, 32> CPUFeatures; 1273 1274 // Look for the CPU features. 1275 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1276 if (Lines[I].startswith("Features")) { 1277 Lines[I].split(CPUFeatures, ' '); 1278 break; 1279 } 1280 1281 #if defined(__aarch64__) 1282 // Keep track of which crypto features we have seen 1283 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1284 uint32_t crypto = 0; 1285 #endif 1286 1287 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1288 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1289 #if defined(__aarch64__) 1290 .Case("asimd", "neon") 1291 .Case("fp", "fp-armv8") 1292 .Case("crc32", "crc") 1293 #else 1294 .Case("half", "fp16") 1295 .Case("neon", "neon") 1296 .Case("vfpv3", "vfp3") 1297 .Case("vfpv3d16", "d16") 1298 .Case("vfpv4", "vfp4") 1299 .Case("idiva", "hwdiv-arm") 1300 .Case("idivt", "hwdiv") 1301 #endif 1302 .Default(""); 1303 1304 #if defined(__aarch64__) 1305 // We need to check crypto separately since we need all of the crypto 1306 // extensions to enable the subtarget feature 1307 if (CPUFeatures[I] == "aes") 1308 crypto |= CAP_AES; 1309 else if (CPUFeatures[I] == "pmull") 1310 crypto |= CAP_PMULL; 1311 else if (CPUFeatures[I] == "sha1") 1312 crypto |= CAP_SHA1; 1313 else if (CPUFeatures[I] == "sha2") 1314 crypto |= CAP_SHA2; 1315 #endif 1316 1317 if (LLVMFeatureStr != "") 1318 Features[LLVMFeatureStr] = true; 1319 } 1320 1321 #if defined(__aarch64__) 1322 // If we have all crypto bits we can add the feature 1323 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1324 Features["crypto"] = true; 1325 #endif 1326 1327 return true; 1328 } 1329 #else 1330 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1331 #endif 1332 1333 std::string sys::getProcessTriple() { 1334 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); 1335 1336 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1337 PT = PT.get64BitArchVariant(); 1338 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1339 PT = PT.get32BitArchVariant(); 1340 1341 return PT.str(); 1342 } 1343
